EL115 Logic Circuit Design Tutorial 4

							EL115 Logic Circuit Design: Tutorial 4

1)   Design a synchronous modulo-7 counter and implement it using positive edge-triggered D-type bistables and
      standard logic gates (AND, OR or NOT) only.

2)   Design a synchronous modulo-7 counter for implementation using positive edge-triggered T-type bistables
      and standard logic gates (AND, OR or NOT) only.

3)   Design an asynchronous modulo-7 counter and implement it using positive edge-triggered D-type bistables
      and standard logic gates (AND, NAND, OR, NOR or NOT) only.

4)   Compare and contrast the implementation of a synchronous modulo-7 counter using positive edge-triggered
      D-types and T-types and an asynchronous modulo-7 counter using negative edge-triggered D-types.

5)   Design a system which operates as either a 2-bit shift register or as a 2-bit binary counter. The signal S/C is
      `1' to select action as a shift register, accepting a data input as Q0 and shifting Q0 to Q1, and `0' to select the
      counter, where Q1Q0 count up in natural binary. Specify your design using an ASM chart and implement it
      using positive edge-triggered D-type bistables and standard logic gates (AND, OR or NOT). Given that for
      the bistables TSU = 10 ns, TH = 2 ns, and TPHL = 13 ns and TPLH = 12 ns, for any combinational gate TPHL =
      11 ns and TPLH = 12 ns, estimate the maximum clock frequency at which your circuit will operate reliably.