Engineering ELEC 4609 - Integrated Circuit Design and Fabrication by she20208


									                                               Carleton University
                                             Department of Electronics
             Engineering ELEC 4609 – Integrated Circuit Design and Fabrication
                                  Course Outline -------------------- Fall 2009
Instructor:              Steven McGarry           ME5158          email:

TAs:                     Peter Chyurlia           ME5135          email:
                         Ryan Griffin             ME5169          email:

Marking scheme:          Final exam 50% - The final exam will be three hours and closed book. An equation/constant
                         sheet will be given, a copy of which will be available on the website. Programmable
                         calculators, defined as a calculator that can store program steps or text at any level of
                         sophistication, will not be allowed in the final exam.
                         IC design project 50% - A major component of ELEC4609 is the design and testing of a
                         simple integrated circuit in nMOS technology. We will attempt to fabricate the circuits here at
                         Carleton, and return finished silicon chips for testing before the end of term. Students will
                         normally work in pairs on the project, but must submit individual reports. In order to allow
                         time for chip fabrication, there will be tight deadlines for design completion in mid-October.
                         A complete layout with full supporting simulation results must be submitted at this time to
                         obtain credit for the course. A comprehensive report, due towards the end of term, is expected
                         on this project.
                         A passing grade in the project is required to obtain credit for course!

Course web site:
                         All course material (lecture notes, labs, examples, etc.) will be available on the course web
                         site. (For the most part, courtesy of Prof. Tarr.)

Assignments/Labs: Much of the design work in this course is done outside scheduled lab periods. Lab periods
                         provide an opportunity to have TAs review and comment on your work. Lab attendance is
                         therefore not compulsory. In addition to the term design project, there will be assignments
                         posted (not marked, but covered on the final exam) on CMOS layout and the fundamentals of
                         CMOS process design.

Health and Safety: See for general guidelines.
                         Normal precautions in working with low-voltage electrical equipment must be taken when
                         testing projects.
                         Students wishing to assist in multiproject chip fabrication must complete special training.

Basic MOS IC Design Concepts - Basic nMOS structure and process flow. Relationship between layout and cross-
section. Design rules. BasicCMOS structure and process flow.

MOS Circuit Building Blocks - nMOS inverter: transfer characteristic, ratioing, noise margin, rise and fall times.
Advantages of CMOS. NAND and NOR gates. Transmission gates. Dynamic logic. Bootstrapping. PLAs. Input
protection. Driving large capacitive loads with output buffers. Latch-up. Introduction to analog CMOS circuits:
differential amplifiers, source follower buffers, current mirrors, device matching, temperature compensation.

MOS Process Technology Steps - Overview of the processes required to fabricate a MOS IC: oxidation, ion
implantation, diffusion, thin film deposition, photolithography and etching. Integration of basic steps into a simple
CMOS process flow.

Advanced CMOS Technology (as time permits) - Issues in the design of deep submicron MOSFETs. Causes and
consequences of short-channel and hot-carrier effects, and techniques for their suppression. The ITRS roadmap and the
future of microelectronics.
Final Exam Availability
In keeping with Faculty of Engineering policy, students are not entitled to view the results of their final exam, which is
considered to serve as an evaluation of performance rather than a pedagogical tool.

Academic Accommodation
You may need special arrangements to meet your academic obligations during the term. For an accommodation
request the processes are as follows:
Pregnancy obligation: write to me with any requests for academic accommodation during the first two weeks of class,
or as soon as possible after the need for accommodation is known to exist. For more details visit the Equity Services
Religious obligation: write to me with any requests for academic accommodation during the first two weeks of class,
or as soon as possible after the need for accommodation is known to exist. For more details visit the Equity Services
Students with disabilities requiring academic accommodations: in this course must register with the Paul Menton
Centre for Students with Disabilities (PMC) for a formal evaluation of disability-related needs. Documented
disabilities could include but are not limited to mobility/physical impairments, specific Learning Disabilities (LD),
psychiatric/psychological disabilities, sensory disabilities, Attention Deficit Hyperactivity Disorder (ADHD), and
chronic medical conditions. Registered PMC students are required to contact the PMC, 613-520-6608, every term to
ensure that I receive your Letter of Accommodation, no later than two weeks before the first assignment is due or the
first in-class test/midterm requiring accommodations. If you only require accommodations for your formally scheduled
exam(s) in this course, please submit your request for accommodations to PMC by the last official day to withdraw
from classes in each term. For more details visit the PMC website:

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