Improved PCB Circuit Design With User Definable Pinouts

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                      Improved PCB Circuit Design
                      With User Definable Pinouts
                                                                                                                         by Martin Hart,
                                                                                                                  Mirror Semiconductor

                      Co-design is a compelling tech-       What if you could design ultimate designers who have the task of lay-
                      nique to empower printed circuit      boards simply by instructing the ing out the PC board. The board
                      board designers to concurrently       semiconductor supplier to change designer has no ability to change
                      optimise board-level designs by       the pinouts of chips according any aspect of the IC package or to
                      re-mapping the pinouts of legacy      to your wishes? Today, that wish re-map the pinout and are thus are
                      die. Such EDA co-design software      seems like a fairy-tale. The real- forced to accept the chips that are
                      seamlessly delivers instructions to   ity is that
                      wire bonding machines via the In-     the semi-
                      ternet (or by conventional means)     conductor
                      providing long-awaited benefits.       chip      de-
                      In the current Chip Packaging         sign team
                      1.0 environment, there is no com-     decides
                      munication channel for board de-      what type
                      signers to collaborate with chip      of IC pack-
                      designers. However, there is an       age to use
                      opportunity to change the way         and how to
                      boards are designed in the future     assign the
                      Chip Packaging 2.0 world. The         p i n o u t s . Figure 2 – EDA software iterates UDPo - User Definable
                      ‘throw it over the wall’ approach     Legacy IC Package pinouts until PC board layout is optimised
                      is not the best way to design. The    package
                      question is ‘what if’ board design-   pinouts are cast in stone and de- thrown to them. As a result, the
                      ers were empowered to re-map          fined in the chipmaker’s datash- board designer is currently unable
                      legacy package pinouts (without       eets. While some efforts exist to to develop an ultimate PC board de-
                      changing the performance of the       co-design new silicon designs and sign. This current method is called
                      silicon) in order to design opti-     substrates (example: multichip Chip Packaging 1.0 (Figure 1).
                      mum PC boards? Designers fac-         modules, PoP and SiP), currently
                      ing daily challenges shall have an    there is no method to change the While there is a push to make co-
                      active voice in providing enlight-    pinouts of off-the-shelf die (wafers) design mainstream, there is lit-
                      ening answers to that question.       according to the whim of the PC tle motivation for the IC design
                      Another question is what will it      board designer. There is no com- team to change. However, some
                      take to compel the semiconductor      munication channel in place be- improvements could be possible if
                      community to rally to the chal-       tween the chip design team and the IC packaging were to adopt a new
                      lenge of co-design with the new       PC board design team. IC packages approach that offers more design
                      UDPo technology?                      are ‘tossed over-the-wall’ to board freedom to the PC board designer
  P A C K A G I N G

                                                                                                   in the so called Chip Packaging 2.0
                      Figure 1 – No collaboration between IC chip design team and PC board         environment. The new approach is
                      designer to define the package pinout                                         compelling and worthy of consid-
                                                                                                   eration. In this new approach the
                                                                                                   PCB designer will use their EDA
                                                                                                   software to iterate the IC pack-
                                                                                                   age pinouts of legacy IC die while
                                                                                                   simultaneously optimising the
                                                                                                   board’s routing (Figure 2). This
                                                                                                   new approach to semiconductor
  A D V A N C E D

                                                                                                   packaging is referred to as ‘User
                                                                                                   Definable Pinout’ (UDPo), which
                                                                                                   empowers board designers to re-
                                                                                                   map package pinouts of legacy
                                                                                                   chips using EDA software tools.
                                                                                                   The optimised chip is wire-bonded
                                                                                                   by the chipmaker according to the
                                                                                                   pinout instructions of the PC board

                      OnBoard Technology April 2008 - page 52                                     
designer. Once defined, the UDPo        using insulated bonding wire to
chip is added to the PC Board BOM      prevent shorting inside the IC
(Bill of Materials) for mounting on    package. The dream of creating
PC boards using normal SMT as-         single layer boards is within reach
sembly practices.                      (Figure 3).

Typically during the circuit board’s
initial design process, the board      Design issues with UDPo
designer makes a series of trade-
offs between electrical, thermal       There are numerous issues yet to
and mechanical needs. Once com-        be solved before Chip Packaging        Figure 3 – Single layer routing
ponent locations are established,      2.0 and user-definable pinouts can      is possible when an optimised
the circuit schematic is loaded        be adopted as a standard industry      UDPo pinout device is bussed with
and autorouting of the board com-      practice.                              standard IC
mences. The iteration begins by
benchmarking the initial results       For example, co-design EDA soft-       example of insulated bonding wires
achieved with standard pinout          ware tools for optimising chip         in an open cavity QFN package.
packages. Next, the EDA software       pinouts must be economical and
begins the pinout iteration proc-      reliable for mainstream board de-
ess. Pairs of pinouts on selected IC   signers to use. Several companies      Designing with User Definable
packages are iterated while board      are working on creating versions of    Pinouts
routing is observed. During the        EDA chip co-design and optimisa-
iterative process, improvement is      tion software as demonstrated dur-     Let’s examine a simple circuit de-
observed as copper routing lengths     ing various industry shows in the      sign to illustrate how UDPo can
are shortened, board size is re-       course of 2007.                        improve design. Figure 6 shows
duced and/or fewer inner layers are                                           the ‘before’ non-optimised board
realised. Circuit speed improves      Assuming that reliability issues        design. U1 and U2 are off the shelf
roughly one nanosecond in a theo-     with EDA software can be resolved,      8 pin SOP packages. The copper
retical lossless substrate for each   the next challenge for the new ap-      routing on the PC board from
6-inch (150mm) reduction of dual      proach to UDPo (user definable           U1 pin 4 to U2 pin 7 crosses the
copper path (signal plus ground)      pinouts) is the collaboration with      copper routing from U1 pin 5 to
according to the speed of light for-  semiconductor makers. There is a
mula.                                 need to define new libraries to allow
                                                    silicon with uncon-
                                                    ventional wire bond-
                                                    ing crossing over the
                                                    die in every direc-
                                                    tion. Traditional wire
                                                    bonding is very neat
                                                    and orderly, however,
                                                    in the proposed Chip
                                                    Packing 2.0 environ-
                                                    ment ‘neat and or-
                                                                                                                          P A C K A G I N G

                                                    derly’ may need to be
                                                    replaced with appar-
                                                     ently disorderly wires   Figure 5 – Example of an open
                                                     that cross over one      cavity QFN package with crossing
Figure 4 – Example of insulated bonding wire that    other (such as is ena-   insulated bonding wires
safely allows wires to cross                         bled by Microbonds
                                                     X-Wire      insulated    U2 pin 8. The board designer will
The remapping of the pinouts of bonding wire) in order to achieve             need to add a layer with plated vias
one chip at a time is optimised. design optimisation (Figure 4).              to prevent short circuits and com-
The co-design then cycles to the                                              plete the design.
                                                                                                                          A D V A N C E D

next chip until the total PC board Most of the common industry                By comparison, figure 7 illus-
is optimised to the satisfaction of standard JEDEC IC package out-            trates the ‘after’ optimised board
the board designer. Once the chip lines such as QFN, QFP, SOIC, BGA,          achieved by re-mapping the
pinouts are optimised, the EDA CSP and TSOP can all be adapted                pinouts of U2 without changing
software will produce a bonding to the concept of UDPo. Standard              the performance of the silicon die.
schedule (net list) for input into wire bonding machines are easily           The optimised board requires no
semiconductor wire-bonding ma- converted to use insulated bonding             vias, has shorter copper routing
chines. Chip packages are bonded wires. Figure 5 shows an extreme             and fewer layers.                                                    OnBoard Technology April 2008 - page 53
                                                                be remapped. The re-mapped U2           sultant board designs will become
                                                                requires crossing of bonding wires      simpler, it is anticipated that there
                                                                from die pad 7 to lead frame pin 8      will be quicker time to market as
                                                                and from die pad 8 to lead frame        well as lowering of costs related to
                                                                pin 7.                                  testing, rework and field failures.

                                                                The EDA software then creates a         Figure 7 – ‘After’ optimised board
                                                                bonding schedule (net list), and        design. U2 is re-mapped using
                                                                the data is given to IC packaging       insulated bonding wires to prevent
                                                                assembler to wire bond the legacy       shorting pins 7 and 8 with the IC
                                                                die (or wafer). Insulated bonding       package
                                                                wires are used to prevent short cir-
                      Figure 6 – ‘Before’ non-optimised         cuits with the chip package. The IC
                      board design                              packaging assembler delivers U2 to
                                                                the board assembler (EMS/CMS)
                                                                who uses standard SMT assem-
                      The board designer will use co-de-        bly practises to mount the com-
                      sign chip optimisation EDA soft-          ponents and complete the board
                      ware to simultaneously iterate and        assembly. Admittedly, the above
                      re-map U2 while auto routing cop-         examples in Figure 7 and Figure 8
                      per traces on the board. After com-       are ultra simplistic for illustration
                      pleting the iteration process, the        purposes only. However, the same
                      EDA software identifies that two           co-design process can be applied to
                      bonding wires inside U2 should            complex board designs. Since re-

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  P A C K A G I N G

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  A D V A N C E D

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                      OnBoard Technology April 2008 - page 52