Future of Analog Design and Upcoming by scm19335

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									Future of Analog Design and
  Upcoming Challenges in
     Nanometer CMOS
          Greg Taylor

        VLSI Design 2010
                           Outline

• Introduction
• Logic processing trends
• Analog design trends
• Analog design challenge
• Approaches
• Conclusion



     Future of Analog Design and Upcoming Challenges in Nanometer CMOS   2
                     Introduction

• This talk will focus on analog design on
  digital processes
 – Small geometries
 – Low voltages
 – Integration with logic
• Processes optimized for analog circuits
  are a different problem


      Future of Analog Design and Upcoming Challenges in Nanometer CMOS   3
            Introduction (cont)

• Intel view:
  – Don’t get in the way of digital scaling
  – Transistor count doubles every 24 months
  – Don’t violate the Law!
• Alternative view
  – Logic processes are leading the way to
    smaller geometries
    – They provide the first look at the design of
      analog circuits at these feature sizes

      Future of Analog Design and Upcoming Challenges in Nanometer CMOS   4
                           Outline

• Introduction
• Logic processing trends
• Analog design trends
• Analog design challenge
• Approaches
• Conclusion



     Future of Analog Design and Upcoming Challenges in Nanometer CMOS   5
     Logic Processing Trends
     Transistor count   109                                          109



                        107                                          107

                                               2x every
                                               2 years
                        105                                          105



                        103                                         103
                          1970   1980   1990     2000     2010   2020

• Performance and functionality continue to
  improve with increased transistor count

           Future of Analog Design and Upcoming Challenges in Nanometer CMOS   6
                                        SRAM Scaling
                   10
Cell Area (um 2)




                                                                                65 nm, 0.570 um2


                    1

                              0.5x every                                        45 nm, 0.346 um2
                               2 years

                                                                                32 nm, 0.171 um2
                   0.1
                     1995        2000          2005          2010


                                Mark Bohr: IDF 2009                             22 nm, 0.092 um2

                            Future of Analog Design and Upcoming Challenges in Nanometer CMOS      7
            30 Years of Scaling
Contact 1978




                       Ten 32nm SRAM Cells
                              2008




                                            1 µm


      Future of Analog Design and Upcoming Challenges in Nanometer CMOS   8
Process trends: New Generation
         Every 2 Years
           10                                                                10000
                      Nominal feature size



             1                                              0.7X             1000




                                                                                    Nanometers
                                                           every 2
 Microns




                                365      130nm              years
                                         248 90nm
                                                    193
                                                65nm
                                                   45nm
           0.1                                                               100
                                                      32nm
                   Nanotechnology                       22nm
                     (< 100nm)
                                                                13
    0.01                                                                     10
            1970      1980     1990      2000       2010           2020

                                                             Source: Intel                       9
                                                     Yield Trends
               90nm     65nm       45nm            32nm
                                                                      • 2 year technology
Defect
                                                             Higher
                                                                        cycles
Density
                                                              Chip
(log scale)
                                          2 year
                                                              Yield    – High yields
                                                                       – Fast ramp to
                                                                         volume
                                                                      • Progress is not
              2002 2003 2004 2005 2006 2007 2008 2009 2010
                                                                        slowing



                            Future of Analog Design and Upcoming Challenges in Nanometer CMOS   10
                           Outline

• Introduction
• Logic processing trends
• Analog design trends
• Analog design challenge
• Approaches
• Conclusion



     Future of Analog Design and Upcoming Challenges in Nanometer CMOS   11
             Why Analog Design?
 (analog circuits are needed to interface with reality. reality is analog)




                               Magical Fairyland
                                of 1’s and 0’s


Thermal                                                                  Configuration




                                                                            Source:
                     Temporal                 Electrical                 Rachael Parker


          Future of Analog Design and Upcoming Challenges in Nanometer CMOS               12
                 Growth in Analog Circuits

                                                                          Analog Circuits/Systems on Intel Microprocessors

   Microprocessor:                                             35
    clock generator
        IO bus                   # of Unique Analog Circuits   30
  thermal shutdown
         trim                                                  25

                                                               20
                                                                                                                             Fuse
                                                               15                                                            Thermal
  Multi-core SOC:
                                                                                                                             Clocking
 multi-domain clocking                                                                                                       IO
      10-20 PLLs                                               10
  high speed serial IO
     low jitter clock                                          5
advanced thermal and
 power management                                              0
                                                                    250      180    130    90      65       45     32
unit-level trim of analog
      components                                                                    Process Node (nm)


                      Future of Analog Design and Upcoming Challenges in Nanometer CMOS                                           13
  Performance Requirements
      ~10x over a decade
Pentium® II Processor                       Core™ i7 Processor
• 250 nm                                  • 45 nm
• PLL: 400 MHz Fmax                       • PLL: 3+ GHz Fmax
              C
• DTS: 140 ° ± 15 ° C                                 C
                                          • DTS: -10 ° to 140 °C
  single trip point                            C
                                            1 ° Resolution
• I/O: 266/400 MT/s                       • I/O: 6400 MT/s




     Future of Analog Design and Upcoming Challenges in Nanometer CMOS   14
                           Outline

• Introduction
• Logic processing trends
• Analog design trends
• Analog design challenge
• Approaches
• Conclusion



     Future of Analog Design and Upcoming Challenges in Nanometer CMOS   15
                           Voltage Scaling
            10
    Voltage (V)



                                       0.7x/gen
                  1
                      2000 1000 800 500 350 250 180 130         90    65   45     32

                                               CD (nm)
• Voltage scaling has slowed on recent
  technologies
 – This is the technology maximum voltage
              Future of Analog Design and Upcoming Challenges in Nanometer CMOS        16
   Analog Scaling with Voltage

• Reduced operating range of classical
  circuits
 – Signal shrinks
 – Noise doesn’t
• Low overdrive exacerbates Vt mismatch
• Weakly “off” switches leak



     Future of Analog Design and Upcoming Challenges in Nanometer CMOS   17
      Device Mismatch Trend

• Transistor threshold variation increases
  with shrinking device size
 – σVt = C2/√Weff•Leff
• Process improvements provide some
  relief
 – Scaled device sizes still lead to variation
   increases



      Future of Analog Design and Upcoming Challenges in Nanometer CMOS   18
Scaling of σVt Random Variation




  –   Kuhn, “Reducing Variation in Advanced Logic Technologies”, IEDM 2007
       Future of Analog Design and Upcoming Challenges in Nanometer CMOS     19
                                  Noise
• Thermal noise
                               2 / 3    L
                  2
               dVeq     = 4kT         ≈
                                      df
                               gm       W
• 1/f noise
                              KF       df
                  2
               dVeq    =
                                 2     f
                           WL • Cox
• Dynamic range decreases for smaller L and W
  –   Sansen, “Analog IC Design in Nanometer CMOS Technologies“, VLSI
      Design 2009




          Future of Analog Design and Upcoming Challenges in Nanometer CMOS   20
                 Co-
                 Co-Optimization
• Time to market can force design in parallel
  with process development
  – The good news is that process development is in
    parallel with design
• Reserve some adaptability to cover when
  development does not go as expected
• Note:
  – Digital circuits generally have analog success
    criteria
  – Analog circuits usually have binary success
    criteria
       Future of Analog Design and Upcoming Challenges in Nanometer CMOS   21
               Other Challenges
• Mixed Signal Validation:
  – When digital and analog circuits are mixed the
    validation approaches that are effective for either
    in isolation fail to adequately cover the
    combination
     – Circuit simulation runs times explode
     – RTL simulation doesn’t model analog behavior
• Testability
  – Increasingly difficult to characterize the clock
     – Low bandwidth, legacy DFT pins
  – Difficult to do volume analog test, yet statistical
    design requires statistical test


       Future of Analog Design and Upcoming Challenges in Nanometer CMOS   22
                           Outline

• Introduction
• Logic processing trends
• Analog design trends
• Analog design challenge
• Approaches
• Conclusion



     Future of Analog Design and Upcoming Challenges in Nanometer CMOS   23
     Avoid Analog If You Can

• Many functions can be implemented
  with analog or digital approaches
 – If possible, choose digital
                                                                 Cntr




      Future of Analog Design and Upcoming Challenges in Nanometer CMOS   24
   Copy* It If You Can’t Avoid It

• A new implementation is fun
 – It’s also a way to find new kinds of
   mistakes to make
 – It’s more expensive and takes longer than
   copying
• Take advantage of the work that others
  have done to find mistakes and validate
  solutions
 * Paying attention to IP laws
      Future of Analog Design and Upcoming Challenges in Nanometer CMOS   25
If You Can’t Copy It, Then Apply
     Good Design Practices
• Keep It Simple!
  – As simple as possible, as digital as possible
• Document your work
  – The flip side of reuse, is that you need to make
    your own work reusable
  – Documentation improves the quality of design
    reviews, helping find mistakes sooner
  – People who are reusing your work are invested in
    finding errors




       Future of Analog Design and Upcoming Challenges in Nanometer CMOS   26
        Good Design Practices
            co-
• If you’re co-developing along with your
  process, build in lots of tolerance for process
  targeting
• Build in tolerance for variation
  – There are only so many atoms available in those
    transistors
  – Keep matching localized
• Utilize self calibration, trimming, and fuse
  options
  – This will help increase tolerance to retargeting and
    variation


       Future of Analog Design and Upcoming Challenges in Nanometer CMOS   27
     If You Can’t Fix It, Feature It

• Analog to digital converter                                                 +
                               Vin



 –               0.2-to-
     Daly, “A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator
     Redundancy”, ISSCC 2008

• Adaptive frequency clocking
                                                                voltage



                                                Frequency




                                                                             Voltage
                                                                    freq

                                                          time
 –                                Micro-
     Kurd, “Next Generation Intel Micro-architecture (Nehalem) Clocking
     Architecture”, JSSC 2009

         Future of Analog Design and Upcoming Challenges in Nanometer CMOS             28
               Statistical Design
• Increasing device variation requires variation
  aware design
  – Worst case design is generally not practical
  – Skew corner simulation does not highlight the
    impact of within die variation
• Statistical design techniques help predict and
  understand the impact of variation
  – Monte Carlo
  – Design of Experiments
  – These tools don’t replace the need for engineers
    to understand statistics!

       Future of Analog Design and Upcoming Challenges in Nanometer CMOS   29
         Validation Is Essential
• Circuit simulation
  – It’s the time honored approach
     – Necessary, but not sufficient in a mixed signal system
• Mixed signal validation
  – RTL is often discrete time, discrete voltage
  – Hybrid circuits control RTL invisible behavior
     – Impedance, delay, temperature, voltage, current
• Design reviews
  – Reviewer team needs to have variety and
    engagement



       Future of Analog Design and Upcoming Challenges in Nanometer CMOS   30
                 AMS Validation

• Ensure that individual analog blocks
  work
 – The traditional realm of circuit simulation
• Ensure that analog blocks work
  together
 – Not just at the center of the spec range
• Ensure that digital and analog work
  together
 – Both control and data flow
      Future of Analog Design and Upcoming Challenges in Nanometer CMOS   31
         Other Rules of Thumb
• Need to enforce supply isolation between
  analog and digital circuits
• Production vs. simulation schematics
  – It’s tempting to make “alternate” schematics for
    simulation that include extras
     – Don’t
  – If necessary build a test bed in a higher level of
    hierarchy




       Future of Analog Design and Upcoming Challenges in Nanometer CMOS   32
                           Outline

• Introduction
• Logic processing trends
• Analog design trends
• Analog design challenge
• Approaches
• Conclusion



     Future of Analog Design and Upcoming Challenges in Nanometer CMOS   33
                      Conclusion
• We are increasing the scope and complexity
  of analog circuits on logic processes
 – At the same time those processes are becoming
   harder to work with
   Eliminate unnecessary analog design
   Avoid making analog the limiter where possible
    – floorplan constraints, timing margin…
                            non-
   Mitigate process scaling non-idealities
    – Trim, offset cancellation, noise shaping, high voltage
      analog, etc
   Don’t skimp on mixed signal validation

      Future of Analog Design and Upcoming Challenges in Nanometer CMOS   34
         Questions?




Future of Analog Design and Upcoming Challenges in Nanometer CMOS

								
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