A Digitally Tuned 1.1 GHz Subharmonic Injection-Locked VCO in 0.18µm CMOS Hesham Ahmed, Chris DeVries, and Ralph Mason Department of Electronics, Carleton University, Ottawa, Canada Email: email@example.com, firstname.lastname@example.org, email@example.com Abstract phase noise. In an attempt to eliminate offchip components, integrated In this paper, a second-order digitally controlled Q-enhanced filters provide a promising solution for receiver oscillator, based on subharmoninc injection locking, is filtering . A Q-enhanced filter in the receive chain can be presented. The prototype design is implemented in a 0.18µm converted to an oscillator by simply adjusting the bias current standard CMOS process. The implemented injection-locked to increase its Q. The resulting oscillator can be used as a oscillator, with a resonant frequency of 1.1 GHz, provides a VCO in the transmit chain for systems using half duplex low phase noise of –99.7 dBc/Hz at a 50 KHz offset. The operation. Use of Q-enhanced filters as VCOs has been oscillator is injection-locked with the eleventh harmonic of a proposed previously but their use has been limited to a low frequency 100 MHz PLL. Using switched-capacitor conventional RF PLL architecture . One problem with banks, the oscillator can be digitally tuned to within this type of VCO is that they generally have higher phase 300 KHz of the injection locking frequency which allows it to noise as the circuits are not optimized for the VCO function. be locked with an input signal as low as –53 dBm. The Through injection locking of such VCOs, this problem can oscillator has an overall tuning range of 20% and together be overcome. Using this approach, the overall chip area can with an input amplifier consumes only 688 µW when be reduced by eliminating the need for a separate VCO and powered by a single 1.6V supply voltage. RF PLL in the transmit chain. In this paper, the application of injection locking of an 1. Introduction oscillator is explored. This oscillator is within a transceiver structure that allows it to be digitally controlled thereby As gigahertz-band communication is becoming more improving its locking range and phase noise and reducing the mature, the realization of a single chip transceiver becomes power consumption significantly. more demanding, with the need for lower cost, reduced size and less power hungry transceivers. The motivation for this 2. Injection-Locked Frequency Oscillators work is the reduction in overall transmitter power consumption and reuse of receiver building blocks to achieve The process of injection locking is a fundamental a more compact transceiver structure. property of oscillators . Depending on the ratio of the For wireless transceivers, the Local Oscillator (LO) is injection frequency to the oscillator frequency, injection generally based on an RF PLL architecture that consumes locking can be categorized into three distinct types: first- considerable power. The low phase noise VCO and PLL harmonic, subharmonic and superharmonic . Injection prescaler, which operate at the highest frequency, dissipate locking is used to lock a free-running oscillator to an external the majority of this power . An alternative method is the incident signal. When a free running oscillator is injected use of a low frequency PLL that can be used to injection-lock with a periodic signal fc it will lock to and track the a VCO to one of its harmonics . This provides a number injected signal over a Locking BandWidth (LBW) given by of advantages. First, you do not require a separate PLL for fc ± LBW/2. The phase noise of the output tracks the phase the LO. The low frequency PLL can be the same PLL that is noise of the injected clock over a wide bandwidth . used for transceiver clock generation and therefore does not The LBW is dependent on the level of the injected signal. require any extra power. Second, you do not require a low To accommodate process and environment variations, typical phase noise VCO as the phase noise will be determined by RF applications require an LBW of 25-50 MHz greater than the clock PLL, which allows a significant reduction in the the signal bandwidth. Achieving this LBW requires a large VCO power consumption. A major drawback with this injection signal power. For subharmonic injection locking, approach is that the clock PLL phase noise will be increased the harmonic often has significantly lower power than the by the square of the injection locked harmonic . fundamental, which therefore must have an even larger Therefore, care must be taken to minimize the clock PLL power for correct locking. If the oscillator free running frequency can be guaranteed 4. Injection Lock Amplifier and VCO Design to be close to the injection harmonic frequency, independent 4.1 Circuit Design of process and environmental variation, the required LBW can be greatly reduced. As a result, the injection signal Figure 2 illustrates a simplified circuit diagram of the power and associated power dissipation can be reduced. implemented injection-locking amplifier and VCO. The circuit consists of three basic parts, an input 3. System Architecture transconductance or amplifier stage, a tank circuit and a negative resistance or Q-enhancement transconductance. Figure 1 shows the overall transceiver system architecture. The top part of the figure shows the receive chain which consists of an input RF switch (1), LNA (2), Q- Vf enhanced band select filter (3), attenuator (4), transconductor (5), Q-enhanced channel select filter (6), RF amplifier (7) M2a M2b and sub-sampling mixer (8). The lower block diagram shows out+ out− the transmit chain which consists of injection lock amplifier in+ M1a M1b M3a Vdegen M3b (9), injection lock VCO (10), up-converting mixer (11), in− M4 preamp (12) and PA (13). For transmit, the Q-enhanced band select filter (3) is converted to the injection lock VCO VQ R1 (10) by increasing its bias current. Also note that the tank circuit of the Q-enhanced channel select filter (6) is used for the tank of the mixer (11) in the transmit chain. All parts of the transceiver are controlled by eight or 16-bit control Figure 2. Injection Amplifier and VCO Circuit Diagram DACs (14) that can be used to digitally control the frequency and Q of the injection-locked VCO and transmit chain tuned The input transconductance uses a standard cascode LNA mixer. A TX DAC (15) is used to convert data from the structure. The filter tank circuit makes use of offchip baseband processor. The focus of this paper is on the inductors to obtain better quality factor and thus less power highlighted portion of the block diagram, which includes the consumption. Switched-capacitor banks are used in place of injection lock amplifier and VCO as well as the process for varactors of a conventional RF tank circuit since they provide pre-tuning the VCO before injection locking. higher Q, larger tuning range and better noise rejection operation. The enhancement transconductor, which is a basic differential pair, consists of transistors M3a,b. Also, not shown, are two differential source follower stages used for testing the outputs of the injection-locked 1 2 3 4 5 6 7 8 VCO with a 50 ohm load. It can be shown that by connecting a negative resistance LNA Gm circuit across a tank circuit can result in a Q given by , To 1 ω 0C fs ADC Q= ⋅ Qo = (1) 1 − g m Ro go − gm where Qo is the initial Q of the tank circuit (without enhancement and typically inductor limited i.e. Qo≈ Ro/ωoL= 1/goωoL), go is the equivalent parallel losses in the tank circuit, gm is the negative transconductance, C is the tank circuit capacitance and ωo is the center frequency given by, 9 10 11 12 13 1 PLL PA ωo = (2) LC 14 7 8 By setting gm close to go, the Q of the circuit can be set TX arbitrarily high and the circuit will oscillate at ωo. Baseband / DAC uProcessor ... DAC 15 To 4.2 Injection Lock VCO Tuning From fs ADC ADC Tuning of the VCO is achieved using direct digital tuning that does not require an input reference . A sub-sampling mixer, a typical sample and hold circuit with an input Figure 1. A Proposed CMOS Transceiver Architecture bandwidth large enough to handle RF signals, is used to sample the RF signal to a much lower digital IF signal. A low-frequency clock PLL is used to generate the sampling 30 frequency and an ADC, similar to that in , is used to 25 digitize the signal. A digital baseband circuit that is used for receive signal demodulation is reused to measure the 20 LBW [MHz] frequency of the VCO. An on-chip microcontroller uses the measured frequency to digitally adjust the free running VCO 15 frequency. The digital control is achieved by turning the tank circuit switched-capacitor banks on and off. Using a small 10 unit capacitor size of 5 fF, the free running frequency can be adjusted by 300KHz steps over a 20% tuning range. 5 Once the VCO has been tuned to within 300KHz of the 0 desired injection locking harmonic frequency, the clock PLL -60 -50 -40 -30 -20 frequency is switched to the injection locking fundamental frequency and applied to the injection-locking amplifier. The Injection Locking Power [dBm] injection locking fundamental frequency is typically higher Figure 4. Locking BandWidth vs. Injected Signal Power than the receive sub-sampling frequency to minimize phase noise (i.e. use a lower harmonic) and reduce transmit spurs Figure 4 shows the Locking BandWidth as a function of by having non-desired harmonics of the clock PLL out of the injected signal power. It can be seen that a signal power band. of –53 dBm is sufficient to lock the VCO as long as the free For the purposes of this paper, a sub-sampling frequency running frequency is within 1 MHz of the injection signal. of 45 MHz was used for tuning the free running VCO and a The free running VCO tuning algorithm is insensitive to frequency of 100 MHz was used for the injection locking process and environment conditions and allows the VCO to fundamental. The injection locking VCO was locked to the be tuned to within 300 KHz of the injection harmonic th 11 harmonic of the clock PLL at 1.1 GHz. frequency. This allows the VCO to be locked with a minimal injection harmonic power. Without the tuning algorithm it 5. Experimental Results would typically require more than 20MHz of LBW and an injection locking harmonic power of more than –25 dBm. The test chip was fabricated in a 0.18µm standard CMOS process. The chip was bonded directly to a test board using chip-on-board bonding (see Figure 3). VCO PA Mixer Rfamps / Sub- I.L. Amp Sampler µProcessor / SPI & Memory Figure 5. Oscillator Spectrum Figure 5 shows the measured output spectrum of the Figure 3. Chip Photomicrograph VCO using an HP8564E spectrum analyzer. As can be seen, th the spur due to the 9 harmonic is –54.34 dBc relative to the th th In the free-running mode, the injection locking VCO is injection locked 11 harmonic. The 10 harmonic is an even biased using a 1.6V supply with a bias tail current of 270 µA harmonic of the PLL square wave output and is therefore and has a tuning range from 990 MHz to 1.21 GHz. To greatly attenuated. It was measured at –68.8 dBc using a injection lock the VCO, a bias current of 160 µA is applied smaller resolution bandwidth for the spectrum analyzer. to the injection-locking amplifier to give an overall bias These spurs will be further suppressed when passed trough current of 430 µA. the tuned mixer, PA matching circuit and antenna. 7. References Free running  W. Chen, C. L. Kuo, “18 GHz and 7 GHz Superharmonic Injection-locked Dividers in 0.25 µm (-79.7 dBc/Hz) CMOS Technology,” Proceedings of the 28th European Solid-State Circuits Conference ESSCIRC2002, pp. 89-92, Florence, Italy, September 2002.  X. Zhang, X. Zhou, B. Aliener, and A.S. Daryoush, “A Study of Subharmonic Injection Locking for Local Oscillators,” IEEE Microwave Guided Wave Letters, Injection locked vol. 2, pp. 97-99, March 1992. (-99.83 dBc/Hz)  D. Shen, C. Hwang, B. Lusignan, B. Wooley, “A 900- MHz RF Front –End with Integrated Discrete-Time Filtering,” IEEE Journal of Solid State Circuits, vol. 31, no. 12, pp. 1945-1954, December 1996.  W. B. Kuhn, N. K. Yanduru, S. Wyszynski, “Q- Figure 6. Phase Noise before and after Injection Locking enhanced LC Bandpass Filters for Integrated Wireless Applications," IEEE Transactions on Microwave Finally, the HP8564E spectrum analyzer has been used to Theory and Techniques, vol. 46, no. 12, December measure the phase noise of the oscillator. Figure 6 shows the 1998. phase noise performance of the injection locked VCO before  W. B. Kuhn, “Design of Integrated RF Bandpass and after injection locking. The free running VCO has a Filters and Oscillators for Low-Power Radio phase noise of –79.7 dBc/Hz at 50 KHz offset. When Receivers,” IEEE International ASIC Conference, pp. injection-locked with a 100 MHz PLL signal, the phase noise 87–91, September 1996. is improved to –99.8 dBc/Hz at 50 KHz offset.  R. Adler, “A Study of Locking Phenomena in Measurement results for the VCO performance are Oscillators,” Proceedings of IRE, vol. 34, pp. 351-357, summarized in Table 1. The chip micrograph, implemented June 1946. Reprinted Proceedings IEEE, vol. 61, no. in a standard digital 0.18µm CMOS technology, is shown in 10, pp. 1380-1385, October 1973. Figure 3.  H. R. Rategh, T. Lee, “Superharmonic Injection- Locked Frequency Dividres,” IEEE Journal of Solid- TABLE 1. SUMMARY OF VCO PERFORMANCE RESULTS State Circuits, vol. 34, no. 6, pp. 813-821, June 1999. Technology Standard 0.18µm CMOS Power Supply 1.2 – 1.8 V  P. Kinget, R. Melville, D. Long, V. Gopinathan, “An Center Frequency 990 – 1210 MHz Injection Locking Scheme for Precision Quadrature Harmonic Spurs < -54.34 dBc Generation,” IEEE Journal of Solid-State Circuits, Phase Noise Free running -79.7 dBc / Hz vol. 37, no. 7, pp. 845-851, July 2002. @50 kHz Injection-Locked -99.8 dBc / Hz  C. DeVries, R. Mason, “A 0.18µm CMOS, High Q- Injection Amp. 270 µA enhanced Bandpass Filter with Direct Digital Tuning,” Current VCO 160 µA Proceedings of IEEE Custom Integrated Circuits Conference CICC2002, pp. 279-282, Florida, USA, Total Power (Vdd = 1.6 V) 688 µW May 2002. 6. Conclusions  B. Song, “A Fourth Order Bandpass Delta-Sigma Modulator with Reduced Number of Op amps,” IEEE In this paper, a subharmonic injection-locked, digitally Journal of Solid-State Circuits, vol. 30, no. 12, controlled, VCO, implemented in a standard 0.18µm CMOS December 1995. technology, is presented. The VCO can be locked using a low-power, low frequency clock PLL with reduced injection locking power. The free running VCO is tuned using a subsampling mixer, ADC and digital controller. The VCO can provide low spurious levels and good phase noise while consuming only 688 µW.
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