An Overview of the Java Embedded Micro-kernel Architecture

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					    An Overview of the
Java Embedded Micro-kernel
       Architecture

            Hong Ong
     Distributed Systems Group
      University of Portsmouth

        hong.ong@port.ac.uk
     http://dsg.port.ac.uk/hong

              DSG Seminar Nov. 1st 2002
                            Outline

    Project Goals.
    JEM architecture overview.
      –   Address space,
      –   Threads,
      –   IPC.
    Implementation issues.
      –   Compilation, memory allocation and mapping,
          etc.
    Status.

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                      Original Project Goals

    Our original goals were:
      –   To design an Abstract Device Interface (ADI) for
          MPJ.
      –   To improve the communications performance of
          MPJ.
      User-level networking.
      – Virtual Interface Architecture (VIA)

      – InfiniBand

      – Schedule Transfer Protocol (STP)




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                            UNET - General Idea

             User Process




             OS



                     NIC
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                            Things Change …

    Device has more powerful processors and
    more memory. For example,
      –   Myrinet - 8 Mbytes of RAM, 200Mhz RISC
          processor.
    A new opportunity:
      –    Not just offload protocol processing but also
          can offload service processing !!
    A new problem:
      –   We need a runtime environment to host and
          manage the service modules (applications).

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                                  New Project Goals

             A generic runtime environment that can be
             used in a range of embedded devices:
             A micro-kernel that can provide the
             necessary mechanisms for the various
dynamically loaded

             runtime aspects of the system.
             Service modules that can be dynamically
             loaded at runtime.
             Micro-kernel + Service modules should be
             Java-based … well, as far as possible …

      DSG Seminar Nov. 1st 2002                       6
                            Why Java ?

    Classes encourage modularity and data
    abstraction.
    Safety features (such as array index
    checking) improve robustness.
    Exceptions make it easier to handle error
    conditions.
    Many useful packages are available, e.g.,
    networking, GUI, etc.
    Other reasons …

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                                Why not Linux?

                  Linux Kernel Size (.tar.gz)                   For reference:

            35                                                  • Linux 2.4.18 =
            30
                                                                  2.7 million lines
                                                                  of code
            25
                                                                • uClinux =
Size (Mb)




            20

            15                                                    512KB size
            10                                                  • JEM = ~12 K
             5                                                    lines of codes,
             0                                                    expects ~250-
            31-Jan-93 28-Oct-95 24-Jul-98 19-Apr-01 14-Jan-04     300KB (without
                                  Date                            optimization)
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          U


                            What’s out there?

    1st generation µ-kernels
      –   Mach                CMU, OSF
      –   Chorus              Inria, Chorus          External Pager
      –   Amoeba              Vrije Universiteit
      –   L3                  GMD                    User-Level Driver
    2nd generation µ-kernels
      –   Spin                Washington
      –   Exokernel           MIT
                                                   User-Level Address
      –   L4                  GMD / IBM              Space
      –   Java OS
      –   J-Kernel
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                            The Great Promise

    Coexistence of different
      –   APIs
      –   file systems
      –   OS personalities
    Flexibility
    Extensibility
    Simplicity
    Maintainability
    Security
    Safety
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                    The Great Promise Disaster

    Coexistence of
    different
      –   APIs
      –   file systems
                                SLOW
      –   OS personalities
    Flexibility                 UNFLEXIBLE
    Extensibility               LARGE
    Simplicity
    Maintainability
    Security
    Safety
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                            JEM Construction

    Leverage lessons and designs from other projects.
      –   Micro kernel – L4, QNX.
      –   Safe language environemnt – J-Kernel, SPINE.
      –   UNET – Jaguar, PANIC.
    The idea: keep the kernel minimal.
      –   all services are implemented outside the kernel as servers
          that execute in user-mode.
    The problem: security.
      –   Not all services can be fully trusted by every user and by
          every other OS service
    The solution: the address-space paradigm.
      –   Any server (and any user) has its own private address
          space

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                             JEM Architecture

                     JEM            JEM
                    Module         Module




                                               JEM Comms API
                        JEM Comms API




                   JEM JNI
                                    JEM
                     API




                   Abstract Hardware Layer

                                               DMA
                                             Transfers
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            Possible JEM Configurations
                                                     specialized
                                     thin

                Security               embedded
 Java                       Native
                                         app      highly-specialized
  OS                         Java
                                                     component
                  RT
                  MM
                                                       HW
        JEM                          JEM                JEM


         HW                          HW                  HW


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      An Example – Configuration #2

                                             Workstation

                                                                     Main Processor and Memory

                                                                            MPJ Application
                    Network Card

                    JEM          MPJ API
                                               MPJ API
                   Module        Module                                            MPJ API




                                            JEM Comms API
                     JEM Comms API                                          JEM Comms API




                  JEM JNI                                                JEM JNI
                                   JEM                                                       JVM
                    API                                                    API




                  Abstract Hardware Layer
                                                                                             OS

                                                     DMA Transfers




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         JEM Fundamental Abstraction

    Address Space
    Thread
    IPC




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                            Address Spaces

    At the hardware level, an address space is
    a mapping which associates each virtual
    page to a physical page frame or marks it
    ‘non-accessible’.
    The micro-kernel hides the hardware
    details of address spaces.
    But, allow implementation of arbitrary
    protection (and non-protection) schemes
    on top of the micro-kernel.

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                            Recursive Mapping

    The basic idea is to support recursive construction
    of address spaces outside the kernel.
    By magic, there is one address space S0 which
    essentially represents the physical memory and is
    controlled by the first subsystem S0.
    At start time all other address spaces are empty.
    For constructing and maintaining further address
    spaces on top of S0, the micro-kernel provides
    three primitives:




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      Address Space Primitive: map()

                            The owner of an
                            address space can
                            map any of its pages
                            into another address
                            space, provided the
                            recipient agrees.
                            Afterwards, the page
                            can be accessed in
                            both address spaces.
                            The recipient can
                            (recursively) map the
                            page.
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     Address Space Primitive: flush()

                                            Owner can flush any of
                                            its pages.
                            flush
                                            The unmapped page
                                            remains accessible in
                                            the owner’s address
                                            space, but is removed
                                            from all other address
                                            spaces.
                                    flush
                                            The operation is safe
                                            since the users of
                                            these pages have
                                            agreed to accept a
                                            potential flushing.

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    Address Space Primitive: grant()

                                    The owner of an address
                                    space can grant any of its
                                    pages to another address
                                    space
                  map       grant   The granted page is
                                    removed from the owner’s
                                    address space and included
                                    into the recipient’s address
                                    space.
                   grant            The important restriction is
                                    that the granter can only
                                    grant pages that it can
                                    access.


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             Address Spaces: Summary

                                                              Application
                                  Application


          Application                                                  Application


                                                      Pager 4
                                                                                     Driver
                                Pager 3
                                                                                     Driver

                                     Pager 1                 Pager 2


                                                Initial AS


                                          Physical Memory
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                                 Thread

    A thread is an independent
    flow of control inside an
    address space.
    Internal properties                    IP
      –   stack                            SP
      –   status                          FLAGS
              e.g. FLAGs, privilege,
              OS-specific states (prio,
              time…)
      –   address space
    External properties
      –   unique id
      –   communication status


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                                     IPC

    Operation types:                       Message types:
      –   send                             –   register
      –   receive from                     –   dir string (opt)
      –   receive (from anyone)                      – up to 2M

      –   call (send to and receive        –   indir strings (opt)
          from callee)                               – up to 15 x 4M
      –   send & receive (from             –   map pages (opt)
          anyone)
    Timeouts:
      –   snd, rcv, snd pf, rcv pf
      –   0, infinite, 1us … 19 h
          (log)


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                            Interrupts

    The natural abstraction for hardware
    interrupts is the IPC message.
    The hardware interrupt is regarded as a set
    of threads that send empty messages (only
    consisting of the sender id) to associated
    software threads upon device interrupt.
    A receiving thread determine the nature of
    interruption based on message source id.



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                            I/O

    An address space is the natural abstraction
    for incorporating device ports.
    This is obvious for memory mapped I/O.
    The granularity of control depends on the
    given processor.
    Controlling I/O rights and device driver is
    thus also done by memory pagers and
    pager on top of the micro-kernel


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                       Drivers at User Level


                                                               User
                            INTR


                                    Driver
          Device


                            = ipc
                                    • IO ports: part of the user address space
                                    • interrupts: messages from hardware


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                 Implementation Strategy

                       *. j a va
                   (JEM micro-kernel)
                          or
                     (JEM Modules)
                                                  GCJ compilation Process

                                                                 *. s
                                                            (assembly code)
                            Native code
                             (executable)
                                                                  as
                                                       (assembly compiler)




                     Loader                     *. o                             *. s o
                                                                              (GCJ runtime
                                            (object code)
                                                                                library )



                                                                  ld
                 Myrinet 2000 Network                           (linker)
                       Interface


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                    Implementation Issues

    Our Primary Hard Problems:
      –   Java memory allocation support – the new
          operator and finalization (garbage collection),
      –   Java thread support,
      –   Java Runtime library support.
    Other Hard Problems:
      –   Require a robust and general AHL Specification.
      –   Performance.




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                            GCJ + libgcj

    Intricate relationship between the GCJ
    compiler and its runtime support.
    A good thorough knowledge of libgcj
    internals is required.
    Enable the JEM code to access the meta-
    information generated by the compiler.
    Wire the GCJ runtime primitives back to
    the JEM runtime primitives.


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                   Address Space Mapping



                            map




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           Mapping Database, Tile-map
                     Trees
                                    ptab Entry




                A

                                                 tiles (physical memory frames)
                 B
                                                 A 0 A 1 A 2 A 3 A 4 A 5

                            C             ?          B 7
     D
                                                                   How to find
                                                  D 0      C 2    the D0-entry
                                                                 in the tile-map
         X                      E                     E0              tree?

                                                                  Parse tree?
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           Mapping Database, Tile-map
                     Trees
                                    ptab Entry




                A

                                                  tiles (physical memory frames)
                 B

                                                 A 0   A 1     A 2   A 3     A 4   A 5

                            C                          B 7
     D
                                                                     How to find the
                                                   D 0        C 2    D0-entry in the
                                                                     tile-map tree?

         X                      E                        E0                PTE link?



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           Mapping Database, Tile-map
                     Trees
                                    ptab Entry




                A

                                                 tiles (physical memory frames)
                 B
                                                 A 0 A 1 A 2 A 3 A 4 A 5

     D                      C                        B 7
                                                                   How to find
                                                  D 0      C 2    the D0-entry
                                                                 in the tile-map
         X                      E                     E0              tree?

                                                                    cache?
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           Mapping Database, Tile-map
                     Trees
                                    ptab Entry



                A

                                                 tiles (physical memory frames)
                 B
                                             A 0 A 1 A 2 A 3 A 4 A 5

     D                      C                        B 7

                                                  D 0      C 2

         X                      E           X 7       E0



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           Mapping Database, Tile-map
                     Trees
                                ptab Entry

          A
                                    tiles (physical memory frames)
           B
                                       A 0A 1A 2A 3A 4A 5

  D                    C                       B 7

                                             D 0 C 2

      X                     E          X 7 E0               D0
                                          PTE pointer            parent
                                                                 sibling
                                             opt: virt address    child

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                              Status

    Done:                            To Do:
      –   GCJ + Libgcj               –   Device dependent.
          modification.              –   AHL Specification.
      –   Device independent part    –   Benchmark – IPC,
          (almost, need to               Memory mapping, etc.
          beautify/tidy the code).   –   Documentation!!




DSG Seminar Nov. 1st 2002                                       37