ELEC 5705 Synthesizer Integrated Circuit Design Assignment #4 by woo44846


									         ELEC 5705 Synthesizer Integrated Circuit Design:
                                                                 Assignment #4
                                                      Due April 22, 2005 before 5pm

The goal of this course will be to design using Cadence Design Systems a completely
integrated frequency synthesizer. The fourth assignment will be to design the Σ∆
modulator. A rough guide for the synthesizer specs will be as follows:

    -      Center Frequency of the VCO: 5GHz
    -      Tuning Range: 4.8GHz – 5.2GHz
    -      KVCO: 135MHz/V
    -      Divide Ratio 110-140 (large enough to lock the VCO over its whole range)
    -      XTAL frequency: 40MHz
    -      Divide ratio programmable in steps of 1.
    -      Supply voltage will be 3V
    -      Step Size: 1.25MHz

          Integer                                               2's comp-                                                            2's comp-
                                                                                                     z-1                                                          z-1
        divisor I(z)                                              liment                                                               liment
  Total                                                      3 bit       -(C2+C3(1-Z-1))Z-1                                         2 bit       -C3Z-1
 divisor         Fractional                     (1-Z-1)C2+
                  divisor 4 bit                 (1-Z-1)2C3                   3 bit                                    C3(1-Z-1)                          C3
           +                            +                            +                          -1
                                                                                                            +                               +
                                                          3 bit                  C2+C3(1-Z )                                      2 bit                          carryout
                  +(1-Z-1)2C3              carryout                                                        carryout                                                 C3
                                     1 bit                                                           1 bit                                                                1 bit
                                              C1                                                              C2
         n bit +               n+1                n                              +            n+1                    n                              +            n+1    quan       n
                                       quan                                                                quan
.F(z)                  +               -tizer
                                                          z-1                         +                    -tizer
                                                                                                                              z-1                        +              -tizer
                                A1                                       n bit                 A2                                           n bit                 A3
                           +                    -Eq1(z)                                   +                         -Eq2(z)                                  +                   -Eq3(z)
               n bit                                                          n bit                                                              n bit

For this assignment complete the following:

    1) Design a 3rd order MASH 1-1-1 Σ∆ to drive your MMD. Show as a minimum a
       dft of the circuit spurious components to prove that the noise shaping works.
    2) Simulate the MASH with the rest of your PLL at the circuit level to prove that
       you can lock to a factional number. Perform a dft of the output to see if there are
       any spurs generated by your design.
    3) If you are taking RFIC include your circuit level VCO design in the above
       simulation. When it locks…congratulations you have designed your first
    4) Now that you have designed all blocks in the synthesizer what is the phase noise
       of your design? Would a lower order Σ∆ have been sufficient from a noise point
       of view?
    5) If you are not taking RFIC then design a buffer to drive 5mm of transmission line
       terminated in a 50Ω load.

    Note: Assignments should be no more than 15 pages in length!

To top