ELEC 5705 Synthesizer Integrated Circuit Design Assignment #2

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					       ELEC 5705 Synthesizer Integrated Circuit Design:
                                       Assignment #2
                                       Due March 10. 2005

The goal of this course will be to design using Cadence Design Systems a completely
integrated frequency synthesizer. The second assignment will be to design the divider
architecture and implement it at the transistor level. A rough guide for the synthesizer
specs will be as follows:

   -     Center Frequency of the VCO: 5GHz
   -     Tuning Range: 4.8GHz – 5.2GHz
   -     KVCO: 135MHz/V
   -     Divide Ratio 110-140 (large enough to lock the VCO over its whole range)
   -     XTAL frequency: 40MHz
   -     Divide ratio programmable in steps of 1.
   -     Supply voltage will be 3V
   -     Current is to be as low as possible

You may implement the divider any way you like, but the obvious choice for this design
will be five cascaded, programmable divide by 2/3 stages as discussed in class.
 Input                                                                                     output
                                                        ____                       P/P+1
           Divide          2/3 Cell          2/3 Cell          2/3 Cell
           by S     Mod0      1                 2                n-1
                                      Mod1                                Modn-1     n

                            R0                R1                Rn-2               Rn-1
You should show the divider working inside the loop. As a minimum you must show the
loop locking when the divider is switched between two division settings. Note these will
be very long simulations so you should verify that your divider is working properly first.
Also check to make sure it interfaces properly with the DC levels of your behavioral

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