SFIL Dual Damascene Meeting Report by mre15330

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									 Dual Damascene using Step
and Flash Imprint Lithography

                 Grant Willson
           Department of Chemical Engineering
                Department of Chemistry
                  The University of Texas
                   Austin, Texas 78712


             http://willson.cm.utexas.edu
   Step and Flash Imprint Lithography
Photomask 6025 template, coated with                                     S-FIL fluid dispenser – 126
release layer            Template                                        ink jet system

                                           Planarization layer
   Step 1: Dispense drops                      Substrate




   Step 2: Lower template                                                Template filling driven by capillary
                                        Template                         action – low imprint pressure and
       and fill pattern                   Planarization layer            room temperature process
                                              Substrate




  Step 3: Polymerize S-FIL
   fluid with UV exposure                Planarization layer
                                             Substrate




                                       Template                                    Step & Repeat or
 Step 4: Separate template
                                                   Planarization layer             whole wafer imprint
       from substrate                                 Substrate
             The First SFIL Tool




“Step and Flash Imprint Lithography: A New Approach to High-Resolution
Patterning,” Proc. SPIE 3676 379-389 (1999)
              SFIL tool today




Resolution: Sub-32 nanometer half pitch
Alignment: < 10nm, 3 sigma (single point, X,Y)
Automation: Fully automated wafer and mask loading
Flexibility: 200mm and 300mm substrates (SEMI standard)
Field size: 26mm x 32mm (step-and-scan compatible)
Resolution of Imprint Lithography
  2nm Replication
(Rogers et al, Illinois)
                              SFIL
                           20nm Replication


                                                 25nm vias




                            ~130 atoms wide


                                              22nm logic (M1)
   Imprints from the Imprio 250
32nm half-pitch    24nm half-pitch    22nm half-pitch



                  Thanks to Toshiba



 32nm Logic         32nm Metal 1      25nm Contacts
Flash Memory Imprints
            Thanks to Samsung




 38 nm HP
 Non-CMOS Applications

100nm                 20 nm




                     Patterned
                      Media
 Photonic Crystals
           Multitiered Templates




      Fabricated with alternating layers of ITO and PECVD Oxide

                                       SFIL Imprint




S. Johnson, et.al. Microelectron. Eng. (2003) 67, 221
Our Job!

       Moore

You?
Egyptian Damascene
       ATDF Dual Damascene Process
    resist
       ILD
 etch stop
       ILD
 substrate

             initial stack   trench litho    trench etch




               via litho     BARC / resist   resist ash




               via etch       resist Ash       plate



23 unit process steps/layer =
184 steps for 8 layers of metal
                                                 CMP
  Direct Etch or Direct Imprint
SIM Process                           DPD Process
 Imprint Template
                                        Imprint Template


                        Sacrificial                    Directly
                SIM     Imprint                        Patternable
                        Material                       Dielectric


                                                      DPD
           Dielectric
             Layer



Previous Metal Layer                  Previous Metal Layer
                             SIM Damascene
                                Process
Multi-Tier Template



                                            # of process steps:   1
                                                                  0
                                                                  3
                                                                  2
                             SFIL IMPRINT
                                Press
                                 Flash
                                Release




                      ◄ Cured SIM
                        Dispense SIM

                      ◄ CVD ILD

                         Copper Barrier
        M1
             SIM Damascene
                Process

                     # of process steps:6
                                        8
                                        7
                                        5
                                        4
                                        3
                                       x8
                                       64
                                     Savings of
                     184 – 64 = 120
                                           steps



     Etch transfer
     Copper Seed
     CMP Plate
     Barrier Etch

M1
         BEOL Multilevel Imprint Cost Saving
                                   140%

                                   120%                                      20%
                                   100%
               relative cost (%)
                                   80%

                                   60%

                                   40%

                                   20%

                                    0%
                                                      wph = 5     wph = 10   wph = 20   wph = 30    wph = 40      wph = 50

                                           V1/M2                V1/M2 Dual Damascene by NIL in resist: 27 steps
                                          base line
                                            DD:
                                          44steps




   20% overall wafer cost saving at 30 wph
   Cost analysis by Sergei V. Postnikov, Infineon Technologies;
    presented at Semicon Europa 2007, Stuttgart, Germany
Lloyd Litt, et. Al NNT 08
                Multi-level Templates
 Features       CD             Height
   Vias       120 nm           240 nm
  Lines       125 nm           360 nm


                          1 μm vias

                                        Features       CD       Height
                                          Vias        50 nm     125 nm
                                         Lines       125 nm     313 nm
                                        Courtesy of IMS Chips


Courtesy of Toppan Photomask
     Multi-Level S-FIL Test Vehicle

     Via chain



 M2 by SFIL                                                                              M1 by
                                                                                    Photolithography

                            Test Structures
       Via Chains
        Via Chains              Isolated Lines
                                 Isolated Lines                    Dense Lines
                                                                    Dense Lines
                                                                      Dummy lines


                           IN                 OUT            IN                       OUT




                                  Comb                               Serp/Comb
                                                                      Serp/Comb
        Serp
         Serp                      Comb
                                                                                                   Comb
                                                  Comb 2    Serp
                                                                                            Serp
                                                             IN
                                                                                            OUT
IN               OUT                                       Comb
                       Comb 1
  SIM Via Chain Structures
 Via chain



M2 by SFIL                      M1 by
                           Photolithography




100nm vias   100nm vias   100nm via
  Pattern Transfer Demonstration
SIM Material



 Via Etch
Ar/C4F8/N 2

ILD Material


  Trench
  Descum
   N2/H2
     Pattern Transfer Demonstration


  Trench
   Etch
CF4/C4F8/N 2




    Ash
   N2/H2


               Both Coral® and Black Diamond® were processed
     Via Chain – 120 nm 1000 Contacts
           Cu (M2)                                         100




                              Cumulative Probability (%)
                                                           80
                         Ta                                                                             Chain #1
                                                           60
                                                                                                        Chain #2
                     Coral                                                                              Chain #3
                                                           40
    Cu                                                                                                  Chain #4
    (M1)                                                   20
                                                                                                        Chain #5
                                                                                                        Chain #6
    Template CD = 120 nm                                    0
      Final CD = 115 nm                                          0   2    4      6     8     10    12      14      16
                                                                     Via Chain Resistance (Ohm per contact)


    Yield statistics (6 valid and identical chains tested)
      • Overall yield of 1000-contact chains with via CD 120 nm
        (nominal) / 115 nm (final) – 96.83%
      • Individual contact yield   – 99.9968%
Directly Patternable Dielectric

           Imprint Template




                         DPD




         Previous Metal Layer
     DPD Property Requirements

Property                    Requirement
   Viscosity                  Less than 20 cP
   Photocurable               Chain reaction polymerization
   Cure shrinkage             Less than 15%
   Dielectric Constant        e≤3
   Thermal Stability          Less than 1% wt loss/hr @ 400oC
   Mechanical Properties      Young’s Modulus ≥ 4 GPa
   CTE                        Less than 30 ppm/oC
   Water Sorption             Less than 1% wt
             Sol-gel Design/Formulation
                                                                                     O
O        O
    Si             O            O    Si                                          O
    O                                O                                  O        O        O
               O            O                H2O, H+               Si       Si       Si       Si
               O        O
                   Si           Si                                          O        O
                   O                      ultrasonication, O   O
                                O
                                          vacuum
              Alkoxysilanes                                             Sol-Gel
    Sol-gel DPD Characterization
Property                                 Measurement
    Viscosity                              9-17 cP
    Acrlyate conversion                    93% @ 1.2 J/cm2
    Vertical shrinkage a                   ~ 30%        
    Dielectric Constant                    e ≤ 2.3
    Thermal Stability b                     364 °C
                                                   ?
    Mechanical Properties c                3-7 GPa ?
    CTE                                    23.4 ppm/°C
    a. Shrinkage is composite of UV cure bake at 300 °C
    b. Measured after bake at 350 °C.
    c. Measured by both nanoindentation and SAWS.
Metal Patterns (via chains) in
        Sol-gel DPD
                             Wires (M2)



                            “Dummy“
                            metal fill



                            Via chain
        Sol-Gel DPD Integration Study


                                           BEOL
 Imprint
                                           etch
uniformity
                                           metal
alignment
                                           CMP
template




                 Defect Sources
             M1 defects (not expected)
             Particle defects (expected)
Sol-Gel Via Chain Yield

             120nm Via Chains




                                   Courtesy of Brook Chao
             Poor Yield




              Cause of Failure
              Open at via bottom
POSS Design/Synthesis for DPD
         R                         R
                      O
            Si                Si
R        O O              O
    Si           Si
             O                 O

    O             O
         R Si                 Si
         O            O                R
    Si                 O
                 Si                             O Si O Si
R            O            R
                                                                    x

                                                O Si O Si   O

O Si O Si                                                       O   y
                                           h
                                   x                        x+y=8
                                                                            
O Si O Si             O                     
                                                O Si O Si
                          O        y
                      x+y=8                                             x

                                                O Si O Si   O

                                                                O
                                                                    y
                                                            x+y=8
           POSS Characterization
Property                                Measurement
    Viscosity
                                          ~640 cP     
   Exposure                               89 mJ/cm2 @ 80% conv.
   UV shrinkage                           17 ± 4%
   Thermal shrinkage a                    5 ± 3%
   Dielectric Constant                    2.84
   Thermal Stability a                    344 oC
   Mechanical Properties b                2-5 GPa ?
   CTE                                    32 ppm/oC
a. Measured after bake at 250 °C.
b. Measured by both nanoindentation and SAWS.
    Viscous Dispense System
   Issue: inkjet requires m < 20 cP
   Solution: new viscous fluid dispense
    technology is being implemented
                           POSS Design/Synthesis
                                Polyhedral Oligomeric Silsesquioxane (POSS)

                                                                                       B            O                    O               O
                   O                                                                       Si                Si                    Si         Si
        Si                 Si                                                  O
                                                                                                        O
                                                                                                                                                                 n


                                                                                                                                                       B
     O O                                                                                    O
                       O                                                                                          BO
              Si                                                          Si
Si
         O                  O O Si O SiH                          A                    O                Si

                                                                                                                         Si
                                                                                                                                          Benzocyclobutane
               O                           8
O        Si                Si
                                                                      O
                                                                                   O
                                                                                            Si
                                                                                                                 O
                                                                                                                                        B      (BCB)
     O             O                                  O                                                 O
Si                     O
         O
              Si                                                          Si                    B           Si
                                                                                                                     O                                 O
                                                          O                                     O                             Si         Si
                                                                  A                                                  O              O              O
     Hydrosilylation chemistry                 Pt(dvs), Toluene
                                                                                                                                                   A
                                                                                                                                                           8-n


                                                                                                                                              (Meth)acrylate
                 Conclusions
   Multi-level S-FIL is a viable approach for Cu /
    low-k dual damascene processing

    • SIM Process has been demonstrated by good electrical
      yield in various via and line test structures
    • Implementation does not involve reliability testing

    • Lower cost DPD Process is making progress
       • Opportunity for materials design
       • Some processing challenges remain
    • Implementation of DPD requires reliability testing
     These people did the work
      Brook H. Chao, Frank Palmieri,
     Wei-Lun Jen, and D. Hale McMichael
       The University of Texas at Austin

  Jordan Owens, Rich Berger, Ken Sotoodeh,
  Bruce Wilks, Joseph Pham, Ronald Carpio,
         Ed LaBelle, and Jeff Wetzel
 Advanced Technology Development Facility, Inc.
These people paid for the work

								
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