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     NAP Case Study Open Day: 19-Jan-06

                    Case Study No 6

     Presenter: Dr. Carsten Wegener - UCC

Project Title: Characterisation of an FPAA based
                 Sigma Delta ADC
Characterization of an FPAA based
        Sigma Delta ADC

  Carsten Wegener and David Flynn



Department of Microelectronic Engineering,
    University College Cork, Ireland.

      Carsten.Wegener@ucc.ie
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Overview

  Taught Masters programme

  Sigma Delta ADC operation

  Field-Programmable Analog Array platform

  Prototyping and characterization

  Results and conclusions



   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Taught Masters programme

         Duration: 12 months (starting in October)
         Course work of ten 5-credit modules
         Research (minor) thesis “Modeling and Prototyping a
         Sigma Delta ADC using a Field Programmable Analog
         Array”
                Modeling: theoretical understanding and behavioral
                MATLAB simulations
                Prototyping: experimental lab work at circuit level including
                circuit debug
                Sigma Delta ADC: industry standard Analog-to-Digital
                converter architecture which trades (switching) speed for
                amplitude resolution
                FPAA: fast prototyping of analog circuits; Cypress PSoC as
                test vehicle with pre-designed SD-ADC block
   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Sigma Delta ADC operation

         Control loop with time-average of output bit-stream y[n]
         approximating analog input u[n] due to negative feedback
         Single-bit ADC and DAC; can implement high-resolution
         ADC due to fast oversampling allowing averaging of output
         Filter topology H(z) (e.g. an integrator) determines the
         Sigma Delta topology (e.g. 1st- or 2nd-order)
                                                                ADC

      u[n]        +         x[n]                      v[n]                                   y[n]
                                         H(z)
                        −



                                                             DAC

   Carsten Wegener, Tyndall, Cork, January 19, 2005     Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Field-Programmable Analog Array platform

         Switched-capacitor circuits are “compatible” with digital
         CMOS process; enables System-on-Chip (SoC)
         Integrator operation by charge transfer C1 ⇒ C2
                                                             C2



                 φ1           C1              φ2
      Vin

                                                                                          Vout
                 φ2                      φ1                 +



   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Field-Programmable Analog Array platform

         Switched-capacitor circuits are “compatible” with digital
         CMOS process; enables System-on-Chip (SoC)
         Integrator operation by charge transfer C1 ⇒ C2
         Cypress PSoC contains basic building blocks
         Pre-designed module implementing a 2nd-order Sigma
         Delta




   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Cypress PSoC Switched-Capacitor block

  Configurable Analog Block
                                                                      φ1∗ AutoZero
        BQTAP

                                     CCap                                ( φ2+!AutoZero)
                                                               FCap               *FSW1
       C Inputs

                                                                           φ1∗ FSW0
       ACMux

                            φ1       ACap      φ2+ AutoZero
       A Inputs
                                               φ1∗                                                         OUT
                            φ2
        REFHI                                  !AutoZero
        REFLO
        AGND                                                                               AnalogBus∗φ2B
                                                                                                           ABUS
      ARefMux
        ASign
                           φ2        BCap                     Power                            CmpBus
        B Inputs                                                                                           CBUS

                                φ1

      BMuxSCA




   Carsten Wegener, Tyndall, Cork, January 19, 2005        Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Cypress PSoC Switched-Capacitor block

  Elements of SC integrator highlighted
                                                                      φ1∗ AutoZero
        BQTAP

                                     CCap                      FCap( φ2+!AutoZero)
                                                                            *FSW1
       C Inputs
                                                                C2         φ1∗ FSW0
       ACMux

                            φ1       ACap      φ2+ AutoZero
       A Inputs
                                     C1        φ1∗                                                    OUT
                            φ2
        REFHI                                  !AutoZero
        REFLO
        AGND                                                                          AnalogBus∗φ2B
                                                                                                      ABUS
      ARefMux
        ASign
                           φ2        BCap                     Power                       CmpBus
        B Inputs                                                                                      CBUS

                                φ1

      BMuxSCA




   Carsten Wegener, Tyndall, Cork, January 19, 2005        Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Cypress PSoC Switched-Capacitor block

  Configured first-order Sigma Delta
                      SC PSoC Block                               φ1



                                                    FCap=32                   φ2



                                                                       φ1 *Reset


                                φ1    ACap=16
               Vin
                                                                                                         Data           Data Bus
              Vref+                                                                                      Decimator
              Vref−
                                                                                                                Data
                                                                                                                Latch
                                                                          Analog Column Comparator Bus




                                                                                                                           CPU
                                                         Divide by 4    φ1                                                 Interrupt
                                           Analog
                                          Column Clock    φ1,φ2         φ2
                                                         Generator                                         Timer
               Source Clock




   Carsten Wegener, Tyndall, Cork, January 19, 2005                          Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Cypress PSoC Analog Block Array
                                                                                                  Digital
                                                                                                  Blocks
                                CompBus0          CompBus1          CompBus2           CompBus3


                              ACA               ACA               ACA                ACA
                               00                01                02                 03




                              ASA               ASB               ASA                ASB
                               10                11                12                 13




                              ASB               ASA               ASB                ASA
                               20                21                22                 23



                          AnalogBus0        AnalogBus1        AnalogBus2         AnalogBus3

                                                                                                  Port 0,2
                                                                                                  Port 0,4
                                                                                                  Port 0,5
                                                                                                  Port 0,3

                     clock0            clock1            clock2             clock3



   Carsten Wegener, Tyndall, Cork, January 19, 2005                     Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Prototyping and characterization

         Prototyping with FPAA requires a mix of software/DSP and
         hardware design skills
         Pre-designed 2nd-order Sigma Delta ADC exists and can
         be modified to suit application
         Initial test/debug in lab with DC input and parallel bit output
         Performance characterization in Tyndall’s Design
         Technology Evaluation group
                                HP82000
         Input                  Mainframe
         Signal
         Generator            DUT                        Programming             Samples processed
                                                         WorkStation             using Matlab


       Clock
       Generator              DUT Board



   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC
                                    Taught Masters programme
                                    Sigma Delta ADC operation
                     Field-Programmable Analog Array platform
                               Prototyping and characterization
                                       Results and conclusions


Fast Fourier Transform and frequency selection

                 Non-coherent versus coherent sampling (N = 16 points)

                                                                                                                                                                                    5                                       5                                       5                                       5

                                                                                                                                                                                4       6                               4       6                               4       6                               4       6
                 4                              14                  4                             14                  4                             14

             3                                                  3                                                 3                                                         3               7                       3               7                       3               7                       3               7
                                                     15                                                15                                                15
                      5                    13                           5                    13                           5                    13

         2                                                  2                                                 2                                                         2                        8              2                        8              2                        8              2                        8
                                                          16                                                16                                                16

                                      12                                                12                                                12                        1                   9                  1                    9                  1                    9                  1                    9
                              6                                                 6                                                 6                                                                                                                                                                                                1
     1                                               1                                                 1
                                                                                                                                                                                            10                  16                  10                  16                  10                  16                  10                  16
                                           11                                                11                                                11
                          7                                                 7                                                 7
                                                                                                                                                                                             11             15                       11             15                       11             15                       11             15

                              8       10                                        8       10                                        8       10                                                     12        14                            12        14                            12        14                            12        14


                                  9                                                 9                                                 9                                                               13                                      13                                      13                                      13




   noncoherent:                                                                                                                                                    coherent:
   sampling frequ.: Fs = 16 kHz                                                                                                                                    sampling frequ.: Fs = 16 kHz
   input frequ.: Fi = 1.5 kHz                                                                                                                                      input frequ.: Fi = 1 kHz
           F                                                                                                                                                               F
   M = N Fsi = 16 1.5 = 1.5
                  16
                                                                                                                                                                                  1
                                                                                                                                                                   M = N Fsi = 16 16 = 1
                                                                        Require M to be an (exact!) integer
   Carsten Wegener, Tyndall, Cork, January 19, 2005                                                                                                                 Characterization of an FPAA based Sigma Delta ADC
                                           Taught Masters programme
                                           Sigma Delta ADC operation
                            Field-Programmable Analog Array platform
                                      Prototyping and characterization
                                              Results and conclusions


Fast Fourier Transform and frequency selection

                            Non-coherent versus coherent sampling (N = 16 points)
                            Spectral leakage and exact frequency selection
                                                    Power Spectrum                                                                          Power Spectrum
                   60                                                                                          60




                                                                                                               40
                   40



                                                                                                               20
                   20


                                                                                                                0
     Power (dB)




                                                                                                 Power (dB)
                    0

                                                                                                              −20


                  −20
                                                                                                              −40



                  −40
                                                                                                              −60




                  −60                                                                                         −80
                        0      500    1000   1500       2000         2500   3000   3500   4000                      0   500   1000   1500       2000         2500   3000   3500   4000
                                                    Frequency (Hz)                                                                          Frequency (Hz)




                                     500 Hz input                                                                             500.76675 Hz

   Carsten Wegener, Tyndall, Cork, January 19, 2005                                                  Characterization of an FPAA based Sigma Delta ADC
                                       Taught Masters programme
                                       Sigma Delta ADC operation
                        Field-Programmable Analog Array platform
                                  Prototyping and characterization
                                          Results and conclusions


Results from measurements

                        8-bit Sigma Delta prototype
                               SNR performance: 46.4 dB (7.6 bit) measured vs. 46 dB
                               specified
                               INL performance: 0.4 LSB measured vs. 0.5 LSB specified
                                     INL versus Digital Output Code
                6                                                                                                   INL versus Digital Output Code
                                                                                               1


                                                                                              0.8
                4

                                                                                              0.6


                2                                                                             0.4


                                                                                              0.2
    INL(LSB)




                0                                                                 INL(LSB)
                                                                                               0


                                                                                             −0.2
               −2
                                                                                             −0.4


                                                                                             −0.6
               −4

                                                                                             −0.8


               −6                                                                             −1
                    0         50       100                150         200   250                     60   80   100          120           140         160   180   200
                                         Digital Output Code                                                             Digital Output Code




 Input range: 2.6Vpp; overranged with 2.8Vpp for INL measurement.
   Carsten Wegener, Tyndall, Cork, January 19, 2005                                      Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Results from measurements

         8-bit Sigma Delta prototype
                SNR performance: 46.4 dB (7.6 bit) measured vs. 46 dB
                specified
                INL performance: 0.4 LSB measured vs. 0.5 LSB specified
         11-bit Sigma Delta prototype
                SNR performance: 56.3 dB (9.1 bit) measured
                INL performance: 4.0 LSB (equiv. of 0.5 LSB at 8-bit
                resolution)
         Temperature dependence of performance parameters
         evaluated




   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Project outputs

         Student experience:
                Understanding of Sigma Delta background and applications
                Familiarity with FPAA technology; possibilities/ limitations
                Hands-on experience with hardware prototyping and
                debugging
                Exposure to industry-standard Automatic Test Equipment
         Research output:
                MEngSc thesis and degree
                Measurement results of FPAA setup match specifications
                Case of direct interaction between Microelectronic Eng.
                and Tyndall
                Follow-up project with FPAA’s is considered


   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Conclusions

         Carrying out experimental work is an important add-on to
         theoretical understanding of research topic
         Inclusion of measurements performed on adequate
         equipment enhances student experience
         Problems with the experimental setup were identified
         which in a modeling-only approach to the topic would have
         been missed
         Similar projects can be run through the “Open Access Test
         Facility” which is part of Tyndall/NAP as of 2006
         Active support provided by Ted O’Shea’s DTE-group
         helped the student to be exposed to best-practice
         Opportunities for Tyndall employees to get involved in
         research activities are currently under consideration
   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC
                        Taught Masters programme
                        Sigma Delta ADC operation
         Field-Programmable Analog Array platform
                   Prototyping and characterization
                           Results and conclusions


Acknowledgments

  Thanks to...
         David Flynn for sticking through this project
         Ted O’Shea for accommodating David Flynn in his DTE lab
         Mark O’Shea and Stephen McSherry from DTE for their
         generous support
         Paul Roseingrave and Julie Donnelly for running NAP
         Science Foundation Ireland (SFI) - for supporting NAP
         You for your attention




   Carsten Wegener, Tyndall, Cork, January 19, 2005   Characterization of an FPAA based Sigma Delta ADC