What is a MOSFET Fundamental Relations in MOSFET by xarrnet

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									                     What is a MOSFET?
 • Definitions
    – MOS = Metal Oxide Semiconductor
         • physical layers of the device
    – FET = Field Effect Transistor
         • What field? What does the field do?
         • Are there other fields that are important?
    – CMOS = Complementary MOS
         • use of both nMOS and pMOS to form a circuit
                                                                     V
 • Primary Features                        Metal                     gate
    –   gate
    –   gate oxide (insulator)             Oxide
                                                          E         insulator
                                                                     channel
    –   source and drain                    Semi-
                                                      source   ------------              drain
    –   bulk/substrate                    conductor
                                                                  silicon substrate
    –   channel


                             ECE 813S03, Prof. A. Mason                     Lecture 1, Page 2




        Fundamental Relations in MOSFET
• Electric Fields                                                     V
                                                                      gate
   – fundamental equation
        • electric field: E = V/d                          E        insulator
                                                                     channel
   – vertical field through gate oxide                 source -  - - - - - - - - - drain
        • determines charge induced in channel                 - -silicon substrate
   – horizontal field across channel
        • determines source-to-drain current flow
• Capacitance
   – fundamental equations
        • capacitor charge: Q = CV
        • capacitance: C = ε A/d
   – charge balance on capacitor, Q+ = Q-
        • charge on gate is balanced by charge in channel
        • what is the source of channel charge? where does it come from?


                             ECE 813S03, Prof. A. Mason                     Lecture 1, Page 3




                                                                                                 1
              CMOS Cross Section View
• Cross section of a 2 metal, 1 poly CMOS process




• Layout (top view) of the devices above (partial, simplified)




                           ECE 813S03, Prof. A. Mason                          Lecture 1, Page 4




                   CMOS Circuit Basics
• CMOS = complementary MOS                               drain                  source

    – uses 2 types of MOSFETs                     gate              gate

      to create logic functions
        • nMOS                                          source                  drain
                                                             nMOS           pMOS
        • pMOS
• CMOS Power Supply                                                                   VDD
    – typically single power supply                      +
                                                                    CMOS                 CMOS
                                             VDD                     logic        =
    – VDD, with Ground reference                         -
                                                                    circuit
                                                                                          logic
                                                                                         circuit
        • typically uses single power supply
        • VDD varies from 5V to 1V
                                                                 V
• Logic Levels                                                VDD
                                                                                logic 1
    – all voltages between 0V and VDD                                           voltages
    – Logic ‘1’ = VDD                                                      undefined
    – Logic ‘0’ = ground = 0V
                                                                                logic 0
                                                                                voltages

                           ECE 813S03, Prof. A. Mason                          Lecture 1, Page 5




                                                                                                   2
          Transistor Switching Characteristics
 • nMOS                                                    drain    Vout      nMOS
       – switching behavior                              gate
                • on = closed, when Vin > Vtn      Vin              nMOS                    Vin
                                                          +          Vgs > Vtn = on                    pMOS
                • off = open, when Vin < Vtn             Vgs                            VDD
                                                                                                        off
 • pMOS                                                   -         source           VDD-|Vtp|
       – switching behavior                                                                       on
                • on = closed, when Vin < VDD - |Vtp|                                                   on
                                                                              pMOS
                • off = open, when Vin > VDD - |Vtp|    +            source               Vtn
                                                                                                  off
 • Digital Behavior                                    Vsg
                                                                      pMOS                      nMOS
                                                        -
       – nMOS                                       Vin
                                                         gate
                                                                       Vsg > |Vtp| = on
                                                                       Vsg = VDD - Vin
       Vin Vout (drain)                                     drain
       1    Vs=0 device is ON                                        Vout
       0    ?       device is OFF
       – pMOS                                                   Rule to Remember
       Vin Vout (drain)                                         ‘source’ is at
       1    ?           device is OFF                           • lowest potential for nMOS
       0    Vs=VDD=1 device is OFF                              • highest potential for pMOS


                                      ECE 813S03, Prof. A. Mason                       Lecture 1, Page 6




                    MOSFET Pass Characteristics
  • Each type of transistor is better at passing (to output)
    one digital voltage than the other
        – nMOS passes a good low (0) but not a good high (1)
        – pMOS passes a good high (1) but not a good low (0)


                         VDD                       VDD         +
 nMOS                                                       Vgs=Vtn            Passes a good low
on when gate        0V                       VDD               -               Max high is VDD-Vtn
    is ‘high’
                                  Vy = 0 V                      Vy =
                                                                VDD-Vtn

                           0V                      0V        -
 pMOS                                                     Vsg=|Vtp|           Passes a good high
on when gate         VDD                     0V              +                 Min low is |Vtp|
    is ‘low’                    Vy = VDD                   Vy = |Vtp|


           Rule to Remember
           ‘source’ is at lowest potential (nMOS) and highest potential (pMOS)

                                      ECE 813S03, Prof. A. Mason                       Lecture 1, Page 7




                                                                                                              3
                 MOSFET Terminal Voltages
•    How do you find one terminal voltage if other 2 are known?
      – nMOS
           • case 1) if Vg > Vi + Vtn, then Vo = Vi
     Vo         – here Vi is the “source” so the nMOS will pass Vi to Vo
           • case 2) if Vg < Vi + Vtn, then Vo = Vg-Vtn
Vg
                – here Vo is the “source” so the nMOS output is limited
      Vi   • Example (Vtn=0.5V):           Vg=5V, Vi=2V ⇒ Vo = 2V
                                           Vg=2V, Vi=2V ⇒ Vo = 1.5V


      – pMOS
           • case 1) if Vg < Vi - |Vtp|, then Vo = Vi
     Vi         – here Vi is the “source” so the pMOS will pass Vi to Vo
           • case 2) if Vg > Vi - |Vtp|, then Vo = Vg+|Vtp|
Vg              – here Vo is the “source” so the pMOS output is limited
           • Example (Vtp=-0.5V):          Vg=2V, Vi=5V ⇒ Vo = 5V
     Vo
                                           Vg=2V, Vi=2V ⇒ Vo = 2.5V



                                    ECE 813S03, Prof. A. Mason              Lecture 1, Page 8




                  Switch-Level Boolean Logic
•    Logic gate are created by using sets of controlled switches
•    Characteristics of an assert-high switch


                                                                      nMOS acts like an
                                                                      assert-high switch


      – y = x • A, i.e. y = x if A = 1



 Series switches ⇒ AND function                     Parallel switches ⇒ OR function




                                    ECE 813S03, Prof. A. Mason              Lecture 1, Page 9




                                                                                                4
                   Switch-Level Boolean Logic
 •   Characteristics of an assert-low switch

                                                                      pMOS acts like an
                          y=x                        y=?
                                                                      assert-low switch

         – y = x • A, i.e. y = x if A = 0


 Series assert-low switches ⇒ ?                   NOT function, combining assert-
                                                    high and assert-low switches



                     NOR

Remember This??
                                                 a=1 ⇒ SW1 closed, SW2 open ⇒ y=0 = a
         a • b = a + b,     a+b=a•b
     DeMorgan relations                          a=0 ⇒ SW1 open, SW2 closed ⇒ y=1 = a

                                  ECE 813S03, Prof. A. Mason                      Lecture 1, Page 10




                                   CMOS Logic

            assert-low pMOS
              logic
inputs                 output
           assert-high
              logic
                       nMOS



push-pull CMOS network
     – pMOS, pushes high                                                          pMOS
     – nMOS, pulls low
CMOS Inverter

                                                                                 nMOS

                                                       only one network (p or n) is required to
                                                           produce the logic function, but the
                                                           complementary set allows for zero
                                                           static power dissipation.

                                  ECE 813S03, Prof. A. Mason                      Lecture 1, Page 11




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