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A Prototype LED_PIN diode optical data link for the ATLAS .. - DOC


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									System Tests of Radiation Hard Optical Links for the ATLAS SemiConductor Tracker
D.G. Charlton, J.D. Dowell, R.J. Homer, P. Jovanovic, I.R. Kenyon, G. Mahout, H.R. Shaylor, J.A. Wilson The University of Birmingham, Great Britain. A. Rudge CERN, Geneva, Switzerland J. Fopma, I. Mandići, R.B. Nickerson, P. Shield, R. Wastie, A.R. Weidbergii Oxford University, Great Britain. L-O. Eekiii, A. Goiv, B. Lund-Jensen, M. Pearce, J. Söderqvistv Royal Institute of Technology (KTH), Stockholm, Sweden M. Morrissey and D.J. White Rutherford Appleton Laboratory, Great Britian.

Abstract A prototype optical data and Timing, Trigger and Control transmission system based on LEDs and PIN-diodes has been constructed. The system would be suitable in terms of radiation hardness and radiation length for use in the ATLAS SemiConductor Tracker. Bit error rate measurements were performed for the data links and for the links distributing the Timing, Trigger and Control data from the counting room to the front-end modules. The effects of cross-talk between the emitters and receivers were investigated. The advantages of using Vertical Cavity Surface Emitting Lasers (VCSELs) instead of LEDs are discussed. PACS: 29.40.Gx; 85.60.Jb; 85.60.Me; 29.90.+r Keywords: LHC; Data transmission; Optoelectronics; Radiation tolerance.

1. Introduction
Optical links will be used in the ATLAS SemiConductor Tracker (SCT) [1] to transmit data from the front-end modules to the off-detector electronics and to distribute the Timing, Trigger and Control (TTC) data from the counting room to the front-end modules. The initial developments were based on GaAlAs LEDs emitting at around 820 nm, radiation hard multi-mode optical fibre and epitaxial silicon PIN-


Visitor from the Josef Stefan Institute, Ljubljana, Slovenia. Corresponding author. Email: t.weidberg1@physics.ox.ac.uk iii Now at Cap Gemini, Stockholm, Sweden. iv Currently at EP Division, CERN, Geneva, Switzerland. v Now at Allgon Systems AB, Solna, Sweden.


diodes. The data links operate at a rate of 40 Mbits/s using the NRZi format in order to minimise the emitter on-time and hence maximise the component lifetime. This data transfer rate is sufficient to keep the queuing losses below 1 % for the worst case strip occupancies [2]. The TTC links use bi-phase mark (BPM) encoding to transmit the 40 MHz bunch crossing clock together with a 40 Mbits/s control data link. This paper reports results from prototype LED/PIN-diode optical links, which are shown to meet the necessary requirements. An overview of the links system is given in Section 2, including a description of the main elements. The requirements imposed by the rest of the SCT system are also summarised. The results of detailed tests of the links, including bit error rate (BER) measurements, are given in Section 3. The performance of the system, although within specifications, may be improved for the final system, as described in Section 4. One main improvement is the replacement of the on-detector LEDs with Vertical Cavity Surface Emitting Laser diodes (VCSELs). Other tests of the components of the optical links system have been reported elsewhere: on the radiation hardness of the optoelectronic components [3,4]; on the radiation hardness of the fibre [4,5]; and on the performance of an LED/PIN- diode link for ATLAS [2].

2. Optical Transmission System
A block diagram of the prototype optical links system is shown in Fig. 1. The data link is provided by the LED Driver Chip (LDC) which drives an LED to send light into a radiation hard multimode fibreii. The light is received by a PIN-diode array and the resulting electrical signal is amplified and discriminated in the receiver module. The TTC link is provided by the BiLED chip which takes the 40 MHz Clock and the TTC data and creates a BPM encoded signal which drives a VCSEL. The VCSEL light is coupled into the same type of radiation hard multimode fibre as used for the data link and is received by a PIN-diode. The electrical signal from this PIN-diode is amplified and decoded by the DORIC3 chip which extracts the 40 MHz clock and decoded data. The specifications for the system are summarised in Table 1.
Table 1. Specifications of the optical transmission system.

Parameter Data link speed Maximum BER for data link TTC link data rate Maximum BER for TTC link Clock speed for TTC link Maximum jitter for recovered clock (RMS) Maximum radiation dose (in silicon) Maximum 1 MeV equivalent neutron fluence (for silicon)

Value 40 Mbits/s 10-9 40 Mbits/s 10-9 40 MHz 1 ns 10 Mrad 3.1014 n/cm2

Non Return to Zero (i.e. the signal is high during the transmission of a „one‟ and goes low while transmitting a „zero‟). ii Fujikura 50/60/125/250 radiation hard fibre. Fujikura, Koto-Ku, Tokyo, Japan.


Data in
40 MHz Clock Decoded Data

Data out A
40 MHz Clock T C Data T

Fig. 1. Block diagram of prototype optical links. LDC = LED Driver Chip, DORIC3 = Digital Opto Receiver IC, BiLED = bi-phase mark (BPM) encoding and LED Driver IC, Amp = preamplifier, Disc = discriminator, A = optical attenuator.

2.1 On-detector Components The main on-detector components are the LED/PIN-diode package and the LDC and DORIC3 chips. They are mounted on a low mass ceramic opto-hybrid connected to a low mass aluminium tape with power supply lines provided via a flexible kapton cable. 2.1.1 LED/PIN-diode package The LED/PIN-diode package consists of two GaAlAs LEDs and one epitaxial Si PINdiodei mounted on a low mass silicon substrateii. More details of the package and the LEDs are available in reference [2]. Results for radiation hardness tests of the LEDs are available in reference [4]. The PIN-diodes have been shown to be radiation hard [3]. 2.1.2 LDC and DORIC Fabrication The LDC and DORIC were designed in the AMSiii 0.8 m BiCMOS process. This is not a qualified radiation hard process, however the following techniques were adopted in order to improve radiation hardness: only npn bipolar transistors were used; the transistors were run at relatively large currents to ensure small changes in the DC current gain (with radiation; and the circuits were designed to be tolerant to large changes in . The results of radiation testing are discussed in Section 3.2.2. The LDC was designed at the same time as DORIC3 and processed on the same multi-project wafer. Both the LDC and DORIC3 were designed to fit within the size envelope defined by the opto-hybrid assembly.


Centronic Ltd., Electro Optics division, Croydon, U.K. Marconi Electronic Systems, 520/1/02648/000, Caswell, Towcester, U.K. iii Austria Mikro Systeme International AG, Schloß Premstätten, A-8141 Unterpremstätten, Austria.


2.1.3 LDC The LDC has two main circuit blocks: an LVDSi compatible input stage and a highcurrent output driver. The input stage responds to low amplitude differential signals with up to  1V common mode voltage and provides a correct amplitude and DC level to drive the output stage. The output stage is a large differential pair with a current source supplying the tail current. The tail current is adjustable from 0 to 50mA by means of an external control voltage. The circuit also has a parallel current source bleeding 5 % of the tail current continuously through the LED. This continuous current keeps the LED forward biased and improves the rise and fall times of the optical output. The LED anode is connected to the positive supply and the cathode is driven from an npn open collector output. The other collector of the differential pair is returned to positive supply so the current drain is constant and minimal decoupling is needed. The specifications are given in Table 2 and a simplified schematic diagram is given in Fig. 2.
Table 2. LDC specifications.

Parameter Number of independent circuits on one substrate Internal termination resistance for input Output switch current LED current control voltage range Power supply voltage Power dissipation for 20 mA current Operating temperature Test temperature

Value 2 100 0-50 1.6-6.6 4  0.2 160 -10 30

Units  mA V V mW 0 C 0 C

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Fig. 2. LDC simplified schematic diagram.


Low Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI) Draft 1.3. IEEE P1596.3-1995


2.1.4 DORIC3 The current output signal of a PIN-diode is DC coupled into the input stage of the DORIC3 (see Fig. 3) which is a low noise transimpedance amplifier. The transimpedance amplifier has active supply line filtering to minimise induced noise from the supply and feedback from the following stages. The output is AC coupled into a differential gain stage. The AC coupling removes DC offsets from the signal; this is possible because BPM encoded signals have no DC component. The PINdiode bias voltage is also passively filtered to minimise noise. All of the analogue and digital circuitry following the transimpedance amplifier has been designed with low-level differential current mode circuitry to minimise feedback and make it insensitive to supply line noise and variation. A comparator produces digital outputs from the amplified signals. A decoding circuit re-generates the clock, extracts command signals and synchronises them to the clock. Clock and command signals are output as LVDS compatible voltage levels. Two sets of clock and command outputs are available: normal outputs to drive a local module and reserve (or redundant) outputs to drive an adjacent module (in case of TTC link failure). The normal and redundant outputs may be switched on and off independently by means of control lines. If not in use the redundant outputs are switched off in order to minimise interference. The specifications for the DORIC3 are given in Table 3 and a simplified block diagram is shown in Fig. 3.
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Fig. 3. Block diagram of the DORIC3 chip.

Table 3. DORIC3 specifications

Parameter Input current low level Input current high level Supply voltage Control line low level Control line high level Operating temperature Power dissipation Test temperature

Value 0 6-12 4  0.2 0 1 4 1 -10 250 30

Units mA mA V V V 0 C mW 0 C


2.1.5 Opto-hybrid and kapton cable A photograph of the opto-hybrid/kapton cable assembly is shown in Fig. 4. The final version of the circuit is likely to be a single compact structure, but the current prototype is made of three separate items. The „kapton cable‟ is a double-sided copper-on-kapton flexible circuit which connects power supplies and control levels from the low mass aluminium tapes to the corresponding module and opto-hybrid, and distributes the redundant clock and command signals to the adjacent modules. The „aluminium plate‟ stiffens the flexible circuit in the area around the opto-hybrid and provides a thermal connection to the cooling pipe. Finally, the „opto-hybrid‟ is a thick film circuit printed on a ceramic substrate which carries the LED/PIN-diode package and the DORIC and LDC ICs. A pair of 1 mm pitch zero insertion force connectors are used to connect the kapton cable to low mass aluminium-on-kapton power tapes. The module connector and the redundant channel connectors are 1.27 mm pitch through-hole types. The connections between the opto-hybrid and the kapton-cable are made using wire bonding.

Fig. 4. The LED/PIN-diode package and DORIC and LDC ASICs mounted on a ceramic opto-hybrid.


2.2 Off-detector components The off-detector electronics sends optical TTC data to the module and receives the optical data signal. The electronics for the TTC distribution is based on the BiLED chip which encodes the BPM data and drives a VCSEL. The data receiver module uses a silicon PIN-diode array with the PIN-diode mounted on a PCB and connected to an amplifier and discriminator to produce digital outputs. 2.2.1 The BiLED Chip The ASIC used to drive the VCSELsi sending the TTC data to the front-end modules is the BiLED chip. The BiLED chip was fabricated in the 0.7 ES2ii CMOS process. The BiLED chip was designed to drive LEDs but it can also be used to drive VCSELs. VCSELs were used in these studies in order to provide a larger optical signal. A schematic diagram of the BiLED chip is shown in Fig. 5. An external Phase Lock Loop (PLL) generates the 80 MHz clock for a simple state machine which generates the BPM encoding. The data can be delayed by up to 32 clock cycles in order to ensure that the trigger latency is correct for the front-end readout chip. The clock delay can be further adjusted in fine steps (500 ps) in order to synchronise the clock received by the front-end readout chip with the bunch crossings in the LHC machine. The amplitude of the optical pulse from the VCSEL can be adjusted by an external control voltage which is set by a DAC. The rise and fall times of the drive signal for the VCSEL can also be adjusted by control voltages in order to ensure a mark to space ratio of 1:1. This feature was designed for LEDs and did not work so well for VCSELs as it was harder to control the rise time of the optical signal. In the work described here, precise timing control of the optical signal from the VCSEL was achieved by the Vernier Board (see Section 3.2.1).

Biphase Mark LED Driver


Fine Delay 500ps steps 128 steps



Cycle Delay Select Data IN

Data Cycle Delay 32 Cycles

Fine Delay 500ps steps 128 steps

Biphase Mark Encoder

LED Driver

Drive Strength Fine Delay Select Edge Slew Rate

Fig. 5. A schematic diagram of the BiLED ASIC.

i ii

Honeywell HFE 4081 ST coupled VCSEL. European Silicon Systems, now owned by ATMEL.


2.2.2 The PIN-diode array chip An eight-way silicon PIN-diode arrayi was used in the off-detector receiver part of the link. An eight-way fibre-ribbon is connected „head-on‟ to the PIN-diode array with a MT-connectorii, as shown in Fig. 6. This approach is simple and cheap since it includes no „V‟-grooves, pig-tailing, mirrors or light guides. A schematic detailing the layout of the chip is shown in Fig. 7.

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Fig. 6. The layout of the PIN-diode array assembly. An 8 fibre ribbon is aligned to the PIN-diode array by an MT-connector located via two precision pins.

The PIN-diode array chip is precision cut using a diamond edge and glued onto a ceramic carrier substrate. Two sets of three single-shot laser cut holes in the substrate act as a reference when aligning the chip corners through a microscope. Two larger multi-shot laser cut holes locate the MT-connector alignment pins. Once aligned, the chip is covered by a 50 m thick cover-glassiii which provides a reference surface for the MT-connector. The cover-glass is coated to reduce reflections which may cause cross-talk or possible optical feedback noise in a laser emitter. The ceramic carrier

Developed in collaboration between KTH, Stockholm, Sweden and AME AS, Postboks 83, N-3191 Horten, Norway as AE 9708. ii Mechanically Transferable ferrule. iii CMX, manufactured by Pilkington Space Technology. Glued in place with optically transparent epoxy resin (EPO-TEK 301-2), manufactured by Epoxy Technology Inc., MA, USA.


substrate with the PIN-diode array, cover-glass and the MT-connector alignment pins are mounted onto a DIL-package. The MT-connector is held in position with a support consisting of two hinged arms which are fixed with a screw. The size of the package is about 10 mm x 20 mm.

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Fig. 7. The layout of the PIN-diode array chip.

The response of a single PIN-diode element was measured with a narrow beam of laser light. The measured response was compared to a calibrated reference detector. The response was determined to be 0.58 A/W for a bare chip and 0.50 A/W after the cover-glass was glued into place. These results correspond to quantum efficiencies of 0.85 and 0.72, respectively. A temperature rise of 10oC increased the response by approximately 0.7 %. The dark current was measured to be 0.09 nA at 20 oC. The noise equivalent power (NEP) of the PIN-diode array was measured to be 110 (190) pW for an electronics bandwidth of 100 (300) MHz. Even with the worst case NEP, the PIN-diode array has an intrinsic dynamic range exceeding 20 bits.


The capacitance of a PIN-diode array element decreases as the reverse bias voltage is increased, as shown in Fig. 8. A reverse bias voltage of ~30V is sufficient to reduce the capacitance of a central (outer) element below 0.8 pF (1.0 pF).
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Fig. 8. The capacitance of a central PIN-diode element plotted as a function of the reverse bias voltage, measured at 1 MHz.

There are three sources of cross-talk between PIN-diode array elements: scattering of light onto neighbouring PIN-diode array elements from reflections between the connector and PIN-diode array surface, light scattered within the PIN-diode array chip and electrical cross-talk due to capacitive coupling. The latter two are minimised by placing a grounded guard ring around the PIN-diode elements on the chip. Reflections are minimised by the coating on the cover-glass. To measure the cross-talk within the PIN-diode array without a cover-glass, a narrow laser beam was shone onto the middle of a single PIN-diode element and the signal in adjacent elements was measured. The cross-talk was less than 0.05 %. The cross-talk with the cover-glass in place was measured with a MT-connector coupled to the PIN-diode array. A single channel was pulsed with a 20 ns shaped signal and the magnitude of the cross-talk (measured on the signal peak) was 0.08 % for adjacent channels and 0.04 % for nextto-adjacent channels. 2.2.3 Amplifier and Discriminator In order to facilitate screening and enable the testing of different circuit configurations depending on optical light power, the receiving circuits were constructed on the mother-daughter board principle. The PIN-diode array is connected to a low noise amplifieri on a daughter board. The amplifier has a measured equivalent input noise of 1.7 pA/Hz (this is about 30 % lower than the manufacturer‟s specifications) and a differential transimpedance gain

Analog Devices AD8015.


of 20K. The circuit is linear over  40A, and has a bandwidth in excess of 200 MHz. The mother board contains the second stage differential amplifiers, discriminators and LVDS drivers. The analogue bandwidth of the system was defined by RC networks to be 100 MHz. SPICE simulation of the circuit showed the noise bandwidth to be 132 MHz, corresponding to the measured cut-off slope of between 20 and 40 dB/decade, giving a total equivalent input noise of 20 nA. The amplifier output was DC coupled into a discriminator ICi in order to eliminate rate dependent effects with the NRZ data stream. For some tests a capacitor was added in order to compare the performance of the DC coupled system with an AC coupled one. 2.3 Test System The test system used to perform BER measurements consists of a sequencer module (SEQSI) and a specially designed BER test board (LITMUS). A 50,000 bit deep pseudo-random sequence is stored in SEQSI. This data is fed into LITMUS at a rate of 40 Mbits/s. The bit stream is also fed into the links and the output is fed into the second input of LITMUS. LITMUS contains an XOR gate which was used to detect bit errors by comparing the output of the data stream generated by SEQSI with the reconstructed data at the output of the optical link. A programmable delay is used to account for the time delay between the recovered and input data streams. A 10 bit counter is used to count the bit errors. The counter can be read from a VME system. A block diagram of the system is shown in Fig. 9. This system was used to measure BERs for both the data and the TTC link separately as well as for the combined two way links (see Fig. 9).

3. System Test Results
In this section results are reported on the BER measurements for the prototype (data, TTC and combined) links. Measurements of the cross-talk between emitters and receivers are described along with measurements of the jitter of the recovered signals. 3.1 Data links


LeCroy MVL407.



LE D P IN Opto-R eiver ec


V ernier





Fig. 9. Bit Error Rate test system. SEQSI = sequencer, LITMUS = Link Test Module Using SEQSI, BILED = bi-phase mark (BPM) encoding, Vernier = low jitter bi-phase mark delay adjust.

3.1.1 BER dependence on optical power for data links Pseudo-random data were sent down the link using an LED driven by the LDC chip as the light source. The data were received by the opto-receiver. The BER of this system was measured at different levels of optical power set by the LED forward current. In order to be able to operate the link at low light levels, but with a sufficient LED drive current to get undistorted signals, the light was attenuated by a fixed factor using an air gap attenuator. The calibration of the optical power at the receiver end versus LED drive current was done using an optical power meteri, taking into account the duty cycle of the signal. The results of the BER measurements are shown in Fig. 10. The measurements were done with both AC and DC coupled receiver amplifiers.
1.00E+00 1.00E-01

1.00E-02 1.00E-03


1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Optical power (µW)


MEGGER OTP620 optical power meter.


1.00E+00 1.00E-01

1.00E-02 1.00E-03


1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Optical power (µW)

Fig. 10. The BER as a function of optical power for (a) the AC coupled receiver, and for (b) the DC coupled receiver. The points with error bars show the measured values and the curves are the results of the fits described in the text.

For an AC coupled system, in the absence of non-Gaussian noise, the BER as a function of optical power is given by the following equation:

1  A  2T   A  2T  BER  erfc   erfc  4  2 2   2 2 
where A is the optical amplitude, T is the difference between the threshold and A/2 (which is constant for an AC coupled receiver) and  is the RMS of the noise. The function erfc is the error function defined as:

erfc(t ) 


e  t


t 2

dt .

For a DC coupled amplifier with fixed threshold, the BER is given by:

1  AT   T  BER  erfc   erfc  4  2   2 
where A is the optical amplitude, T is the threshold and  is the RMS of the noise. Since the exact value of the threshold was not known, a fit was performed to the BER versus optical power with both  and T as free parameters. For the AC coupled receiver the results from the fit are:  = (0.034  0.002) W, T = (0.044  0.008) W.


For the DC coupled receiver the results from the fit are:  = (0.039  0.002) W, T = (0.45  0.02) W. Allowing for the responsivity of the PIN-diode of 0.5 A/W this result corresponds to an equivalent noise at the input of the amplifier of 17 (20) nA for the AC (DC) coupled receiver. This is compatible with the expected value of 20 nA estimated in Section 2.2.3. One can see in Fig. 10 that the chosen functions describe the dependence of BER on input optical power reasonably well. This implies that there is no serious nonGaussian noise present in the system. The required BER of 10-9 can be achieved with an optical power higher than ~0.5W which is easily provided by a LED (see Fig. 11). 3.1.2 Long term threshold stability As explained in Section 2.2.3 the data links are DC coupled and it is therefore important to check the stability against possible threshold shifts. To study the stability of the receiver, a long term BER measurement was done without readjusting the threshold. With an input optical power of 20W, the measured BER was 4·10-12 over a period of 64 hours.


DL002 LEDX (irradiated LDC) DL002 LED (irradated LDC)

LED light output (µW)










0 0 5 10 15 LED current (mA) 20 25 30

Fig. 11. Graph of the LED optical power versus drive current for 8 LEDs in 4 LED/PIN-diode packages. In the legend, LEDX denotes the diode closer to the PIN-diode in the opto-package.

3.1.3 Cross-talk The cross-talk in the receiver was measured both in terms of the voltage amplitude at the analogue output of the amplifier and in terms of the BER. With an optical input generating a signal of 500 mV at the output of the receiver the cross-talk on the neighbouring channels was measured to be 5 mV. The BER caused by pulsing neighbouring channels was measured to be less than 10-9 at 20W optical power into each channel. 14

3.2 TTC links 3.2.1 BER timing scan The principle of the bi-phase mark (BPM) encoding of the control data is shown in Fig. 12. Transitions every 25ns are used for transmission of the bunch crossing clock and „zeros‟ in terms of data. Additional transitions between the bunch crossing edges are generated to transmit „ones‟. Note that „ones‟ can be transmitted as either rising or falling edges.
0 0 0 1 0 0 0 1 0 0 0







Fig. 12. Bi-phase mark (BPM) encoding of data.

The DORIC3 chip recovers the clock and decodes the data from the received BPM encoded signal. From the received clock edges it recovers rising edges of the 40MHz clock while the falling edges are generated internally. The data pulse is generated from the input BPM data edge. In order to correctly recover the „one‟ sent, this pulse has to be „hit‟ by the internally generated back-edge of the recovered clock. In DORIC3 the generated data pulse is very narrow (about 2 ns). This makes the data recovery extremely sensitive to jitter and BPM timing especially to the time between the clock edge preceding the data edge and the data edge itself. To study this the Low Jitter Timing Vernier board was made. This board takes the BPM signal generated by the BiLED chip as input. It reduces the jitter of the input to less than 250 ps peak-to-peak and allows for the time adjustment of all four BPM signal transitions. A scan of BER measurements as a function of clock to data edge time is shown in Fig. 13.
1.00E+00 1.00E-01 Clock to Rising Data Edge Scan 1.00E-02 1.00E-03

Bit Error Rate

1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5

DL002 (irradiated) DL003 DL004 DL006

Clock to data edge (ns)


1.00E+00 1.00E-01 Clock to Falling Data Edge Scan 1.00E-02 1.00E-03

Bit Error Rate

1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5

DL002 (irradiated) DL003 DL004 DL006

Clock to data edge (ns)

Fig. 13. A scan of BER measurements versus clock to data edge time. The lowest BER values (1.9·10-9) are 90 % CL upper limits corresponding to observing 0 errors in a 30 seconds measurement.

The results shown in Fig. 13 mean that the data pulse generated in DORIC3 is about 2 ns long and that it is displaced relative to the recovered clock back edge, i.e. not in the middle of the 25 ns interval. One can see that the scan gives similar results for both rising and falling data edges and that the device to device variations are not large. In order to recover the BPM data with DORIC3 at a low bit error rate the light signal should be tuned so that the clock to data edge time is around 11 ns. The oscilloscope picture of such a light signal, obtained with Tektronix P6701 optical probe is shown in Fig. 14. With the timing set as in Fig. 14, the DORIC3 operated with a BER of 2·10-12, which is significantly lower than the ATLAS requirement of the BER being less than 10-9.

11 ns

11 ns

Fig. 14. BPM signal obtained with a Tektronix P6701 optical probe. The clock to data edges are set to 11 ns in order to get a low BER data decoding with DORIC3.

3.2.2 BER versus optical power scan The BER measurements of TTC links were done at different values of optical power received by the PIN-diode. The results of the scan are shown in Fig. 15. One can see that there is a wide operating range easily achievable using VCSELs as the light source at the sending end (the VCSEL light was attenuated to get a clean optical waveform at such a low power). The degradation in performance at low optical power is caused by a worsening of the signal to noise ratio, while at high power it is caused by the onset of amplifier saturation affecting the timing. On one of the opto-packages, the DORIC3 chip had been irradiated with a neutron fluence of 1014 n/cm2 at ISIS and a 24 GeV proton fluence of 3 1014 p/cm2 at the CERN PS. As can be seen from Fig. 15 the performance of this opto-package was not degraded relative to the opto16

packages with the un-irradiated DORIC3s. Four other DORIC3s and four LDCs were also irradiated to these fluences and were found to be functional after irradiation although no analogue measurements were performed on these devices.
1.00E+00 DL002 (irradiated) 1.00E-01 1.00E-02 DL004 DL006


1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 0 20 40 60 80 100 120 Optical power into PIN (µW)

Fig. 15. BER versus optical power received by the PIN-diode. Low BER values (the flat part at 1.9·109 ) are 90 % CL upper limits corresponding to observing 0 errors in a 30 seconds measurement.

3.2.3 Dependence of clock jitter on optical power Together with transmitting command data with low BER, the TTC link must provide the 40 MHz bunch crossing clock to the front-end electronics. The rising edges of the clock are recovered from the 20 MHz BPM transitions while the falling edges of the 40 MHz clock are generated internally. The rising edges determine the system timing and must be recovered with low jitter. A digital oscilloscopei with a histograming facility was used to measure the recovered clock period (rising edge to rising edge) and the RMS spread of these measurements. The oscilloscope picture of the recovered clock and the histogram of the period measurement is shown in Fig. 16. The measurement was made with an optical power of 50 W. The period is exactly 25 ns and the RMS is very low (60 ps) and well within the specifcation listed in Table 1. The mean and RMS of the period were also measured as a function of the optical power received by the PIN-diode. The results of these measurements are shown in Fig. 17 and Fig. 18.


Lecroy Digital Oscilloscope LC374A.


Fig. 16. Oscilloscope picture of the recovered clock and the histogram of period measurements. The timebase is 5 ns per division for the clock trace and 0.1ns per division for the histogram.

DL002 (irradiated)

DL003 DL004


Recovered Clock Period (ns)










Optical Power (µW)




Fig. 17. Recovered clock period as a function of optical power (amplitude) received by the PIN-diode.
1 0.9 DL002 (irradiated) DL003 DL004 0.7 DL006 0.6 0.5 0.4 0.3 0.2 0.1 0 0 20 40 60 Optical Power (µW) 80 100 120

Fig. 18. RMS of the recovered clock period as a function of optical power (amplitude) received by the PIN-diode.

Sigma of Recovered Cock Period (ns)



3.3 Loop Configuration 3.3.1 BER for the loop configuration The full functionality of the link is to deliver clock and command to the module via the TTC link and to send data from the module via the data link simultaneously. To test this the bit error rate measurement in a loop configuration („two way link‟) was made. In this test the pseudo-random data is BPM encoded by the BiLED chip and sent to the DORIC3 via the optical fibre. The DORIC3 recovers the data and its LVDS output is fed into the LDC which sends the NRZ data using an LED and fibre to the opto-receiver. The opto-receiver recovers the data and its output is fed to the BER tester (see Fig. 9). The optical power of the TTC link was set to 65 W and the drive current of the LED was set to 20 mA, giving an optical power of ~20 W. A BER lower than 10-10 was measured for the two way link. 3.3.2 Cross-talk measurements Cross-talk between the TTC and data link can be observed in the sense that pulsing the LDC (data link) can cause bit errors in the DORIC3 data recovery. This cross-talk depends on two parameters – the LED drive current amplitude in the LDC, and the optical power received by the PIN-diode. A range of settings could be found where the cross-talk is low enough to allow the two way link to operate at a low bit error rate, as reported in Section 3.3.1. These measurements were also made on an equivalent optopackage with the LEDs replaced by VCSELsi and the cross-talk was of a similar magnitude despite the fact that the optical output was two orders of magnitude higher. This result demonstrates that the origin of the cross-talk is electrical rather than optical. The cross-talk was measured by setting the LED current amplitude to 20 mA and pulsing the LDC with 20 MHz pulses from a pulse generator. At the same time the BER of the TTC link was measured as a function of the optical power received by the PIN-diode. The results of the measurements are shown in Fig. 19. Comparing this figure to Fig. 15 one can see that the effect of cross-talk is a reduced dynamic range. However, it is still sufficiently small to allow for simultaneous operation of both data and TTC links at low BER.




1.00E+00 1.00E-01 1.00E-02
DL002 LEDX (irradiated) DL002 LED (irradiated) DL002 (irradiated) DL004 LEDX

DORIC Bit Error Rate

1.00E-03 1.00E-04


1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 0 20 40 60 80 100 120 Optical power into PIN (µW)

DL004 DL006 LEDX DL006 LED DL006

Fig. 19. The bit error rate of TTC link as a function of optical power received by the PIN-diode when LEDs on the optopackages have been pulsed with 20 MHz pulses, with amplitude of 20 mA. LEDX is the diode closer to the PIN-diode on the package.

The bit errors caused by cross-talk occur only when 'ones' are sent to the DORIC3. They are caused by the increased jitter of the back-edge of the recovered clock. This edge must “hit” the data pulse as explained in Section 3.1. The dependence of the BER on the RMS spread of the front- to back-edge time of the recovered clock is shown in Fig. 20. One can see that roughly the same BER is measured at the same value of the RMS, independently of whether the LED of the data link was pulsed or not. In Fig. 21 the RMS spread of the front- to back-edge separation, is shown as a function of the optical power. It can be seen that the RMS is increased if the LED is pulsed, thus explaining the cross-talk bit errors. The data bit errors when „zeros‟ are wrongly recovered as „ones‟ start to be important at much lower optical powers when the recovered clock RMS spread is already unacceptable and are therefore irrelevant.
1.00E+00 1.00E-01 1.00E-02

DORIC Bit Error Rate

1.00E-03 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 1.00E-09 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

DL002 DL003 LEDX DL003 LED DL003 DL004 LEDX DL004 LED DL004 DL006 LEDX DL006 LED DL006

Sigma of Positive Width of Recovered clock (ns)

Fig. 20. Bit error rate as a function of the RMS spread of the front- to back-edge time of the recovered clock. Measurements were done without pulsing the data link and when pulsing data links LEDs (LEDX and LED in the legend, respectively).



Sigma of Positive Width of Recovered Clock (ns)

0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0
0 5 10 15 20 25






Optical Power (µW)

Fig. 21. RMS spread of the time from the front-edge to the back-edge of the recovered clock as a function of the optical power received by the PIN-diode. Measurements were done without and with pulsing the data link LEDs (LEDX and LED in the legend, repsectively).

4. Proposed Improvements to the system
The system described in this paper worked reliably and could meet the ATLAS specifications. The principal problem was that a very precise timing system was required for the distribution of the TTC signals and this would not be practical in a large scale system. The main improvements to the system will be achieved in the next generation of the BPM decoding chip, DORIC4, where the timing window to accept data pulses is effectively increased to 12.5 ns (half the clock period) compared to the 2ns for DORIC3. The other important change for DORIC4 is that it has been optimised for the much larger optical power available from VCSELs as compared to LEDs. Thus DORIC4 no longer requires a low noise preamplifier for the first stage and a fully AC coupled differential input is used. This means that the effects of crosstalk between the emitters and receivers in the system are reduced to a negligible level. The other upgrade to this system is to replace the on-detector LEDs with VCSELs. This will increase the signal going into the off-detector amplifier by about two orders of magnitude which will greatly simplify the design of the system. Packaged arrays of PIN-diodes and VCSELs suitable for the off-detector opto-electronics are now available commerciallyi.

5. Conclusions
A prototype optical data transmission system based on LED/PIN-diodes has been described. The tests of the data links and TTC links show that both work well and meet the ATLAS specifications. The effects of cross-talk between the emitter and the receivers in the on-detector opto-electronics has been studied. Although this was significant, it did not prevent the system working at the required level. With the improvements discussed in Section 4, it should be possible to construct a reliable large scale system suitable for the readout of the ATLAS SCT detector.


MITEL 4 channel VCSEL array 4D469 and 4 channel PIN-diode array 4D470.


Financial support from the UK Particle Physics and Astronomy Research Council and from the Naturvetenskapliga forskningsrådet (NFR) and the Forskningsrådsnämnden (FRN) is acknowledged. One of us (I.M.) wishes to thank the Slovenian Science Foundation and the Ministry of Science and Technology, Slovenia for support. We wish to thank Dr. C. Buttar and Dr. M. Edwards for help with irradiating the ASICs. We wish to thank Dr. J. Hall of Marconi Electronic Systems for many useful discussions.

[1] ATLAS Inner Detector Technical Design Report, CERN/LHCC-97/17. [2] D. Buira-Clarke et al., Nucl. Inst. and Meth. A 399 (1997) 119. [3] J.D. Dowell et al., Nucl. Inst. and Meth. A 424 (1999) 483. ATLAS Inner detector notes INDET-182 and INDET-200 available from WWW: http://alice.cern.ch/ATLAS/ [4] J. Beringer et al., Radiation hardness and life time studies of LEDs and VCSELs for the optical readout of the ATLAS SCT, to be published in Nucl. Instr. and Meth. A. Information also available from WWW: http://www.cern.ch/ATLAS/lGROUPS/INNER_DETECTOR/sctnew/Electronics/link s/index.html [5] D.G. Charlton et. al., Development of Radiation-hard VCSEL/PIN-diode optical links for the ATLAS SCT, pp349, 353, proceedings of the 4th Workshop on Electronics for LHC Experiments, CERN/LHCC/98-36, Rome, September 1998.


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