Accuracy, Fast-Response, Cost-Efficient Solar Cell Regulator Suitable for Low-Power Applications Jiann-Jong Chen, Fong-Cheng Yang, Hsin-Tung Li and, Yuh-Shyan Hwang Abstract— An accuracy, fast-response, cost-efficient solar as remote terminals. In space applications, this is the cell regulator suitable for low-power applications is only source of power, barring nuclear alternatives. The presented. The proposed regulator is a current-to-voltage need for small size and low weight has necessitated the regulator and has been fabricated with TSMC 0.35µm use of high-speed switching voltage regulators. The I-V 2P4M CMOS technology. The measurement results show Curves of a Si-base solar cell under different radiances the settling time which can achieve 400ns with 0.5% error is shown in figure 1. for full load-current. Furthermore, the line and load regulations are 14µV/mA and 8ppm/mA, respectively. The The characteristic of the solar cell is like a current current efficiency can be up to 99.3% for 150mA output source with an equivalent series resistor Rs and an current. The active chip area is only 226µm x310µm. equivalent parallel resistor Rp, its modeling can be shown as figure 2. The resistor Rs is small and can be Index Terms: current-to-voltage regulator, current- considered as zero in most of the applications. The mode voltage regulator, transient response. resistor Rp can be considered as infinity to simplify the circuit analysis. I. INTRODUCTION The current interest in commercial green power in the developed world is about 25 years old, starting in the mid-1970s after the first oil shock. Many a billion dollars and many years later, the public is asking if green power is for real. Electricity derived from any renewable energy source is considered “green” because of the negligible impact on greenhouse gas emissions. In terms of commercial energy, this list currently includes hydro, wind, biomass, geothermal, and solar. Now there is a broader goal: to minimize the emission of CO2 (the most common global warming gas) that results from the burning of fossil fuels. It is possible to generate electricity from the thermal part of the solar spectrum. This is generally done by concentrating the incoming sunlight and then trapping its heat, which can Figure 1: I-V Curves of a Si-base solar cell under different raise the temperature of a working fluid to a very high radiances. degree to produce steam and then generate electricity. The concentration part of this explanation is very As the solar cell is used in the application, which important, as that is what allows the sunlight to produce allowed the larger voltage variation, it is a good energy enough heat to be used to generate electricity. Notice resource. However, in most of the application, the load that this process is different from that of a photovoltaic can not be supplied a voltage source with larger panel where the sunlight is directly converted into variation. Therefore, we need a current-to-voltage electricity without the intermediate heat collection. regulator, as shown in figure 3, suitable for solar cell applications. There are some regulators have been Photovoltaic conversion of solar energy is one of the proposed in previous works [1-3]. However, they are most promising ways of meeting the increasing energy not cost-efficient in low-power application. On the demand. The technology of photovoltaics has evolved other hand, their transient responses are not fast enough and is vying to become an economical alternative to and their accuracy is not good enough. So, we proposed other power sources in certain niche applications such an accuracy, fast-response, cost efficient current-to- voltage regulator suitable for low-power solar cell regulations. The first stage is the differential pair, applications in this paper. detects the difference between the reference voltage (Vref) and the feedback signal (Vfb), so as to provide error signal to the power transistor for voltage regulation. The power transistor is designed to operate Rs in saturation region at dropout to reduce the transistor RLoad size and the parasitic gate capacitance .Consequently, Rp the slew rate at the gate of the power transistor is improved due to the smaller gate capacitance. Is Figure 5 shows the detail circuit of the proposed regulator. The transistors Ma10-Ma14 form a single-stage differential pair and the high-swing second stage is composed of Ma21-Ma23. In addition, a transconductor boosting circuitry  is formed by Mb0-Mb2 which is Modeling of solar cell used to increase gm2 to enhance the accuracy of the Figure 2: The modeling of solar cell connected with loading output voltage. The current-mode regulator mainly resistor. display as output voltage and time that the voltage return stable, when the load current change in the twinkling of an eye. Those can affect the transient response including output capacitor, output capacitor Solar Current-to-Voltage equivalent series resistance (ESR), and maximum load Load Cell Regulator current, etc. In the following, when the loading changes, we will analyze the output voltage in several parts. When the loading draw the current from regulator suddenly, the Figure 3: The proposed regulator is applied with solar cell. regulator does not offer a flood of current, due to smaller the unit gain frequency. This action makes the In this paper, a description of proposed regulator will output voltage to product a voltage dip, and the output be included in section II, and the small-signal analysis capacitor offered a large amount of current that load is shown in section III. The experimental results of needs temporarily, flowed into Vout by Cout in this proposed regulator are shown in section IV. Finally, the moment. However, there are some tradeoffs among the conclusion is made in section V. stability of conventional linear regulators and other II. CIRCUIT DESCRIPTIONS performances, such as the transient response, maximum load current, current efficiency, and accuracy of the output voltage, etc. Hence, this paper provides EA Feedback resistors Iin Vout current-mode methods to improve the load transient response and maintain the stability simultaneously. It Vref has a better load transient response, less output noise 1st 2nd POWER Rf1 and ripples, and few off-chip components. The voltage stage stage Transistor Vfb Resr RL dips of the output voltage can be improved obviously Rf2 by the use of the low power bounce current mode Error Cm Rm circuit, as the output load current is switched from 0 to Cout Amplifier 150mA. Finally, we use the bandwidth extension skill to improve the output transient response for the output Figure 4: The architecture of solar cell regulator load current variation. By the bandwidth-extension skill, the value of the Miller compensation capacitor is The architecture of the proposed regulator is shown reduced. In addition, the voltage dips, and settling time in figure 4. The solar cell is considered as a current of the output voltage for the load transient response are source Iin. From figure 4, a moderate-gain stage is improved simultaneously by the use of the bandwidth inserted between the error amplifier and the power extension skill . transistor to reduce the value of the Miller capacitance and enhance the loop gain to improve line and load Figure 5: The proposed solar cell regulator 1 2 Cm C g Lg o (1 + sCout Resr )1 + sC m Rm − −s g m 2 g mn Ro 2 g m 2 g mn Lgo (1 + sCout Resr ) (2) Lg ( s ) ≈ ≈ s Cout 2 C p 2 Cout s Cout 2 C p 2 Cout 1 + 1 + s Cout Resr + +s 1 + 1 + s Cout Resr + +s p−3db g m 2 g mn Ro 2 g m 2 g mn p−3db g m 2 g mn Ro 2 g m 2 g mn (1) Cout >>(Cm，Cp2) >> Cp(1,2) , III. ANALYSIS OF FREQUENCY RESPONSE (2) gmn >> gm1 and gm2 , (3) Ro1gm2Ro2gmnRout>>Rm, (4) The parasitic zeros are high enough to be ignored. The transfer function is calculated in equation (2) and the loop gain at DC can be described as Rf1 Lg 0 = g g g R R R (3) R + R m1 m 2 mn o1 o 2 out f1 f2 Figure 6: The small-signal modeling of proposed solar cell ,and P-3dB is the dominant pole and can be obtained as regulator 1 Figure 6 shows the equivalent small-signal model of p−3dB = (4) the proposed regulator with the single Miller g m 2 g mn Ro1 Ro 2 Rout C m capacitance (SMC), where Ro(1,2), gm(1,2,n), and Cp(1,2) are After comparing the second-order function in (2) with a the output resistance, trans-conductance, and lumped standard second-order function, we can get the value of output parasitic capacitance of the gain stages, the nature frequency pc and the damping factor ς as respectively. Cm is the compensation capacitor, and Cout is the loading capacitance. Resr is the equivalent series shown in equation (5-6). resistance of Cout, and Rout can be written as g m 2 g mn pC ≈ (5) Rout = RL // Ropass // (R f 1 + R f 2 ) (1) C p 2Cout , where RL is loading resistance, Ropass is the output resistance of the power transistor and Rf1 and Rf2 are 1 1 g m 2 g mn Cout ς ≈ Resr + (6) the feedback resistances. 2 g m 2 g mn Ro 2 C p2 To solve the small-signal model, we assume following assumptions: IV. EXPERIMENTAL RESULT The proposed regulator has been implemented in 0.35µm 2P4M CMOS technology. The photograph of the regulator R is shown in figure 7, and the active chip Line Regulation Iout=150mA area is 226µm x310µm. The maximum output current is 1.8030 150mA with a dropout current of 1.0741mA. The 1.8010 proposed regulator with 1.8V output voltage is capable 1.7990 Vout [V] of operating from 152mA to 420mA, and consumes 1.7970 880µA quiescent current. Figures 8 and 9 show the line 1.7950 regulations at Iout =0mA (light load) and Iout =150mA (heavy load), and the measured line regulations are 1.7930 47µV/mA and 14µV/mA, respectively. The measured 1.7910 160 200 250 300 350 400 420 load regulation is 8ppm/mA (Iin=200mA), 40ppm/mA (Iin=300mA) as shown in figures 10-11. The Iin [mA] measurement results of the load transient responses of Figure 9: The Measured line regulation at Iout=150mA. the proposed regulator are measured under two conditions: light load to heavy load, shown in figure 12, and heavy to light, shown in figure 13. It is noted that the load transient responses are measured at 1-µF (Resr=8Ω) off-chip capacitors. The spectrum of outout Load Regulation Iin=200mA voltage is shown in figure 14 with 150mA loading 1.8010 current. Finally, we summarize the specifications of the proposed regulator in Table I. 1.8005 1.8000 Vout [V] 1.7995 1.7990 1.7985 0 20 40 60 80 100 120 140 150 160 180 Iout [mA] Figure 10: The Measured load regulation at Iin=200mA. Figure 7: The photograph of the proposed solar cell regulator Line Regulation Iout=0mA Iin=300mA 1.8100 Load Regulation 1.8060 1.8080 1.8060 1.8050 1.8040 1.8040 1.8020 Vout [V] 1.8030 1.8000 Vout [V] 1.7980 1.8020 1.7960 1.8010 1.7940 1.7920 1.8000 1.7900 1.7990 1 10 50 100 150 200 250 300 330 1.7980 Iin [mA] 0 20 40 60 80 100 120 140 150 160 180 Iout [mA] Figure 8: The Measured line regulation at Iout=0mA. Figure 11: The Measured load regulation at Iin=300 mA. Table I Summary of Measured Performance Technology TSMC 0.35µm 2P4M 150 mA Supply Current 152mA~420mA Iout Output Voltage 1.8V Settling time：400ns(0.5%error) Line Iout= 0mA 47µV/mA Voltage：30mV Regulation Iout= 150mA 14µV/mA 0 mA Load Regulation 8ppm /mA Quiescent Current 880µA Operation Temperature -55℃~130℃ Vout Settling Time Iout= 0mA to 150mA 400ns (0.5% error) Iout= 150mA to 0mA 600ns Iout= 0mA 30mV Voltage dip to 150mA Figure 12: The load transient response at Iin=200mA, Cout=1µF Iout=150mA to 0mA 70mV Light load to heavy load, voltage dip= 30mV. ( horizontal scale : Active Area 226µm x 310µm 200ns/div; vertical scale: 50mV/div and 50mA/div,from top to bottom) V. CONCLUSIONS An accuracy, fast-response, cost-efficient solar cell regulator suitable for low-power applications has been 150 mA designed with TSMC 0.35um 2P4M CMOS processes. Settling time：600ns(0.5%error) Iout Voltage dip：70mV The experimental results confirmed with the theoretical analysis are presented in this paper. The proposed regulator is suitable for current-type electrical source in 0 mA low-power applications. ACKNOWLEDGEMENT Vout The authors would like to thank National Science Council for project supporting and Chip Implementation Center for chip fabrication. This work was sponsored by NSC94-2213-E-027-052. REFERENCES Figure 13: The load transient response at Iin=200mA, Cout=1µF, heavy load to light load, voltage dip= 70mV. (horizontal  Kimiyoshi Kobayashi, Hirofumi Matsuo, Yutaka Sekine,” Novel scale :200ns/div; vertical scale: 50mV/div and 50mA/div,from top solar-cell power supply system using a multiple-input DC–DC to bottom) converter,” IEEE Trans. on Industrial Electronics, Vol. 53, No. 1, pp. 281-286, Feb. 2006.  Kimiyoshi Kobayashi, Hirofumi Matsuo, Yutaka Sekine,” An excellent operating point tracker of the solar-cell power supply system,” IEEE Trans. on Industrial Electronics, Vol. 53, No. 2, pp. 495-499, Apr. 2006.  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