EDEC Theme A Electronic Circuit Design

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					ChipWise Tutor Workbook

20/01/10

Week 15, 2000/01

NAME LOGIN COURSE 1) Aims The aim of ChipWise Tutor is to expose you to the design and simulation of CMOS VLSI circuits at both circuit and logic level. This is achieved through exercises, which cover circuit level design and its effect on performance, stick layout, simulation at transistor level and switch level and hierarchical design. The subject is presented in seven parts:        A Tutorial Guide to ChipWise Transistor Sizing of a Logic Inverter Design and Simulation of Simple Logic Gates Design of a 4-bit Shift Register Design of a Parallel Load Shift Register Design of a Universal Logic Module using a 4:1 Multiplexer Design of a Parity Generator

2) The Workbook This workbook is for you to log results as you work through the ChipWise Tutor course material. For each frame in this workbook, there is a corresponding workbook icon in the Web based courseware. As you work through ChipWise Tutor, whenever you see a workbook icon, you know you must complete the appropriate frame in the workbook. It should be handed in to your demonstrator when you have finished. 3) Screendumps Throughout this workbook, you will be asked to paste in the appropriate screendump from ChipWise. To do this, follow these steps:     Select the Monochrome option from the required window's men-bar. Press <Alt-Print Scrn> to copy the current window into the clipboard buffer. Place the cursor in the appropriate frame in the workbook, and use the Paste command from the MS Word Edit menu to copy the screendump into the workbook. Select the pasted image and scale it to fit the frame.

4) Module 1: A Tutorial Guide to ChipWise For the first module, A Tutorial Guide to ChipWise, there is no need to take notes … just work through the tutorial to get a feel for using the ChipWise design system and the Web based courseware which guides you in using the tools.

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Module 2: Transistor Sizing of a Logic Inverter
2.2 DC Analysis of Logic Inverter P-type width = N-type width Vinv = …………………………………………. P-type width = 2.5 x N-type width Vinv = …………………………………………. Why is this value closer to Vdd/2 than before?

2.3 Transient Analysis of a Logic Inverter P-type width = 2.5 x N-type width Paste the screendump from the output of SVIEW into this frame

Rise Time = ……………………………… Fall Time = ………………………………

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ChipWise Tutor Workbook P-type width = N-type width Paste the screendump from the output of SVIEW into this frame

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Rise Time = ……………………………… Fall Time = ………………………………

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Module 3: Design and Simulation of Simple Logic Gates
3.4 Device Sizing and Simulation of the NAND gate Minimum Sized Transistors – Waveforms A Rise Time = ……………………………… Fall Time = ………………………………. Minimum Sized Transistors – Waveforms B Rise Time = ……………………………… Fall Time = ………………………………. Explain the above results

The 2-input NAND gate Width of N-type transistors doubled Paste the screendump from the output of SVIEW into this frame

Rise Time = ……………………………… Fall Time = ………………………………

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ChipWise Tutor Workbook 3.5 Design and Simulation of a 2-Input NOR Gate Minimum Sized Devices Paste the screendump from the output of SVIEW into this frame

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Rise Time = ……………………………… Fall Time = ……………………………… Explain Your Results

Sketch the circuit diagram of the 2-input NOR gate in
this frame

What should the widths of the devices be if we wish to have rise and fall times at least as fast as the sized logic inverter? Explain Your Results. Size of N-type devices (in microns) ………… Size of P-type devices (in microns) …………

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Module 4: Design of a 4- bit Shift Register
4.2 Circuit Level Simulation of sreg Paste the screendump from the output of SVIEW into this frame

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ChipWise Tutor Workbook 4.6 Logic Level Simulation of sreg Paste the screendump from the output of SVIEW into this frame

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Module 5: Design of a Parallel Load Shift Register
5.1 Derivation of Circuit Diagram from a Stick Diagram Transistor-level circuit diagram Sketch the transistor- level diagram of the shift register circuit in this frame

Circuit Level Simulation of Shift Register Cell Paste the screendump from the output of SVIEW into this frame

Sketch the logic level diagram of the shift register circuit in this frame

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ChipWise Tutor Workbook

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Explain how the shift register cell operates

5.2 Design of one-bit Shift Register Cell with Parallel Load Symbolic Level Design of Modified Shift Register Cell Paste the screendump of the modified shift register cell into this frame

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ChipWise Tutor Workbook Circuit Simulation of modified Shift Register Cell Paste the screendump from the output of SVIEW into this frame

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Circuit Diagram of Modified Shift Register Cell Sketch the circuit diagram of the modified shift register circuit in this frame

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Describe briefly the operation of your modified cell with reference to the simulation results

5.3 Design of a 4-bit Shift Register with Parallel Load Logic Level Simulation of preg4 – Serial Input Mode Paste the screendump from the output of SVIEW into this frame

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ChipWise Tutor Workbook Logic Level Simulation of preg4 – Parallel Load Mode Paste the screendump from the output of SVIEW into this frame

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Mask Level Design of preg4 Paste the screendump of preg4 into this frame

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ChipWise Tutor Workbook Logic Level Simulation of preg4 with given waveforms

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The following waveforms will cause the register to parallel load ‘0101’ and then to serially shift it out of q3 whilst loading new data through d0:

Paste the screendump from the output of SVIEW for the above input waveforms, into this frame

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Module 6: Design of a 4:1 Multiplexer
6.1 Design of a 4:1 Multiplexer Circuit Level Simulation of 4:1 Multiplexer cell Maximum voltage swing = …………………………………………. Minimum voltage swing = ………………………………………….. Explain the effect

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ChipWise Tutor Workbook Paste the screendump from the output of SVIEW into this frame

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Improving the Output Swing This circuit, added to the output of the Multiplexer, improves the output swing of your Multiplexer Explain how transistor Tp and the inverter improve the output voltage swing of the circuit

An interesting experiment that you can carry out is to monitor the current drawn by the inverter when ‘out’ is high and compare that to the current drawn under the same circumstances but with Tp removed. Explain the difference.

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Paste the screendump of your stick diagram into this frame

6.2 Use of a 4 to 1 Multiplexer as a programmable Logic Element

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20/01/10 The circuit on the left can be used to generate various logic functions of a and b under the control of [c3 … c0]. From the result of the circuit level simulation of this circuit with 0V applied to c3, 5V applied to c2, c1 and c0, identify the logic function produced.

Identify the logic levels which need to be applied to [c3 … c0] to achieve the logic functions shown.

1 2 3 4 5

function a+b a EXOR b a AND b b 1

c3

c2

c1

c0

Sketch the floorplan of a structure , based on the programmable Logic Element, which can be used in an ALU to produce various logic functions of two 16-bit words, showing the flow of Data and Control.

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Module 7: Parity Generator Cell
7.2 A VLSI Implementation of a Parity Generator Cell
The circuit shown below can be used as a Parity Generator Cell:

Paste the screendump of your stick diagram of the Parity Cell
into this frame

Circuit Level Simulation of the Parity Cell Paste the screendump from the output of SVIEW for the circuit level simulation of the Parity Cell, into this frame

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Circuit Level Simulation of Parity Cell with level-restore stage Paste the screendump from the output of SVIEW into this frame

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7.3 An 8-bit Parity Generator Circuit Level Simulation of an 8-bit Parity Generator Paste the screendump from the output of SVIEW into this frame

The circuit level simulation of the one-bit parity cell showed an output logic 1 voltage of approximately 4Volts. What is the output voltage swing of the 8-bit parity generator? Explain the result

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Logic Level Simulation of an 8-bit Parity Generator Paste the screendump from the output of SVIEW into this frame

Comment on any differences between these results and those obtained from circuit level simulation with SPICE.

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