On Inductively Coupled Plasma Etching and HARMST by rzu11221


									       On Inductively Coupled Plasma Etching and HARMST
            J. Bhardwaj, H. Ashraf, J. Hopkins, A. Hynes, I. Johnston, S. McCauley,
                               S.Watcham, S. Hall, G. Nicholls
                      STS Ltd., Imperial Park, Newport, UK. NP1 9UJ.

Inductively Coupled Plasma (ICP) etching of silicon to create HARMST is rapidly growing
within the MEMS market. This paper presents recent advances in etch rate and high aspect ratio
profile control for defining microstructures in silicon using a high density low pressure ICP.

There are a number of different technologies that have been used to create HARMST. All of
these fall into two generic techniques involving either indirect formation of the structure by
molding or other means or by direct etching. The indirect formation methods include LIGA, jet
molding and stereo lithography, whilst the direct etch methods include plasma etching, wet
etching and spark erosion. Selection of the most appropriate technique is based on either its
unique in their ability to achieve the HARMST requirements, or (when there are competing
technologies) when the price/performance ratio is most favourable. For silicon micro-
transducers, plasma etching of HARMST has become widely accepted as it offers a number of
distinct advantages, which include on-chip integration of drive/signal conditions electronics, ease
of wafer size scaling. When price and throughput become the overriding factors and the
precision etching is not so critical, then the other direct etch methods have been commonly used.
The rapid uptake of the plasma etching method can be traced back to the availability of the cyclic
etch/passivation method invented by Laermer and Schilp 1. STS produced the first commercially
available reactor based on the technique in 1994, more widely known as Advanced Silicon Etch
ASE™ process, which for the first time allowed high rates, anisotropic profiles with high
selectivity to conventional photoresist masks. The mechanistic details of the ASE™ process have
been revealed elsewhere 1,2,3. Essentially SF6 is used during an etch step to etch Si isotropically,
this is followed by a short passivation step using C4F8 and the steps are alternately repeated. The
passivation protects the sidewall of the feature from etching, thereby allowing anisotropy to be

Of all of the critical parameters, etch rate (for a given depth, profile, anisotropy etc) is the most
important. This directly influences the uptake of the process with competing direct etch
technologies. For example, increasing etch rate by a factor of 3 to 4 will allow the ASE™ to
compete strongly with wet etching. Another vital parameter is the aspect ratio itself. The higher
the aspect ratio capability, the greater the capability of dry etching compared to the direct and
indirect HARMST formation processes. Hence STS have focused on developing enhancements
to both high aspect ratio and etch rate.

1. Aspect Ratio Enhancement.

The apparatus has already been described elsewhere 2,3. In order to enhance the aspect ratio, an
understanding of the limiting factors is first necessary. In the ASE™ process, at any point during
etching, the ratio of etching to passivation (RE/P) during one step determines the profile.
However, as the aspect ratio (etch depth) increases, there is an accompanying change in the RE/P
due to variations in the passivation step coverage and transport of reactive and product species
into and out off the trench respectively. Clearly changes in RE/P will be gradual rather than
abrupt and can cause profile distortions. Figure 1 shows where the trench beings to close up as
RE/P decreases. To maximise the aspect ratio for any particular application, process parameters
such as cycle times, gas flows, process pressure, coil power and platen power may require
continuous adjustment (or ramping) as the etch proceeds. This will maintain the optimum RE/P.
Figure 2 shows the same trench etched after ramping the pressure during the process and

indicates the decrease in etch rate and selectivity which has been compromised in order to
achieve this. Figure 3 schematically illustrates the variation of RE/P versus etch depth. The
following points are shown, firstly RE/P does not significantly vary for shallow (and low aspect
ratio) etches, creating a very wide process window. Indeed, depending on application, RE/P may
not vary at all during etching such that ramping is not necessary (figure 3, Process A) providing
an appropriate process window has been selected. When very high aspect ratio trenches are
etched, (figure 3, Process B) modification to RE/P becomes necessary. Figure 4 shows SEMs of
both high aspect ratio and smooth sidewall trenches etched with parameter ramping. Note, the
ramping here has been used to reduce the sidewall roughness while maintaining excellent profile
control. More detailed examples of ramping have been presented by Hopkins et al 3. Although
etch rate may be sacrificed in order to enhance the aspect ratio, it is the absolute magnitude of
rate (and hence throughput) which will often determine the suitability of one technology over

2. Etch Rate Enhancement.

The rate limiting factor has been shown to be the concentration of F radical species available to
etch silicon to form volatile SiF4. Figure 5 shows that increasing the ICP source power can
double the etch-rate at higher gas flows and at increased pressure. At <130sccm SF6, the process
is clearly flow gas rate limited. Increasing the ICP source power to increase F radical density, is
also accompanied by increased ion density. However, high ion flux to the wafer surface causes a
reduction in selectivity to mask, and deteriorates the profile control. STS have optimised the ICP
source to overcome such problems and allow high etch rates to be truly realised. Figures 6 and 7
show comparisons between a (a) low etch rate and (b) high etch rate ASE™ processes. Note in
both cases etch rate increase has not been detrimental to parameters such as profile control etc.

It should be noted that etch rate can be a strong function of exposed area of silicon, the higher
the exposed area, the lower the etch rate. Therefore, the etch rate must be specified for a defined
wafer size and exposed silicon area as well as the for the range of feature sizes and for the
required etch depth. Practically, deep etching for realising MEMS devices will require some
method of freeing up defined structure. This may be achieved by using a number of methods
including using SFB wafers, through wafer etching (including using thinned or back-etched
wafers) and etching to either a buried oxide layer or to an underlayer. In all of these cases, etch
uniformity begins to play an important role, as the over-etching now becomes significant. For
example for a 400um deep etch with +5% homogeneity will require a >10% over-etch to ensure
that all features etch to the required depth. Some areas of the wafer will now be subject to a
40um over-etch. Now precise control of the profile during over-etching becomes essential,
particularly when etching to an insulating (e.g. SiO2) interface where severe notching of the
silicon is well known problem 5 . By optimising the STS ASE™ tool, notching at the insulator
interface has now been eliminated. Figure 8 shows an SEM of 30um deep 1.5um wide silicon
lines etched to a buried oxide layer. Note the absence of notching at the interface and the
anisotropic sidewall profile which remains unperturbed.

3. ASE™ Future Trends.

STS has been developing the ASE™ process to provide a near complete MEMS applications tool
set. Successful production worthy solutions have been found for requirements such as etching to
oxide interfaces without notching, maintaining profile anisotropy for HARMST and also for
increasing the etch rate. Future development remains focused on further enhancing the etch rate.
Over and above the current doubling of etch rate that has already been achieved, we predict that
the etch rate will again double within the next 12 months or so, such that there is a factor of 4

increase in rate compared to the first ASE™ tools. This will dramatically change the
price/performance capability of the tool. The net result will be further uptake of ASE™ processes
replacing other direct etch and indirect HARMST formation for some applications. Certainly,
the ASE™ method is set to dominate the HARMST based integrated sensor market.


1. F. Lärmer, A. Schilp; German Patent DE4241045.
2. J.K. Bhardwaj, H. Ashraf; Proc. Micromachining and Microfabrication Process Technology,
   SPIE, Vol. 2639, p. 224, ‘95.
3. J. Hopkins, H. Ashraf, J.K. Bhardwaj, A.M. Hynes, I. Johnston, J.N. Shepherd; Proc. MRS
   Fall Meeting, Boston MA, Dec.‘98.
4. H. Ashraf, J.K. Bhardwaj, J. Hopkins, A.M. Hynes, I. Johnston, J.N. Shepherd; Sensors and
   Actuators, in press, Proc. EMRS, Strasbourg, Jun. ‘98.
5. T. Nozawa, T. Kinoshita, T. Nishizuka, A. Narai, T. Inoue, A. Nakaue; Proc. Dry Process
   Sym., I-8, p.37, Tokyo, Nov. ’94.

                                        ™           Figure 2: SEM of pressure ramped during the
Figure 1: SEM of a fixed pressure ASE Process
showing narrowing of60 um trench with depth,        ASE process, showing enhanced profile control,
2.1um/min and 370:1 to SiO2                         1.8um/min and 340:1 to SiO2

Figure 3. RE/P as a function of etch depth.


                                                                 Figures 6 SEM of trenches etched at >5.5um/min,
                                                                 using low and high coil power respectively.


Figure 4a: SEM of a) 40:1 aspect ratio
trenches etched with ramping, 50um depth, 1.2um
space width with 2um line widths and b) smooth
trenches etched with ramping, 40um depth, 3um

                                                                 Figure 7. SEM of trenches etched at >9um/min,
                                                                 using low and high coil power respectively.
    2            260sccm, 15mT        260sccm, 35mT
    1            130sccm, 15mT        130sccm, 35mT
                 65sccm, 15mT         65sccm, 35mT
        0        1000       2000       3000           4000
                     ICP sourcepower(W)

Figure 5. Etch-rate variation with ICP RF power,
SF6 flow-rate and pressure.

                                                                 Figure 8. SEM of 1.5um polysilicon lines etched
                                                                 30um deep onto oxide. Note the absence of
                                                                 notching at the interface.


To top