What is New in AMSDesigner/AMS-Ultra in IUS6.11 by rrboy

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									           What is New in AMSDesigner/AMS-Ultra in IUS6.11?
               By Ramkumar Madhavan, Lead Support AE, Cadence Design Systems

There are 2 major flows in AMSDesigner. AMSD Virtuoso Flow (Gui Based) and AMSD
Incisive Flow (Command line based). There are many major enhancements being made in
both the flows in IUS6.11 release for AMS Designer.

    1. AMSD 64 bit support:
       Now, the user can run AMSD in 64 bit mode. To enable it,
         - Set the following Environmental Variables
                  1. setenv CDS_AUTO_64BIT INCLUDE:INCA
                  2. Or setenv INCA_64BIT
                  3. Or add -64bit option to ncvlog/ncelab/ncsim

           - Platforms supported
                  1. Solaris 10x86, Solaris 8, 9, and 10
                  2. SUSE Linux Enterprise Server V9.0 and 10 on x86_64
                  3. RHEL 3.0 and 4.0 on x86_64

    2. irun:
       irun is a single step executable (replacement of ncverilog) which can take all
       kinds of languages: .v, va, .vams, .vhd .vhdams, .sv, .sc, .e, etc. With irun,
       running a command line simulation is much easy.
          - Fully backward compatible with ncverilog. Accepts both + & - options
          - Support Verilog, VerilogAMS, VHDL, VHDL-AMS, System Verilog,
               System C, Specman e, C, and C++ source files in the same command line
          - It compiles the files based on the file extension. No need for additional
               options for different file types.

      Examples:
      irun -amsfastspice -mess -propspath prop.cfg -analogcontrol top.scs top.v \
      middle.vams sub.vhd (or)
      irun +ncamsfastspice +ncvlogargs+”-mess” +ncelabargs+”-mess” \
      +ncanalogcontrol+top.scs \ +ncpropspath+prop.cfg top.scs top.v middle.vams \
      sub.vhd
3. AMS Spectre New SFE:
   The New SFE (Simulation Front End) has been defaulted in AMSSpectre. SFE is
   the new parser which has lot of benefits when compared to old spectre parser.
   Benefits:
      - Easier to port designs from Spectre/Ultrasim to AMS
      - Native Spice support
      - Improved capacity and performance in processing analog/spice design

   This is enabled by default. To disable, set the below environment variable.
       setenv AMS_NEW_SFE NO

4. Block-based Discipline Resolution (BDR):
   This feature is especially beneficial for designs with multiple power supplies by
   directly specifying block-based digital/electrical disciplines (with different
   power) before DR (Discipline Resolution) process begins.
   Examples:
      - Specify discipline for a net directly
          ncelab -setd "NET-top.I1.I2.net15- mylogic”
      - Specify discipline for a Cell
          ncelab -setd "CELL-mylib.mycell:myview- myelectrical"

   Note: Here mylogic and myelectrical are the unique disciplines created by the
   user to handle multiple power supply scenarios.

   A tutorial example on this feature is available in installation hierarchy.

   $AMSHOME/tools.lnx86/ amsd/samples/BDR_multpwr
   where $AMSHOME is your IUS6.11 installation directory path.

5. Mixed Signal DC initialization:
   The mixed-signal DC is a process to find out a steady state at analog /digital
   boundary by iterating between analog DC analysis and digital simulation at
   time 0.
      - The default maximum number of mixed-signal DC iterations differs
          depending on which solver you are using:
               AMSS: 100
               AMSU: 2
      - The maximum number of mixed-signal DC iterations can be set by
          setenv AMS_DC_MAX_ITER NumberofIterations
   6. Specman and AMS Designer based verification:
      Now you can incorporate Coverage Driven Verification using Specman with
      AMSDesigner for Mixed signal designs.
        - Autoregression and self checking possible
        - Specman is used for directed and random stimulus generation, functional
           coverage and functionality self-checking
        - Testbench can include both Specman e components as well as AMS
           components

   7. Save-Restart:
      Now available in AMS-Ultra.
               – Can change the model file itself
               – Restart works in command mode only

      A tutorial example on this feature is available in installation hierarchy.

      $AMSHOME/tools.lnx86/ amsd/samples/ams_saverestart
      where $AMSHOME is your IUS6.11 installation directory path.


Enhancements in IC5141 USR5 for AMS in ADE:

   8. Support for using a text design as a top-level design:
      You can now use a text design as a top-level design for AMS simulation. The
      top-level text design can be in Verilog, VerilogA, VerilogAMS, VHDL or
      VHDLAMS format. You cannot use a SPICE-based text design as the top-level
      design.

      A tutorial example on this feature is available in installation hierarchy.

      $CDSHOME/tools.lnx86/dfII/samples/AMS/textOnTop
      where $CDSHOME is your IC5141 USR5 installation directory path.

   9. Ability to save or plot signals from text designs:
      In previous releases, you could not save or plot signals connected to an
      instance in your design if:
         - The instance has a Verilog, VerilogA, VerilogAMS, VHDL, VHDLAMS
             or SPICE-based text view.
         - The instance is bound to a Verilog, VerilogA, VerilogAMS, VHDL,
             VHDLAMS or SPICE-based text file using the sourcefile or verilogfile
             property in Hierarchy Editor.
      From this release, you can use the Hierarchy Editor to save or plot signals from
   Text designs.



10. Envelope following analysis using Spectre:
    From this release AMS in ADE supports envelope following analysis for AMS
    with either the Spectre or UltraSim solvers.

11. Transient noise analysis using AMS:
    From this release, AMS in ADE supports transient noise analysis when Spectre
    is selected as the solver.

                                =====END=====

                      If you have any questions, please contact
                               Ramkumar Madhavan
                              (ramkum@cadence.com)

								
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