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					BaBar EMC Electronics Groups

Trigger System

Trigger prototype Test Plan

BaBar Calorimeter Trigger System Trigger Prototype System Test Plan
Version 1.2

Author: File Name First Modified

S.B.Galagedera. email: s.b.Galagedera@rl.ac.uk J.D. McFall email:j.mcfall@bristol.ac.uk S.B.Galagedera's Macintosh HD:Z:BaBar QA: EMC Trigger 4-Jun-97 Last Modified APPROVALS 29-Oct-97

Title Project Manager Customer Customer

Name S.B.Galagedera P. Dauncey B. Foster

Date

Signature

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29-Oct-97

BaBar EMC Electronics Groups

Trigger System

Trigger prototype Test Plan

This is an initial test plan document for the BaBar EMC Trigger system. This test plan is aimed at describing the scope of the prototype tests before going into production. This document describes the following: 1- Test system overview 2- The Trigger Processor Board functions 3- TPB test modes 4- Summary of tests 1 Test system overview The TPB prototype(s) can be tested in the following phases: 1A 1B: Prototype standalone tests (with RAL2301, TRB and IOC) Prototype in system tests (with a ROM prototype and Fast Control modules)

The above phases are in addition to the system tests which are planned in SLAC in 1998. The SLAC system tests will involve the global trigger and all system components to verify the system with the final (or near final) modules and software. 1A Prototype standalone tests configuration This consists of the following hardware: 1A.1 1A.2 1A.3 1A.4 1A.5 1A.6 Standard Calorimeter DAQ VME Crate (9U with 6U carrier shelf in slots 1 to 5, J1 with A24:D16 VME). Two TPB modules (9U, single width). One TCB (TRB Carrier Board, 9U, double width) with no EMB to begin with. One IOC (Motorola MVME167, 6U, single width) which accesses the VME crate on J1. Full J1 Backplane plus the custom Trigger Backplane J2/J3 (with or without a hybrid FC J3 on the first 5 slots) RAL2301 (6U, double width)

Module positions in prototype standalone tests
1 2 3 4 5 6 R A L 2 3 0 1 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

I O C

FC J3

T P B 0

T P B 9

T P B 1

T P B 8

T T P C B B 2

T P B 7

T P B 3

T P B 6

T P B 4

T P B 5

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BaBar EMC Electronics Groups

Trigger System

Trigger prototype Test Plan

1B Prototype system tests configuration The configuration for system tests will be with the following: 1B.1 Standard Calorimeter DAQ VME Crate (9U with 6U carrier shelf removed, J1 with A24:D16 VME). 1B.2 Two TPB module (9U, single width). 1B.3 One TCB (TRB Carrier Board, 9U, double width) with no EMB to begin with. 1B.4 One IOC (Motorola MVME167, 6U, double width) which accesses the VME crate on J1. 1B.5 Standard full J1 Backplane and the Trigger Backplane J2/J3 (with a hybrid FC J3 on the first 5 slots) 1B.6 One FCDM (9U, single width) 1B.7 One FCPM (9U, single width) 1B.8 One TPC + ROM (9U, single width) 1B.9 One ROM with UPC (9U,single width) 1B.10 Trigger patch panel and cables (prototype or final)

Module positions in prototype system tests
1 C D M C P M T V P T C + R R O O M M P B 0 P B 9 P B 1 P B 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

U P C

F C D M

F C P M

T P B 0

T P B 9

T P B 1

T P B 8

T T P C B B 2

T P B 7

T P B 3

T P B 6

T P B 4

T P B 5

2 The Trigger Processor Board functions The block diagram in the PDR documentation on WWW shows the main functions of the TPB including the data sizes and the rates, and should be referred to in conjunction with this document. The main functions of the TPB can be grouped as follows: 1- Input stage from UPC ROMs (on J2 through the patch panel) 2- The Fast Control Interface 3- The VME interface 4- The Spy and playback FIFOs

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BaBar EMC Electronics Groups 5- The Formatter Xilinx 6- The Trigger Algorithm Xilinx 7- The Global Trigger outputs (on J3) 8- The Event and Latency Buffers

Trigger System

Trigger prototype Test Plan

With most of the above there are control circuitries which should be viewed as part of the main function, however, these may share some resources on the TPB. 3 TPB test modes The TPB has 2 modes of operation for tests: internal and external. 3A Internal tests The TPB will rely on the RAL2301 and the software to generate the Fast Control commands and the Trigger Configuration Data. It will also depend on the TCB to distribute the clock and returned data streams to and from each TPB on the trigger Backplane. The IOC will be involved in all the setup and diagnosis. The internal tests are the first tests to be carried out on the prototype TPB in the standalone test configuration as described above in 1A. The TPB is capable of generating its own inputs from its internal memories at any frequency up to 60 MHz and recording the results of intermediate stages and the outputs of the Algorithm Xilinx in internal memories for analysis by the IOC. The pattern RAMs can be loaded and the “start playback” sequence can be started by the C-Link. The neighbour information can not be created in this way unless a second TPB is present on the Backplane. It is also important to fully check the custom J2/J3 prototype Backplane connections as early as possible. This could be done by making 2 TPBs and arranging them in nearest neighbour slots to check all the connections are good. The fast control signals to all the TPB slots could also be checked at the same time. 3A.1 Input stage Inputs are generated by the IOC and loaded into the RAL2301 memories through VME. The RAL2301 will be used by the IOC to load the pattern RAMs through the C-link and also to send the „start playback‟ command to the TPB through the C-link to initiate single-shot or continuous playback. To check the integrity of the input stage the Algorithm Xilinx may be configured as a simple pipeline. Incoming signals may then be passed to the D-link. The alternative is to put a test clip onto the Algorithm Xilinx inputs to observe the signals. Limited tests will be carried out on the UPC inputs (J2) using pulse generators and standard test equipment such as logic analysers. 3A.2 The Fast Control Interface The Fast Control system will be configured and exercised by sending system and triggerspecific commands from the RAL2301 via the C-link.

3A.3 The VME interface

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Trigger System

Trigger prototype Test Plan

Tests will check that the VME can select and read the SPY memories, and that TPB0 initiates SPY signals to all TPBs at the same time. 3A.4 The Spy and playback FIFOs The playback memories will be loaded from the C-link to test the Algorithm Xilinx as described above. Single shot and continuous playback modes will be tested. The record function of the SPY FIFOs will be tested by reading from VME. The SPY modes at „stop on L1 Accept‟ etc must be tested. 3A.5 The Formatter Xilinx Tests will be carried out with the C-link commands L1 Accept, Read Event, Clear Readout, as well as Write Memory and Read Memory to verify the DAQ Mask table. Test data will be input via the playback memories and passed through the Algorithm Xilinx (configured as a simple pipeline) to the Formatter Xilinx, and the output then read over the D-link. 3A.6 The Algorithm Xilinx The Algorithm Xilinx is booted on power up. A signal from the push button switch can also boot up this Xilinx from the on-board serial PROM. Alternatively an X-Checker cable may be used. The configuration constants must then be loaded from the C-Link. Two kinds of input test vectors will be generated on the IOC: one specifically for electronic integrity tests and the other for physics-oriented algorithm efficiency tests. They will be downloaded via the C-link into the playback memories and the Algorithm Xilinx outputs will be read out (beyond the Formatter Xilinx) via the D-link. Configuration data will also be downloaded via the C-link and read back via the D-link. It is difficult to isolate the Algorithm Xilinx from the Formatter Xilinx, and so the correct operation of the Formatter Xilinx must first be verified (see above). 3A.7 The Global Trigger Outputs Data will be loaded into the BEPB memories via the C-link and output via the GT outputs. These data will be validated using a logic analyser. 3A.8 The Event and Latency Buffers Latency buffer tests will load latency values via the C-link and start the latency buffer running. A logic analyser will be used to monitor the read and write controls on the latency buffer. Event buffer tests will verify correct operation for: Clear Readout (reset lines), L1 Accept (write lines) and Read Event (read lines).

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BaBar EMC Electronics Groups 3B System tests

Trigger System

Trigger prototype Test Plan

In addition to internal tests the TPB will be tested with external sources to verify the integrity of the connections and the interface circuits in the system test configuration as described in 1B above. The main difference here is that the ROM UPC will be the input source and the signals will be sent down a cable. The Fast Control commands can either be generated by the actual Fast Control modules or RAL2301 depending on the availability of the FC modules for the prototypes. These inputs can be monitored on board. The outputs from the TPB to the Global Trigger can only be monitored using a logic analyser. All the above functional tests (in 3A) will apply for system tests. 4 Test programme summary            Configure Fast Control Xilinx via C-link and read back via D-link Exercise Fast Control interface using IOC/R2301, sending commands via C-link Write to BEPB buffers via C-link and read back via D-link Output data from BEPB buffers to J3 interface, and check using logic analyser Configure and exercise Latency Control and Event Buffer Control Xilinxes via C-link and Fast Control Configure and exercise SPY and Playback Control Xilinx via C-link and VME (via J1) Write to FEPB buffers via C-link and read back under VME Configure Algorithm Xilinx via C-link Load test data into FEPB. Configure Algorithm Xilinx as a simple pipeline, and read Formatter Xilinx output via D-link, hence also testing Latency and Event Buffers. Load test vectors into FEPB buffer and send to Algorithm Xilinx. Read output from Formatter Xilinx via D-link and outputs to SPY under VME. Verify J2 interface using pulse generator and logic analyser

…and repeat for system tests using cable inputs.

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Lingjuan Ma Lingjuan Ma
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