Research In Wireless Communication Circuits

Document Sample
Research In Wireless Communication Circuits Powered By Docstoc
					      60 GHz Radio

    Professor Ali M. Niknejad
Berkeley Wireless Research Center
University of California, Berkeley
                Major Challenges for
                Communication ICs
    Analog                                             WiFi WLAN
     Voice               Cordless                      802.11 a/b
    (AMPS)               Phones
                     • Low Power RF
                                         UWB
    Digital              Cable        • Wideband LNA
     Voice              Modems        • Antenna
    (GSM)
                     • Wideband VCO           PicoRadio
                     • Wideband LNA
   Voice/Data        • Linear Mixer     • Low Power Amplifier
       3G                               • Novel MEMS-based      60 GHz
                         Optical                                 Radio
• Low Power RF            Data
• Full Integration                                        • CMOS Modeling
                         Comm
• MEMS-based                                              • Design Methodology
• Linear PA          • 40 GHz VCO                         • RF Circuit Blocks
• Sub 100 nm CMOS
Cell Phone External Component
            Count   Diode/Switch
                             RX
         DCS/PCS                        BPF: PCS

                                        BPF: DCS
         Diplexer
                             RX         BPF: GSM
          GSM
                    TX

                                        LPF: PCS/DCS   Isolator   Coupler

                    Diode/Switch   TX   LPF: GSM       Isolator   Coupler

• Current trends in academia and industry have reduced
  component count at RF and IF
• The Low-IF, Direct-Conversion, and Wideband IF radio
  architectures eliminate (reduce) external IF filters
• Systems still heavily dependent on external components on the
  front end: SAW filters, switches, directional couplers, matching
  networks, pin diode, diplexers …
• Many of these components are expensive (high Q) and
  narrowband
 Solution: MEMS Universal Radio
• High dynamic range
  broadband front end and high
  speed ADC
• Eliminate high-Q front-end           MEMS
                                       MEMs resonators / filters
  filtering, employ integrated
  MEMS filtering instead                                           ADC



• Design parallel or broadband
  amplifiers to cover major



                                 PLL
                                 PLL
                                 PLL
                                 PLL
                                        VCO

  bands around 1 GHz, 2 GHz, 5
  GHz, etc.                             Tank
• Require dynamic operation to
  reduce power
• Employ broadband matching,
  filtering, and amplification
• (e.g. 500 MHz – 3 GHz)
            CMOS 60 GHz Radio
 • Objective:
    – Enable low cost, low power, mobile, agile, mm-wave communications
      (Gb/s wireless ethernet)

 • Approach:
    – Employ standard CMOS and SiGe technology for the radio building
      blocks (inexpensive)
    – Exploit antenna array for improved gain, resilience, or throughput
      (robust)

 • Major Challenges:
    – CMOS and SiGe device models not available
    – Silicon substrate is lossy – high quality passive elements difficult to
      realize
DARPA
60 GHz Research Team
 Gary Baldwin, Bob Brodersen, Ali Niknejad

 CMOS:
 • Chinh Doan            LNA/PA, T-Lines
 • Brian Limketkai       VCO, Phase Noise
 • Sohrab Emami          Actives, Mixer
 • Hanching Fuh          PA
 • Eddie Ng              Freq. Dividers

 • Sayf Alalusi          Antenna Array/FE Filters

 SiGe:
 • Eddie Ng              LNA, Freq Dividers
 • Mounir Bohsali        Mixers
 • Patrick McElwee       PA
60 GHz Radio Frequency Planning




 • LO = 55 GHz, IF = 5 GHz  Requires LNA, Mixer, LO, Divider at 60 GHz
 • LO1 = 30 GHz, LO2 = 25 GHz  Easier Implementation, Higher Power?
 • LO×N = 60 GHz also an option
60 GHz Antenna Array Receiver
                Filter   IF Amp   A/D              A/D   IF Amp   Filter




                                        DSP CORE
          VCO                                                              VCO


                Filter   IF Amp   A/D              A/D   IF Amp   Filter

          VCO                                                              VCO


                Filter   IF Amp   A/D              A/D   IF Amp   Filter

          VCO                                                              VCO




 • Antenna elements are small enough to allow direct
   integration into package or substrate
 • Spatial diversity offers resilience to multi-path fading
 • Beam forming can improve antenna gain
 • Channel capacity increased  more bits/Hz
Active Antenna Array Transmitter
                IF Amp   D/A              D/A   IF Amp




                               DSP CORE
          VCO                                            VCO


                IF Amp   D/A              D/A   IF Amp

          VCO                                            VCO


                IF Amp   D/A              D/A   IF Amp

          VCO                                            VCO




• Power control easier
• Each PA is relatively low power (10-50 mW)
• Input to each PA can be phased correctly to
  achieve beam forming for improved gain
                 60 GHz Test Chips
                                       •   July 2002 SiGe
                                            –   30 GHz to 5 GHz Mixer
•   December 2001 CMOS                      –   55 GHz Oscillator
     – SOLT De-embedding
                                            –   28 GHz LNA
     – NMOS transistors
                                            –   60 GHz 50Ω Output Buffer
     – 0.15μm/0.13μm to
       5.0μm/5.0μm                          –   Flip-flop divider, Injection-Locked Divider
     – Long high-speed multi-finger         –   Caps, Inds, BJTs, T-lines
       NMOS devices
     – Diodes                          •   September 2002 CMOS
     – Inductors                            –   TRL de-embedding
                                            –   Transformers, Inductors
•   February 2002 CMOS                      –   Power transistors
     – SOLT De-embedding                    –   Finger capacitors
     – High-speed PMOS devices              –   Optimized NMOS transistors
     – DC measurement structures for        –   Coplanar and Microstrip Lines
       NMOS/PMOS
     – Coplanar transmission lines     •   December 2002 CMOS
     – T-line impedance matching            –   Coplanar and Microstrip Lines
       networks
                                            –   Bypass and coupling caps
     – Low-noise amplifier
                                            –   Distributed Filter
     – Oscillator
                                            –   Amplifiers
                                            –   Oscillators
Characterization Lab Upgrades
                             Sohrab Emami
Agilent 4284 LCR
Meter




                                       Anritsu 37397 VNA



                                                                            LAN



                                                                 HP-IB




                                                                         E5810A Gateway
   DUT/Probe Station
   Cascade Microtech's
   Summit 12000
                         16494A
                         Triax Cable
                                       Agilent 4142 Modular DC
                                       Source/Monitor
Extracted vs. Simulated fmax and fT
                          Sohrab Emami




@ Vds=1v    measured fmax : 57GHz    measured fT: 93.6GHz
 Vgs=0.9v   simulated fmax : 73GHz   simulated fT : 81.7GHz
60 GHz Design Methodology
               Chinh Doan




Calibrate and verify simpler models using most
accurate data available
      Distributed Filter Simulation
                        Chinh Doan




• ADS Simulation Assuming
  interconnection of T-lines
• HFSS Simulation full-wave EM
  using finite elements
• ADS Simulation very close to
  HFSS simulation despite
  simplicity!
        28 GHz Low Noise Amplifier
                             Sohrab Emami
              Vcc




                                 +
                                 vo
               Vb                —




   +
   vi               ±
   —




Simulation:
                        S11= -30dB    S22= -20dB
Icore=6 mA
VCC = 3 V               S21= 15.1dB   NF= 3.2dB
                  30 GHz to 5 GHz Mixer
                                   Mounir Bohsali

                                          50Ω at 5 GHz




                  AE = 19.2 x 0.2 μm2


        Conversion Gain        11.44 dB
        Noise Figure           16.8 dB
        Total Power            30 mW
        Buffer / Mixer         9 / 21
        Simulated Performance
• Traditional microwave mixers are passive and
  lossy (but linear)
• In this research project we would like to find
  the upper frequency limits for an active mixer
  Colpitts 55 GHz Oscillator
             Tank
                                                               Simulation:
                                  Bias                         Icore= 8 mA
                                                               VCC = 1.2 V
Colpitts
Oscillator                                  Bypass
                                                               Vosc= 2 V p-p
                     Chokes

                                                                    Chokes

                                                                             Load
                    Cap Divider
                                              On-Chip T-Line

                                               Buffer



      • Custom tank using ―ring‖ inductor
      • High-Q MIM caps (need high-Q varactors)
      • Differential operation makes substrate common mode
      • Chokes act like low-loss current sources
             Oscillator Layout
                            Low Loss MIM Cap and Inductor Ring
                               Tightly Coupled for Low Loss




                             Tank MIM       Low-Loss Custom
   Single-Ended 50  Load                     Cap Divider
                                  150 pH Loop
600 pH Inductor “Chokes”          Q>30 (HFSS)
                             30GHz SiGe Dividers
     FF-Based:
                                  Eddie Ng
                       Vcc

                               QB
                         Q
D               DB                          D    Q   D   Q


                                            DB QB    DB QB
                               CLK,
    CLK          CLKB          CLKB



                                      Vcc
    Injection-locked:                 Vcontrol
                 Out-                                        Out+




                 Vin
         40GHz and 60GHz CMOS
        Injection-Locked Dividers
                                       40 GHz divider   60 GHz divider
        Vdd
                      Vdd              1.3V             1.3V
Out-           Out+
                      Idd              5.7mA            8.5mA


                      Inductance, Q    150pH, ~10       80pH, ~10


                      Lock range       10%              3.3%
                                       (38G-42GHz)      (59G-61GHz)


  Vin                 Phase Noise at   -40dBc/Hz        -30dBc/Hz
                      10kHz offset—
                      unlocked
                      Phase Noise at   -100dBc/Hz       -85dBc/Hz
                      10kHz offset—
                      locked
60 GHz CMOS Oscillators
     Brian Limketkai
               • 0.13 standard
                 CMOS process
               • Use coplanar
                 waveguide inductors
                 and capacitors
               • Calibration structures
                 on same chip
               • ―Low Frequency‖
                 oscillators to test
                 phase-noise theory
  High Frequency Power Amplifiers
           Hanching Fuh
                                       L3
                      RFC



                                      C3    L1         C1         Rload



• Objectives
   –   Class-F CMOS PA with fully integrated passives       30
                                                                                Gain
   –   0.13 m ST Microelectronic CMOS process              25                  Efficiency

   –   fo = 20 GHz                                          20
                                                                                PAE


   –   Maximize efficiency for given power gain             15

• Simulated Performance                                     10

   –   Power gain up to 25 (14dB)
   –
                                                            5
       Efficiency up to 25%
   –   Power Added Efficiency (PAE) up to 15%               0
                                                                 0.0      0.1   0.2          0.3   0.4   0.5


   –   Simulated with finite Q modeled, ST non-quasistatic                             Vin



       transistor models with gate resistance, and input/output
       matching
             PA Layout Issues
• ―Manhattan‖                 • Tree
   – Most area-efficient         – Delay Equalized
     layout                      – Adaptable to a
   – Not delay equalized to        distributed Power Amp
     gates and drains of           structure
     individual transistors      – Area inefficient
                                 – Large capacitive and
                                   resistive parasitics
                 Wideband LC VCOs
                     Axel Berny
                    VCO Core Schematic and Layout

• All PMOS to reduce 1/f noise
• Only two gain devices for
  less capacitive loading
• LC noise filter to attenuate
  bias noise
• Compatible with modern
  submicron technologies
  where Vdd ~ 1.0V
                                                Area = 1.0x0.8 mm2
                                               (including o/p buffer)
            Wideband Tuning VCOs
                 Axel Berny
                                                                                  to VCO

                                          8x        4x        2x        1x
Frequency Tuning Scheme
•   Divide wide frequency range into           8x        4x        2x        1x

    small sub-bands where tuning char.
    is ~ linear & KVCO is low
•   Non-linear cap of inversion-mode
    varactor is only a small % of total
    tank capacitance
•   Trade-off between achievable               Tuning Range: 1.2-2.2 GHz
    tuning range and output amplitude
    (phase noise). For higher tuning
    range: lower L ( Vo ) and increase
    N (QT  & Vo ).
•   Achievable tuning range is only
    limited by parasitic capacitance,
    NOT by Vdd
          BSIM CMOS Modeling
• Next Generation: BSIM5
• Charge-based charge-sheet bulk referenced model under
  development
• New model will incorporate all existing BSIM4 advanced
  short-channel/process effects
• Advantages:
   –   Inherent source/drain symmetry
   –   Potential reduction in parameter set
   –   I-V and C-V consistency
   –   Flexibility
• Improved Noise and Distortion Modeling
• Scalable Substrate Resistance Network
MOSFET RF Parasitics
     Chinh Doan




                      gm
              ft 
                     2 C gg
                                          ft
            fmax 
                     2 R g (gmC gd C gg )  (R g  rch  R s ) gds
Substrate Resistance Extraction
• Substrate limits high frequency                  b
                                                           Contact
                                                                 d
  gain of amplifiers                           a
                                                       L
                                                                     W
• Resistance adds excess thermal
                                                                      W




                                     Contact




                                                                      Contact
  noise to circuit
• Coupling causes unwanted
  feedback and digital noise                           Contact

  leakage into sensitive analog
  circuitry
• Goals of Research Project:
   – Develop scaling equations for
     substrate network
   – Identify network with minimum
     number of parameters
      Role of Substrate Contacts
• Parallel current path resistance                                        Contact
  scales inversely with width                                                               1
• Perpendicular current path scales                                                 R|| 
                                                         R  W
                                                                                            W




                                                                                                Contact
  linearly with width                                                1
                                                                R
• In general, both paths contribute                                  W

  to the resistance
• Capture this effect by introducing                                     Contact

  two scalable resistors:
                                                 XW||         XNF||
         R||  R ( L  XL)          (W  XW )
                 '           XL||
                ||                                       NF
         R  R ( L  XL) XL (W  XW )  XW NF  XNF
               '


         R  R|| || R
• Now we have 40 substrate parameters!
• Can we simplify the number of parameters?
                    Summary

• We hope to demonstrate a small footprint, low cost,
  low power, agile, robust, mass producible 60 GHz
  radio designed in standard CMOS/SiGe.
• Current simulation tools, design methodologies, and
  transistors models are not ready. We hope to remedy
  the situation.
• Our approach is to simultaneously work with device
  models, circuit building blocks, and system design in
  order to deliver an optimal solution.