Phase-Locked Loop Based Frequency Synthesizer for Wireless by broverya76

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									 Phase-Locked Loop Based
   Frequency Synthesizer
for Wireless Communication


           Yiwu Tang
    Information Electronics Group
           March 9, 2000
                 Outline

• PLL frequency synthesizer fundamentals
• A design example – a 433MHz ISM frequency
  synthesizer
• Work going on and future work
       PLL Fundamentals (I)
             Basic Architecture

~        Phase
                                 Low Pass
       Frequency                            VCO
                                  Filter
        Detector
Fref
                                                  RF Output Fo


                      Programmable
                   Frequency Divider /N
   PLL Fundamentals (II)
       Key blocks in a PLL
• Phase frequency detector
• Charge pump and loop filter
• Voltage controlled oscillator (VCO)
• Frequency divider
  – Prescaler
  – Program counter
  – swallow counter
      PLL Fundamentals (III)
           Major Design Issues
• Performance specification
  – Dynamic performance: lock range, lock time…
  – Noise performance: phase noise, time jitter…
• Design considerations
  – Performance of each building block
  – Simulation at different levels for entire loop
• Implementation in CMOS
       Design Example (I) Overall Architecture
             A 433MHz CMOS Frequency Synthesizer
                                                                                                    433, 432.974,
                                                                                                    433.026 MHz

                                                           Up
5.16MHz         Frequency            Frequency/                         Charge           Loop
Reference                           Phase Detector                      Pump                       VCO
               Divider /200                                                              Filter
Generation
                                                          Down




                                     Program Counter                         Prescalar
                                          /2400                                /7, /8




                                                       Swallow Counter /3,
                                                             /4, /5

                On-chip
               Components                                            LO frequency
                                                                      Selection


 • Frequencies generated: 433MHz, 433MHz±26kHz
 • Reference frequency: 26kHz
 • Frequency divide ratio: 16803, 16804, 16805
 • Prescaler: 7, 8            Program counter: 2400                            Swallow counter: 3, 4, 5
       Design Example (II) Phase Frequency Detector


        Vcc       SET
                             Up
              D         Q
Fref

                  CLR
                        Q




        Vcc       SET
                            DOWN
              D         Q
Fdiv

                  CLR
                        Q
      Design Example (III)
   Charge Pump and Loop Filter
                                    Wide swing
                                   current source
                                  (PMOS, charge)

                                         /Up

                           Up




                          Down

                                       /Down


                                               2nd order
                                               loop filter

                                    Wide swing
Bias circuit                       current source
                                 (NMOS, discharge)
               Design Example (III)
            Charge Pump and Loop Filter
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        0        0.5       1        1.5           2
                        Time (s )                -5
                                          x 10
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                        Time (s )                -5
                                          x 10
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                        Time (s )                -5
                                          x 10
             Design Example (IV)
                                         Prescaler
                                                   Vdd


                                                                    M3                     M4
                                                                                                                    Q
             D
                 SET
                       Q   D
                               SET
                                     Q                        20u/0.5u                     20u/0.5u

                                                                          A
                 CLR
                       Q       CLR
                                     Q                                                     B
Fin                                                                3u/0.5u
                                                                                  M7
                                                                                                                    /Q
                                          Fout                     M5
                                                                                            M6
                                                  CK     1.5u/0.5u
                 SET
                                                                                           1.5u/0.5u
             D         Q                                  Vdd                                     Vdd

                 CLR
                       Q                         1.5u/0.5u                    C            D            1.5u/0.5u
      Mode
                                                                                                   I2
                                                   IN
                                                              I1                                           IN
                                                                         M1               M2
                                                 0.75u/0.5u                                        0.75u/0.5u
                                                                         10u/0.5u      10u/0.5u
                                                  Vss
            Design Example (IV)
                         Prescaler
    3

)   2
V
(
e
d   1
o
M
    0
        0     0.2        0.4      0.6      0.8        1      1.2
                               Time (s )                         -7
                                                          x 10
    3

)   2
V
(
n
i   1
F

    0
        0     0.2        0.4      0.6      0.8        1      1.2
                               Time (s )                         -7
                                                          x 10
    3

)   2
V
(                   /8
t                                                /7
u   1
o
F
    0
        0     0.2        0.4      0.6      0.8        1      1.2
                               Time (s )                         -7
                                                          x 10
           Overall Performance by Simulation

Process                                 0.5µm CMOS
Die size                                0.6mm by 0.6mm
Operation voltage                       3.3V
Operation frequency                     433MHz
Reference frequency                     25.8kHz
Power consumption                       19.5mW
Charge pump current                     450µA
Lock time for a 2.6MHz frequency step   1.1ms
         Work Going On (I)
• Simulating at system level with
  – Matlab
  – SPICE macro models
  – HP ADS
• Developing novel architectures for
  improved performance
                          Work Going On (II)
System Level Simulation with Matlab & Spectre Macro-Model
               4 40


               4 39


               4 38


               4 37


               4 36
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           y   4 35
           c
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           e
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           q
           e
           r   4 34
           F

               4 33


               4 32


               4 31


               4 30
                      0     0.5   1               1.5   2      2.5
                                      Time (s )                    -3
                                                            x 10
                                    Work Going On (III)
Improving loop architectures for better performance
                                     Phase                          Charge Pump
      ~                                                                  &              VCO
                                   Frequency
                                    Detector                         Loop Filter
     Fref=Fdb


                                                            Fc=Fo/N
                                                            =channel spacing

                                     Multiple Frequency
                                          Doublers                       /N Frequency
                Fdb   =2mF   o/N                                            Divider



                                      Phase                           Charge Pump
          ~                                                                &             VCO
                                    Frequency
    Fref1= Fref2+Fc                  Detector                          Loop Filter
                                                                                               Fo




                               Fref2+Fc               Fc              /N Frequency
                                               ×                         Divider



                                               ~    Fref2
               Future Work

• Measure the 433MHz F.S. chip
• Obtain more results on system performance in
  different architectures with system simulation
• Design and implement a dual-mode frequency
  synthesizer for GSM and WCDMA

								
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