FAST FOURIER TRANSFORM COMPONENTS

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					FAST FOURIER TRANSFORM COMPONENTS

Team Leader: Mike Palladino Members: Travis Boucher, Chuck DeLoid

VLSI Professor Rucinski January 11, 2010

Table of Contents

1. Introduction .................................................................... 1 2. Overview ........................................................................ 1 3. Implementation ............................................................... 2 4. Complex Multiplication ................................................. 3 5. Schematics ..................................................................... 4 6. Simulations .................................................................... 5 7. Layouts .......................................................................... 8 8. Conclusion………………………………………........12 9. References……………………………………………13

Introduction:

The purpose of this project is to develop a library of components for a 16-point, radix 4 Fast Fourier Transform (FFT) algorithm. This is a continuation of the pattern recognition application developed by the FPR Corporation initiated a few years ago. The recognition task involves pattern collection preprocessing and matching. These tasks are computationally complex and often it is necessary to perform them quickly with speed being critical in real time applications. This project focuses on an Application Specific Integrated Circuit (ASIC) which is a much more efficient way to use silicon area, but the design takes longer and generally more expensive than a Field Programmable Gate Array (FPGA) chip. ASIC’s are often used for high volume application, resulting in the nonrecurring engineering costs to dissipate over a large production volume.

Overview:

This project is designed to create an ASIC version of a fingerprint authenticator, which requires a number of complex operations involving frequency spectrum domain filtering. The chip designed was to implement complex multiplication iterations using a 4X4 signed multiplier. The frequency domain filtering is the most efficient way of filtering digital signals. Since the fingerprint authenticator consists of binary inputs and outputs, all operations will be done in the frequency domain. A convolution operation in time domain corresponds to multiplication in the frequency domain. The chip plays the role of the frequency multiplier for the FFT. In order to ensure that this approach results in performance gain compared to filtering the digital signals of time domain, an efficient FFT algorithm needs to be used, such as the one in the scope of this project. Having 3 members as opposed to two, the group was assigned more tasks than the other groups. In addition to the complex multiplier, the group constructed a chip that contained the individual components of the multiplier. The chip was composed of an unconnected 2 bit adder, 2 bit subtractor, 2 bit multiplier, and a 4-bit clock synchronizer.

Implementation:

The team was assigned to design two chips. The first and most complex was a complex multiplier. The second was an arithmetic chip which could be used as an adder, subtractor, FIFO, or a multiplier. There are two possible methods of design entry: schematics, and VHDL description. There are also two possible ways to implement the design: in either an FPGA, or an ASIC. The team decided to use a schematic approach for the design entry using Mentor Graphics as our design tool. For the implementation technology we have chosen the AMI 0.5 ASIC process. Mentor Graphics was used to construct a library of components that could be used as the group progressed further into the design process. This hierarchical approach enabled the complex multiplication process using only an: adder, subtractor, and multiplier. Using this type of approach, with more time, the complex multiplier could be used to create a 4-point FFT. Below is a picture of the implementation flow that was used.

Above is a design flow chart for the two chips. It is easily seen that as design process continued the design was rigorously tested for errors. Once the errors were found,

they were fixed and the design process was then able to continue. This was the only way to ensure a correct design in the end that will be a usable chip.

Complex Multiplication:
(A + Bi) * (C + Di) = AC + ADi + BCi – BD = (AC – BD) + (AD + BC)i The overall complex multiplier consists of three signed components; an adder, a subtractor, and a multiplier. The output of the multiplier will yield a real and an imaginary part.

Figure 1: Block Diagram of the Complex Multiplier

Schematics:

The software used throughout the entire project was mentor graphics. There were three signed components that needed to be built in the design architect; the adder, subtractor, and multiplier. When constructing the 16 bit adder, 8 two bit adders were cascaded that were available in the Design Architect library. The resulting output was 16 bits plus a sign bit. Similar to the adder, the subtractor was comprised of eight two bit adders. The difference between the two was the inverted inputs and the carry in was connected to Vdd to signify a carry in of one. The multiplier shown below was constructed using 2 bit full adders and basic logic gates.

Figure 2: Schematic of 8 Bit Multiplier

The twelve blocks are actually two bit adders with a carry in and out bit. Once this schematic was designed, tested, it then got put into a symbol or block and then used on our next circuit which was our actual project, the complex multiplier.

After completing the design phase of the components, they were combined to form the complex multiplier. A FIFO was needed to ensure the data could be clocked and moved throughout the chip. Using 8 D – latches, the FIFO was built and added into the final schematic to complete the design of the complex multiplier. The figure below shows the complete schematic for the project.

Figure 3: Complete Schematic of Complex Multiplier

Simulations:
As the design progressed further into the project, it was necessary to simulate and check to verify its functionality. To do this we first designed our 2-bit adder, tested it, and then from that we were able to make our multiplier and test that. We did this throughout our project and now we are 100% confident that our design is correct. Below is an example simulation that shows the signed addition of 4 + (-1). The outputs are constant values and the correct output of 3 was achieved.

Figure 4: Signed Addition 4 + (-1) = 3

In the figure below, there are four waveforms. These four are inputs to the complex multiplier. Each waveform represents four actual waveforms for each 4 bit number; this was done for ease of presentation. The following two simulations show the imaginary output the real output, respectively. The top waveform is the clock for the circuit. On the rising edge of the clock the inputs are injected into the circuit and on the falling edge the outputs are then present. For the first clock all 1’s are injected into our logic. All 1’s represents a -1 in decimal. Multiplying (-1)*(-1)=1. Therefore keeping in mind that we are doing complex multiplication we should expect all zeros for both sets and our outputs.

Figure 5: 4 inputs to the Complex Multiplier

Figure 6: Real outputs of the Complex Multiplier

Figure 7: Imaginary Outputs of Complex Multiplier

Layouts:

The layouts of the complex multiplier and the general arithmetic chip were implemented in IC station using the Schematic Driven Layout (SDL) viewpoint option. A critical advantage of creating schematics from the netlist translation was the option of auto floor planning in IC station. By using auto floor plan the cells were automatically placed and routed. Any lines that were not automatically routed were classified as overflows, and were highlighted yellow lines indicating the route from point A to point B. These overflows were then routed manually to complete the routing procedure. After completion of routing, a Design Rule Check (DRC) must be performed to ensure that spacing errors as well as design requirements were met. For example, spacing between metals of the same kind (i.e. Metal2) must be a minimum of 3 Lambda apart. If the Metal2 spacing did not meet that requirement, the DRC would detect the rule violation, specifying that the distant needs to be increased to a minimum of “3L.” After fixing all DRC errors, a Layout Versus Schematic (LVS) check must be completed. The basic function of an LVS is to verify the layout design in IC, and the logic of the schematic. Common LVS errors can include short circuits, or incorrect connections,

which must be fixed in order to pass the LVS check. The picture below shows one of two IC layouts, the complex multiplier.

Figure 8: IC layout of Complex Multiplier After completion of the IC layout, a pad frame was generated in Design Architect. A symbol is created from the final schematic of the complex multiplier with pins connecting to the pad frame. The pad frame schematic is shown below.

Figure 9: Pad Frame at Logic Level

The logic is then implemented in IC layout using the same process to complete the original IC Layout. When making the pad frame at the logic level there are certain requirements you must have to generate the pad frame in IC station. The logic block in the middle of the above picture is a block of the complex multiplier. To implement the block as a pad frame, it must have an existing layout in IC station. The IC layout must be the same name as the logic block in Design Architect, this way IC station can reference the proper IC layout when generating the pad frame. For example, the logic block was named “final” as well as the IC layout for the block was named “final.”

Below shows a picture of the pad frame with the chip in the middle. This view shows the entire hierarchy. The complex multiplier logic is centered in the middle, and is wired to the outer pad frame.

Figure 10: Pad Frame Layout of Complex Multiplier Hierarchy View

The general arithmetic chip was implemented and generated the same way using Design Architect and IC station. The following picture shows the pad frame layout similar to the layout of the complex multiplier; in this case the entire hierarchy is not shown just the pad frame with the arithmetic chip centered.

Figure 11: Pad Frame Layout of Arithmetic Chip

Conclusion:

After completion of the pad frame design, the intention was to use MACH-TA software to simulate the chip. Unfortunately the software was not functioning. Software not functioning properly resurfaced multiple times throughout the entire process from start to finish. Due to these software errors and problems, groups were not able to complete their chip design until the deadline was near. All designs up to the pad frame were completed and checked successfully both with DRC checks and LVS checks. It is assumed that after fabrication, the chip should function as planned.

References:

http://ece.unh.edu/courses/ece715/design_flow.htm

http://ece.unh.edu/courses/ece715/mentor_source/adk.html

http://www.mosis.com


				
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