# Implementing Logic Gates and Circuits

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```					Implementing Logic Gates
and Circuits
Lecture L4.4
Implementing Logic Gates
and Circuits
• Logic With Relays
• Integrated Circuit Implementation of Gates
• Transistor-Transistor Logic (TTL)
• Programmable Logic Devices (PLDs)
• Complex Programmable Logic Devices
(CPLDs)
• Field Programmable Gate Arrays (FPGAs)
Relays

A                          A
C                          C

B                          B
Normally Open Relay       Normally Closed Relay
A-B closed when C = 1     A-B open when C = 1
(current through coil)    (current through coil)
NOT Gate
NOT                   5V
X             Y
closed
Y = ~X            0         1
X
Y
open
X         Y
0         1
1         0
NOT Gate
NOT                      5V
X            Y
open

1        0
Y = ~X           X                Y

X         Y                       closed

0         1
1         0
AND Gate
5V
X              X
Z
Y              Y

Z
X   Y   Z
0   0   0
0   1   0
1   0   0
1   1   1
AND Gate
5V
0
X                  X
Z
Y 0                Y

Z
X   Y   Z
0   0   0
0   1   0
1   0   0
1   1   1
AND Gate
5V
0
X
X
Z
1              Y
Y

Z
X   Y   Z
0   0   0
0   1   0
1   0   0
1   1   1
AND Gate
5V
1
X
X
Z
Y 0                Y

Z
X   Y   Z
0   0   0
0   1   0
1   0   0
1   1   1
AND Gate
5V
1
X
X
Z
Y 1                Y

Z
X   Y   Z
0   0   0
0   1   0
1   0   0
1   1   1
OR Gate
5V

X
Z
Y
Z

X   Y   Z
X                 0   0   0
0   1   1
1   0   1
Y                 1   1   1
OR Gate
5V

X
Z
Y
Z

X   Y   Z
X                     0   0   0
0
0   1   1
1   0   1
Y                     1   1   1
0
OR Gate
5V
X
Z
Y
Z

X   Y   Z
X                      0   0   0
0
0   1   1
1   0   1
Y                      1   1   1
1
OR Gate
5V

X
Z
Y
Z

X   Y   Z
X                     0   0   0
1
0   1   1
1   0   1
Y                     1   1   1
0
OR Gate
5V
X
Z
Y
Z

X   Y   Z
X
1                 0   0   0
0   1   1
1   0   1
Y                     1   1   1
1
Implementing Gates Using
MOSFET Integrated Circuits
Relays                    A                 A
A
C                C
C
B                 B

B           nMOS transistor   pMOS transistor
A-B closed when   A-B closed when
Normally open
C=1               C=0
Normally closed
(normally open)   (normally closed)
NOT Gate
5V

X            Y

X        Y
Y = ~X

X   Y
0   1
1   0
NOT Gate
5V

X            Y
0        1
X                Y
Y = ~X

X   Y
0   1
1   0
NOT Gate
5V

X            Y
1        0
X                Y
Y = ~X

X   Y
0   1
1   0
NAND Gate
5V

Z   X
Z
X                   Y

X   Y   Z
0   0   1
Y                       0   1   1
1   0   1
1   1   0
NAND Gate
5V

Z   X
0                                   Z
X                       Y

X   Y   Z
0                       0   0   1
Y                           0   1   1
1   0   1
1   1   0
NAND Gate
5V

Z   X
0                                   Z
X                       Y

X   Y   Z
1                       0   0   1
Y                           0   1   1
1   0   1
1   1   0
NAND Gate
5V

Z   X
1                                   Z
X                       Y

X   Y   Z
0                       0   0   1
Y                           0   1   1
1   0   1
1   1   0
NAND Gate
5V

Z   X
1                                   Z
X                       Y

X   Y   Z
1                       0   0   1
Y                           0   1   1
1   0   1
1   1   0
NOR Gate
5V

X
X
Z
Y
Y

Z

X   Y   Z
0   0   1
0   1   0
1   0   0
1   1   0
NOR Gate
5V
0
X
X
Z
Y
0
Y

Z

X   Y   Z
0   0   1
0   1   0
1   0   0
1   1   0
NOR Gate
5V
0
X
X
Z
Y
1
Y

Z

X   Y   Z
0   0   1
0   1   0
1   0   0
1   1   0
NOR Gate
5V
1
X
X
Z
Y
0
Y

Z

X   Y   Z
0   0   1
0   1   0
1   0   0
1   1   0
NOR Gate
5V
1
X
X
Z
Y
1
Y

Z

X   Y   Z
0   0   1
0   1   0
1   0   0
1   1   0
AND Gate
5V
5V

Z

X

Y           NAND-NOT
OR Gate
5V

X           NOR-NOT
5V

Y

Z
Transistor-Transistor Logic
(TTL)
• Developed in mid-1960s
• Large family (74xx) of chips from basic
gates to arithmetic logic units
• Becoming obsolete with the development of
programmable logic devices (PLDs)
TTL Chips
14 13 12 11 10      9   8

7 4 0 4 H e x In ve rte rs

1   2   3   4   5   6   7

14 13 12 11 10      9   8

7 4 0 8 Q u a d 2 -In p u t A N D G a te s

1   2   3   4   5   6   7

14 13 12 11 10      9   8

7 4 3 2 Q u a d 2 -In p u t O R G a te s

1   2   3   4   5   6   7
TTL NAND, NOR, XOR
14   13 12 11 10     9   8

7 4 00 Q u ad 2 -Inp u t N AN D G ate s

1    2   3   4   5   6   7

14   13 12 11 10     9   8

7 4 02 Q u ad 2 -Inp u t N OR G a te s

1    2   3   4   5   6   7

14   13 12 11 10     9   8

7 4 86 Q u ad 2 -Inp u t E XCL U S IV E -O R G a tes

1    2   3   4   5   6   7
TTL Multiple-input Gates

14   13 12 11 10     9   8

7 42 1 Du a l 4 -In pu t AN D Ga tes

1    2   3   4   5   6   7

14   13 12 11 10     9   8

7 43 0 8-In pu t N AN D G a te

1    2   3   4   5   6   7
Small-Scale Integrated (SSI)
Circuits
• 1 to 10 gates
• NAND gate has 4 transistors
Medium-Scale Integrated (MSI)
Circuits
•   10-100 gates
•   Comparators
•   Multiplexers
•   Decoders
Large-Scale Integrated (LSI)
Circuits
• 100-1000 gates
• Arithmetic Logic Units
Very-Large-Scale Integrated
(VLSI) Circuits
• >1000 gates
• Microprocessors
• Programmable Logic Devices (PLDs)
• Complex Programmable Logic Devices
(CPLDs)
• Field Programmable Gate Arrays (FPGAs)
Basic PLD Structure
X       Y

removable
jumpers

A
1
Z

2
B

X   ~X   Y   ~Y
Alternate PLD Representation
X       Y

A
X    X   X   X    1
Z

X    X   X   X    2
B

X   ~X   Y   ~Y
PLD Connections for XOR
X       Y

A
X            X    1
Z = X & ~Y
| ~X & Y
X   X        2
B

X   ~X   Y   ~Y
1975 –
Signetics invents
the FPLA
1978 – MMI
introduces the PAL
1983 –
AMD introduces
the 22V10

1984 – Lattice
introduces the GAL
– an electrically erasable PAL
The GAL 16V8
1            Vcc    20
I/CLK
2     I      I/O    19
3            I/O    18
I
4    I       I/O    17
5    I       I/O    16
6    I       I/O    15
7    I       I/O    14
8    I       I/O    13
9    I       I/O    12
10   GND            11
I/OE
GAL 16V8
Structure of the GAL 16V8 PLD
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X   Z
P in 1 9
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X
P in 2

Y
P in 3
GAL 16V8 Input Buffer

X
X
~X
Structure of the GAL 16V8 PLD
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X   Z
P in 1 9
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X
P in 2

Y
P in 3
GAL 16V8 Polarity Control
OE

A
C
Pin
B
Polarity X       X closed B = 0   C=A
- open B = 1     C = ~A
Structure of the GAL 16V8 PLD
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X   Z
P in 1 9
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X X X X   X X X X
X
P in 2

Y
P in 3
XC9500                                                             CPLDs
3
In-System
JTAG
JTAG Port           Controller
Programming Controller   •   5 volt in-system
programmable (ISP)
CPLDs
Function
•   5 ns pin-to-pin
I/O
Block 1   •   36 to 288
I/O                                                            macrocells
(6400 gates)
Function
I/O
I/O                          Block 2   •    Industry’s best pin-
Blocks       FastCONNECT                    locking architecture
I/O                             Switch Matrix
•   10,000
Function
Global
Block 3
program/erase
Clocks         3
cycles
Global
Set/Reset           1
•   Complete IEEE
Global
Function       1149.1 JTAG
Block 4
Tri-States                                                          capability
2 or 4
XC9500 Function Block
Global     3      Global     2 or 4
Clocks           Tri-State
Macrocell 1                         I/O

AND     Product-
Array     Term
Allocator
36

From
FastCONNECT

Macrocell 18                        I/O
To
FastCONNECT

Each function block is like a 36V18 !
XC9500 Product Family
9536   9572    95108   95144   95216   95288

Macrocells    36     72      108     144     216     288

Usable       800    1600    2400    3200    4800    6400
Gates
tPD (ns)      5      7.5     7.5     7.5     10      10

Registers     36     72      108     144     216     288
Max I/O       34     72      108     133     166     192

Packages     VQ44
PC44   PC44
PC84    PC84
TQ100   TQ100
PQ100   PQ100   PQ100
PQ160   PQ160   PQ160
HQ208   HQ208
BG352   BG352
Xilinx 95108
• 6 function blocks
– Each contains 18 macro cells
– Each macro cell behaves like a GAL32V18
• AND-OR array for sum-of-products
• 32 inputs and 18 outputs
Architecture of the
Xilinx XC95108
CPLD
PLDT-3
Buttons

Xilinx
XC95108 CPLD

7 segment display

Switches

LEDs
PLDT-3
•   12 macro cells connected to I/O pins
•   4 pushbuttons
•   8 toggle switches
•   8 dip switches
•   16 LEDs
•   2 7-segment displays
•   On-board clock signals (4 MHz and 1 Hz)
FPGAs

Field Programmable Gate Arrays
1985 –
Xilinx introduces the
LCA (Logic Cell Array)

The Xilinx XC3000 CLB
(configurable logic
block).
1991 – Xilinx introduces the
XC4000 Architecture
Vcc
Slew        Passive
CLB                                  CLB                                                      Rate        Pull-Up,
Control     Pull-Down

Switch
Matrix                                                                     D   Q
Buffer

Input
CLB                                  CLB                                                                  Buffer
Q   D       Delay

Programmable
Interconnect                                                                      I/O Blocks (IOBs)
C1 C2 C3 C4

H1 DIN S/R EC
S/R
Control

G4                      DIN
G3    G                  F'
SD

G2   Func.               G'                        D        Q

Gen.                H'

G1
EC
RD
1

H       G'
Y
Func.     H'
S/R

F4             Gen.                      Control

F3     F                DIN
Func.                                             SD
F2   Gen.
F'
G'                        D        Q

F1                       H'

EC
RD
1

X

XC4003 contained 440,000 transistors
H'
F'

K

Configurable                                                      0.7-micron process
Logic Blocks (CLBs)
XC4000E/X Configurable Logic
Blocks
C1 C2 C3 C4
• 2 Four-input function
generators (Look Up                        H1 DIN S/R EC
Tables)                                                   S/R
Control

- 16x1 RAM or         G4                    DIN
SD
G3    G               F'
D        Q   YQ
Logic function      G2   Func.
G'
H'
Gen.
• 2 Registers           G1                                               EC
RD
- Each can be                        H       G'
1

Y
H'
configured as Flip               Func                       S/R

.Gen.
Control

Flop or Latch       F4
F3     F              DIN
SD
- Independent              Func.            F'
D        Q   XQ
F2   Gen.             G'
H'

clock polarity      F1
EC
- Synchronous and                            H'
1
RD

X
asynchronous             K
F'

Set/Reset
Look Up Tables
• Combinatorial Logic is stored in 16x1 SRAM Look Up
Tables (LUTs) in a CLB                   Look Up Table
Combinatorial Logic
A B C D         Z
A                                                           4
0   0   0   0   0    (2 )
B
Z        0   0   0   1   0   2
C
D
0   0   1   0   0   = 64K !
0   0   1   1   1
0   1   0   0   1
 Capacity is limited by number of      0   1   0   1   1
inputs, not complexity                    . . .
 Choose to use each function           1   1   0   0   0
generator as 4 input logic (LUT) or   1   1   0   1   0
as high speed sync.dual port          1   1   1   0   0
RAM            WE                     1   1   1   1   1
G4
G3    G
G2   Func.
Gen.
G1
What’s Really In that Chip?
Programmable Interconnect Points, PIPs (White)
Switch      Routed Wires (Blue)
Matrix

Direct
Interconnect
(Green)

CLB
(Red)

Long Lines
(Purple)
1998 – Xilinx introduces the
Virtex®™ FPGA family
0.25-micron process
2003 – Xilinx introduces the
Spartan®™-3 family of products

Very low cost

World’s first
90 nm FPGA
Block diagram of Xilinx Spartan IIE FPGA
Each Spartan IIE CLB contains
two of these CLB slices
Block diagram of Xilinx Spartan-3 FPGA
Each Spartan-3 CLB contains
four CLB slices
CPLDs vs. FPGAs
Xilinx will release the world’s first
one-billion transistor device this year
10000

Moore's Law
1000
(Doubling every 2 years)                                      x
100
16M
Pentium 4
Transistors (in millions)

10                                               4M
Pentium II
1M      486               Pentium
1

64K   286                                                  Memory
0.1                                                                           Microprocessor
8080

0.01

0.001
1974 1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010
Year

```
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