fpga_image_registration_workflow_modules.pdf by Flavio58

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									Brandyn White - FPGA Image Registration Overview
The blue background modules are to be present in the final system,the peach colored ones may be put together at some point for testing and verification as needed. Random Image Access Sequential neighborhood access Sequential Image Access Control/ Misc

Registration Pipeline
Select Image and pyramid level

Pyramid Pipeline
Select Pyramid Level

Stream image1 pyramid pixel values (convolution)

Read previous image 'convolution' style Stream image2 pyramid coordinates (convolution) Smooth/ Downsample Image

Lookup image1 pyramid pixel value

Transform using homography

Write image back to memory Compute Ix,Iy,It Lookup image2 pyramid pixel value

Input Pipeline
Compute A/b matrices Sum A/b matrices Input Image Save to RAM

After all pyramid pixels

Update homography and pyramid level

Solve linear system

Basic Registration Test
Input 2 images from VGA to ZBT Stream from ZBT (convolution)

Registration/Pyramid Test
Input 2 images from VGA to ZBT

Full Registration Test
Input 2 images from VGA to ZBT

Linear Solution Test
Initialize A/b matrix values Solve linear system Produce homography H

Video in/save/out Test
input image from VGA

Video in/save/conv/out
input image from VGA

Create pyramids

Create pyramids

Save to ZBT

Save to ZBT

Compute Ix,Iy,It

Stream from ZBT (convolution)

Stream from ZBT (convolution)

Read from ZBT

Convolve w/ Derivative Kernel

Create A/b matrices

Compute Ix,Iy,It

Warp Image2 w/ a homography

Output to DVI

Read from ZBT

Homography Test
Sum A/b matrices Create A/b matrices Compute Ix,Iy,It Initialize H matrix values Stream pixel coordinates (convolution) Output to DVI

Output in chipscope/review

Sum A/b matrices

Create A/b matrices

Output in chipscope/review

Sum A/b matrices

Warp Image w/ a homography

Output in chipscope/review

Output in chipscope/review


								
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