Majeure d'Electronique du composant au système

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					       Phy559                   Petite Classe n°2 « Circuits Intégrés VLSI »




                                 Parcours E.E.
                          "Integrated Circuits" Course
                               Petite Classe n°2
                                  Correction

1st part : How to design a NAND2
Schematic layout of a NAND2 gate.
Active areas N+ et P+ are vertical                                                                 S
Gates and output data in horizontal (Polysilicon)
Vss et Vdd power vertical (Metal)                                       A

                                                                        B




                                                                               V ss   V dd
Design VLSI




Année 2008 (X2006)                                                                           1/7
       Phy559                          Petite Classe n°2 « Circuits Intégrés VLSI »




2nd part : Layout of a circuit performing the carry of a one-
bit adder.
Goal:
The goal is to define the masks layout of an integrated circuit performing the carry of a one-
bit adder. The following schematic will be used as a basis for this study.

                                                  V dd

                                   A              B


                                   C              A

                                                  B            S                  S
                                       A      A           B

                                   B                  C

                                               Vss



 Define the schematic layout of this function



                                                                                      S
                        A

                        B

                        C


                        A
                        B


                            V ss
                                                              Vdd




Année 2008 (X2006)                                                                        2/7
       Phy559                   Petite Classe n°2 « Circuits Intégrés VLSI »




 Design the masks layout of this function




                3rd part : Design and layout of a 3-bit counter
Goal:
The goal is to design the masks layout of a N-bit counter integrated circuit. This function has
N inputs and N+1 outputs. The Kst output will be a logical High state if k inputs are High
states.
Here we will study the example of 3 inputs (A, B, C).


                           A                                                   Z0
                           B                                                   Z1
                                                                               Z2
                           C
                                                                               Z3

Questions
What are the boolean expressions of the 4 outputs (Z0, Z1, Z2, Z3).

 z 0 = a.b.c                           z1 = a.b.c + a.b.c + a.b.c
 z 2 = a.b.c + a.b.c + a.b.c           z3 = a.b.c




Année 2008 (X2006)                                                                       3/7
       Phy559                    Petite Classe n°2 « Circuits Intégrés VLSI »




Design the schematic of the counter using logical gates (only NAND3 et INV).




                     0                          Z0                              Z0

                     1

                     2
                                                    Z1                          Z1
                     3

                     4
                                                      Z2
                                                                                Z2
                     5

                     6

                     7                            Z                             Z3
                                                  3

     A B C


We now want to design this circuit using pre-characterized cells as shown below.
                         VDD

                                   S    E1 E2     E3




                         VSS




Precharacterized cells are designed in order to be tiled in the X and                VDD
Y directions, and in order to ease the automatic routing :
   • Fixed height (for example 10 pitches)
                                                                                           S   E1E2 E3
   • Variable width (whole number of pitches)
   • N well with a fixed height
   • Vdd and Vss power with fixed height, horizontal metal 1
   • Input/Output in metal 1 on the routing array


Année 2008 (X2006)                                                                                  4/7


                                                                                     VSS
       Phy559                       Petite Classe n°2 « Circuits Intégrés VLSI »




The NAND3 gate is 5 pitches wide.
The 3 inputs E1, E2, E3, may be connected on 6 lines.
The output signal is available on 7 lines.



     S E


                 The INVERTER width is 3 pitches
                 Input signal E is available on 6 lines.
                 Output signal S is available on 7 lines.




 We suppose that the pre-characterized cells are connected with the previous rules. Design
the metal connections (2 layers) in order to obtain the counter circuit.


                 N         0               1                 2                     4   Z   Z
                 A                                                                               Z
  A                                                                                    1   0
                                                                                                 1


                                                                                                 Z
                                                                                                 0


                                                                                                Z
                                                                                                3

 B
 C                                                                                              Z
                                                                                                2
           N         N      3              5                  6                    7   Z   Z
           C         B                                                                 2   3


                                4th part : Study of an ALU
Goal:
The goal is to perform the retro-engineering of the masks layout of an integrated circuit
already fabricated. In this case it will be an Arithmetical and Logical Unit (ALU).



Année 2008 (X2006)                                                                             5/7
       Phy559                    Petite Classe n°2 « Circuits Intégrés VLSI »




Questions
 Extract the schematic of the ALU using the following masks layout.




                                            -P
                                                                                      -P

                                                                                  P
                -G       NAND2                          -G
                                                                         INV

                                              P
                                              D          P               G
                                              N          U
                                                                                           XOR2
                                                         N              P
                                             Logiq
                NAND3                         ue                                OU2
                                              de
                           OU3                    Passag                 INV
                                                  e
                                                                         -P




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        Phy559                       Petite Classe n°2 « Circuits Intégrés VLSI »




       Identify the several gates of the circuit

                                        C2      -Cin                                  C1   C2   C3   operation
                                                                                      1    0    0    addition
                                                                                      1    1    0    AND
                                                                                      0    0    1    OR
                                      C3                                              1    0    1    XOR




 C2
 E1
 E2
                                 -P                                                                   -S


                                 G
 C1
                                                                                    Vcc



                                               -Cout




Année 2008 (X2006)                                                                                           7/7