High performance total internal reflection type optical switches by pharmphresh30

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									    High performance total internal reflection type optical switches in
                         silicon-on-insulator
     D. Thomson1, A. P. Knights2, D. Walters2, G. Z. Mashanovich1, B Timotijevic1, F.Y.Gardes1
                                           G. T. Reed1.

                        1-Advanced Technology Institute, University of Surrey, UK.
                           2-McMaster University, Hamilton, Ontario, Canada.

                                                        ABSTRACT

The requirement of a precise and controllable reflection interface in total internal reflection type optical switches is
widely acknowledged. When these switches are based upon carrier injection such as those fabricated in silicon-on-
insulator the ability to set up a precise reflection interface becomes difficult due to the diffusion of carriers. This
diffusion of carriers across the reflection interface creates a refractive index gradient which is likely to cause the input
light to be imperfectly reflected into the output port, which is obviously less efficient than reflection from a precise
interface in terms of loss due to the absorption by the free carriers and the directivity of the reflected wave. In our work
we propose the use of a barrier positioned along the reflection interface, and around a completely enclosed injection
region to prevent diffusion of carriers, and therefore set up a precise reflection interface. The barrier will also improve
the injection efficiency since the carriers are being injected into a much smaller volume. This will, in turn, lead to a
reduced switching current and faster switching speeds. This paper reports the modeling of the device and predicts the
bandwidth performance for one specific switch design.


                                                   1. INTRODUCTION

The development of a high performance silicon-on-insulator switch is essential for the development of low cost stand
alone optical switches, switching matrices and also integrated photonic optical circuits. Total internal reflection based
switches can be advantageous over other optical switching topologies since they can be designed to be wavelength
insensitive, polarization insensitive and relatively short in length. Many total internal reflection based switches have been
reported throughout the literature in both silicon and other electro optic materials. Problems associated with previous
designs include high switching currents and the inability to create a precise reflection interface during switching.
          High crosstalk figures between the output arms of the types of waveguide crossings such as those used in this
type of switch are experienced when the interception angle between the waveguides is small. The problem can be
resolved by increasing this interception angle at the cost of higher switching currents and slower switching speeds. In this
paper we show through optical modeling, how waveguide tapers can be used in the crossing region to reduce the
crosstalk at small interception angles, therefore removing the requirement of a higher switching current.
          In the literature many attempts have been made to confine or guide injected carriers to the required regions in
the device [1-5] , they have however lacked the ability to stop the diffusion of carriers throughout the guiding layer. If
carriers are allowed to diffuse away from the region where they are required the carrier injection efficiency is reduced.
These ‘stray’ carriers may also cause unnecessary optical loss in other regions of the device or interfere with adjacent
devices, reducing the achievable packing density.
          In this paper we present a method for reducing the diffusion injected carriers outside of the required active
region of the device within the guiding layer itself. Through the use of modeling it is shown how the concentration of
carriers can be increased in the required region as well as improving the switching speed for a given drive current
through the use of carrier confinement in the guiding layer. Devices are modeled electrically and optically to predict a
switching bandwidth of 100MHz for a specific design.




                      Silicon Photonics II, edited by Joel A. Kubby, Graham T. Reed, Proc. of SPIE Vol. 6477
                                   647713, (2007) · 0277-786X/07/$18 · doi: 10.1117/12.713641


                                                Proc. of SPIE Vol. 6477 647713-1
     2. TOTAL INTERNAL REFLECTION SWITCH DESIGN AND SWITCHING OPERATION


The layout of a basic total internal reflection switch in SOI is shown in figure 1. It consists of two crossing silicon rib
waveguides at an angle; θ. Running along the active side of the reflection interface on the top of the rib is a shallow p-
type doped region connected to an aluminum anode. An n-type region along with connecting cathode are placed on the
top of the slab separated from the p-type region by a volume of intrinsic silicon to set up a PIN diode structure on the
active side of the reflection interface.




                                               Reflected output                                   Traimmifted
                                                 waveguide                                    output waveguide




                                                                                                                  N type
                                                                                                                  Doping


                                                                                                              Cathode




                    h'puut
                   ave guide

                               Figure 1 – Diagram of basic total internal reflection optical switch layout.

         When a forward bias is applied across the PIN diode carriers are injected into the active region modifying the
refractive index due to the free carrier plasma dispersion effect. This change in refractive index causes a change in the
angle required for light incident on the reflection interface to be totally internally reflected (the critical angle). If a
sufficient forward bias is applied for a specific crossing angle, input light will be reflected into the ‘reflected’ output
waveguide. Under zero bias conditions light will pass through, and to the ‘transmitted’ output waveguide since there is
no difference in refractive index on either side of the crossing region.


                                    3. MODIFICATIONS TO THE BASIC DESIGN

Modifications to the basic design have been made to improve the devices performance. Aside from the problem of carrier
diffusion is the issue of crosstalk between the output arms of the switch. It has been recognized in the literature [6] that
when interception angles of waveguide crossings such as those used in the switch of this work become small




                                                   Proc. of SPIE Vol. 6477 647713-2
(approximately 6°<), the crosstalk between the output arms becomes very large. Optical modeling has been carried out
using BeamProp, a modeling package based upon the beam propagation method from Rsoft [7] to confirm this, see
figure 2.




                       Figure 2 - Crosstalk between the output arms as a function of half interception angle.


          If a large interception angle is used to ensure low levels of cross talk, a larger refractive index change for
switching is required since light will be incident on the reflection interface at a smaller angle. This is undesirable as it
will require a larger switching current. A more attractive solution to the crosstalk problem would be one where the
interception angle between the crossing waveguides does not have to be increased. By use of modeling it has been found
that if the waveguide widths are tapered out as they approach the crossing region, crosstalk can be reduced. A parameter
called the taper factor has been used to describe the amount which the waveguide width tapers as it approaches the
crossing region. The taper factor is equal to the waveguide width in the center of the interception region divided by the
original width, tapering over a 100µm propagation length. Figure 2 also demonstrates how small crosstalk figures can be
achieved at small interception angles if the taper factor is increased. Modeling has shown no significant detrimental
effect on the switching current requirement through the use of such tapers.

                                             4. CARRIER CONFINEMENT

A method of restricting the diffusion of carriers to within a region on one side of the waveguide crossing region is to be
described. This method makes use of a thin insulating SiO2 barrier. By etching a trench to the buried oxide layer around
the required region, thermally oxidizing a thin layer of silicon on the surfaces of this trench and subsequently refilling
with polysilicon a thin SiO2 layer can be produced. Figure 3 shows the layout of the device with this SiO2 layer.




                                                 Proc. of SPIE Vol. 6477 647713-3
                                                      'Reflected' output                    'Transmitted' output
                                                         waveguide                              waveguide




                                                                                                                   Inner Si02 barrier

                                                                                                             — Ntypedopedregion




                                                                                                        P type doped region

                                                                                                        ode
                                               Intrinsic Silicon



                            Input waveguide     Buried Oxide


                                               Figure 3 - Diagram of device with SiO2 Barrier

          It can be seen that the inner SiO2 barrier is positioned along the interception region to set up a precise reflection
interface. Away from the reflection interface the barrier is design to cross the waveguides perpendicular to the direction
of propagation to minimize any perturbation of the propagating light. The use of such a barrier in silicon photonic
devices has been demonstrated in recent years to form a MOS phase modulator [8] and in other phase shifting based
devices [9] without significant perturbation of the optical mode.
          Modeling has been carried out in ATLAS a device simulation package from SILVACO [10] to show the ability
of a thin SiO2 barrier at stopping the diffusion of carriers. To carry out this modeling a test structure was produced which
consisted of a non active silicon region and an active silicon region (containing a PIN diode structure) separated by a
3nm SiO2 layer. The carrier concentration along a line perpendicular to the barrier has been examined with the
application of a forward bias. This carrier concentration has been plotted in figure 4.

                                                                                     Barrier Position

                            3.OOE+O1 9

                                               Carrier Injection Region                   Non-active region
                            2.50E+019

                      E
                      C-)
                            2.OOE+019           _________________________
                      o
                             1.50E+019
                      1)
                      C-)

                             1.OOE+019                                                    —.--- Electrons
                                                                                          —.-—Holes
                            5.OOE+018
                      0
                            O.OOE+000                                                                   ••
                                       0.90   0.92      0.94       0.96    0.98   1.00   1.02    1.04     1.06       1.08

                                                           Distplacement along line YY (urn)


                                              Figure 4 - Diffusion of carrier across 3nm barrier.




                                                        Proc. of SPIE Vol. 6477 647713-4
It can be seen in figure 4 that there is negligible diffusion across of this barrier. It can therefore be assumed that the
active region of the device is completely isolated. Using a device with rib height of 4um, a rib width of 2.8um, aslab
height of 1.77um, a waveguide interception angle of 1.5° and a taper factor of 1.8, further SILVACO modeling has been
carried out. This modeling demonstrates how both the concentration of carriers at the reflection interface can be
increased and transient response time of the carriers decreased, under the application of a forward bias.

                                                                                                      Intended position of
                                                                                                      reflection interface
                                                        3.00E+019

                                                                                W ithout barrier
                                                        2.50E+019               W ith barrier
                             Hole Concentration (cm )
                         -3




                                                        2.00E+019


                                                        1.50E+019


                                                        1.00E+019


                                                        5.00E+018


                                                        0.00E+000


                                                                    -5   -4        -3        -2        -1         0       1       2         3
                                                                                          Position across barrier (um)

                                                                                                            (a)

                                                        2.00E+019



                                                        1.60E+019
                         Hole Concentration (cm )
                        -3




                                                        1.20E+019

                                                                                                                      Without barrier
                                                        8.00E+018                                                     With barrier


                                                        4.00E+018



                                                        0.00E+000


                                                                              5.00E-009           1.00E-008           1.50E-008         2.00E-008
                                                                                                  Time (s)

                                                                                                      (b)

Figure 5 – Comparing (a) carrier concentration across the center of the interception region and (b) Transient response of the carrier
          concentration at the center of the interception region, with and without the barrier.

          Firstly figure 5(a) is a plot of the hole concentration along a cut line across the interception region half way up
the rib, both with and without a diffusion barrier. It shows how, without the use of a barrier, the free carriers freely




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diffuse across the intended position of the reflection interface to create a gradient in free carrier concentration across the
interception region, demonstrating the need for a method for restricting the diffusion of these carriers. It can also be seen
in figure 5(a) that by using a barrier to stop the diffusion of carriers, an increased carrier concentration can be achieved at
the reflection interface for the same drive conditions, as well as improved injection uniformity. Figure 5(b) shows the
transient response of holes at a probe point in the center of the interception region when a forward bias is applied. It can
be seen in this figure, that the response time is reduced when a carrier restrictive barrier is in place.

                                                               5. EXAMPLE DEVICE PERFORMANCE

By use of the data obtained from the SILVACO simulations for both carrier concentration against drive current and
against time the performance of an example device can be predicted. The same device has been used as described
earlier; i.e waveguide height 4um, rib width 2.8um, slab height 1.77um, waveguide interception angle 1.5° and taper
factor 1.8. The carrier concentrations have been exported and converted to changes in both the real and imaginary parts
of the refractive index by use of the expressions produced Soref and Bennett [11] for a wavelength of 1550nm:

                                                                      [(
                       ∆n = ∆ne + ∆nh = − 8.8 × 10 −22 ∆N e + 8.5 × 10 −18 (∆N h )0.8      ) (                   )]           Eq.1

                       ∆α = ∆α e + ∆α h = 8.5 × 10 −18 ∆N e + 6.0 × 10 −18 ∆N h                                               Eq.2

These changes in real refractive index and absorption have been imported into BeamProp [7]. Using this method it has
been possible to examine the behavior of the propagation light at 1550nm with different drive currents and upon the
application of a forward bias (transient response). Figure 6 shows how the normalized waveguide power in the reflected
and transmitted output waveguides varies with drive current for TE polarised light.

                                                     0.7                                                              Transmitted
                                                                                                                      Refelcted
                                                     0.6
                        Normalised Waveguide Power




                                                     0.5


                                                     0.4


                                                     0.3


                                                     0.2


                                                     0.1


                                                     0.0


                                                       0.000               0.002         0.004         0.006          0.008
                                                                                      Drive Current (A)


                                                           Figure 6 – Normalised waveguide power against drive current.

It can be seen in Figure 6 that a drive current of approximately 8mA is required to switch the output power from the
transmitted output waveguide to the reflected output waveguide. Figure 7 shows how output powers from each of the
output waveguides varies over time upon the application and removal of a 1.5v forward bias. It can be seen that the
response time (rise and fall) is approximately 2ns. This translates to a bandwidth in excess of 150 MHz.




                                                                            Proc. of SPIE Vol. 6477 647713-6
                                                              0.7                                                        Transmitted
                                                                                                                         Reflected
                                                              0.6

                     Normalised Wavguide Power
                                                              0.5


                                                              0.4


                                                              0.3


                                                              0.2


                                                              0.1


                                                              0.0


                                                                     3.20E-009               4.00E-009               4.80E-009
                                                                                             Time (s)
                                                                                                  (a)


                                                               0.7
                                                                                                                        Transmitted
                                                                                                                        Relfected
                                                               0.6
                                 Normalised Waveguide Power




                                                               0.5


                                                               0.4


                                                               0.3


                                                               0.2


                                                               0.1


                                                               0.0


                                                                     3.80E-008        4.00E-008          4.20E-008   4.40E-008
                                                                                                  Time (s)
                                                                                                  (b)


Figure 7 – Normalised waveguide power against time upon (a) the application of a 1.5v forward bias and (b) the removal of this
                                                     forward bias.




                                                                                 Proc. of SPIE Vol. 6477 647713-7
                                                  6. CONCLUSION

A total internal reflection based optical switch has been described in silicon-on-insulator. It has been shown that the
performance of the switch can be improved in terms of crosstalk by the use of waveguide tapers. The use of a thin
insulating SiO2 carrier restrictive boundary has been described. Modeling has shown how higher carrier concentrations
can be achieved at the reflection interface through the use of such a barrier relating to a lower switching current
requirement. It has also been shown that by isolating the active region of the device in this way can reduce the transient
response time meaning that faster switching speeds are possible. The SiO2 barrier will also mean that integration will be
aided and packing density improved since these devices can be packed in close proximity without interfering with one
other. Modeling results have predicted that for an example device the switching current is approximately 8mA and
switching time approximately 2ns, a device performance far superior previously reported devices. The device dimensions
and parameters used in this work are for example purposes and it expected that through optimization and scaling of the
device dimensions , that the performance can be significantly improved.

                                            ACKNOWLEDGEMENTS

We would like to acknowledge the EPSRC, UK for funding the project and the Royal Academy of Engineering for a
contribution towards travel expenses.

                                                   REFERENCES

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                                             Proc. of SPIE Vol. 6477 647713-8

								
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