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VLSI Design Flow

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					VLSI Design Flow

Lecture 3 Sept 10, 2002 Presented by Andy Laffely alaffely@ecs.umass.edu

Goal
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The course will cover basic theory and techniques

of digital VLSI

design in CMOS technology. Topics include: CMOS devices and circuits, fabrication processes, static and dynamic logic structures, chip layout, simulation and testing, low power techniques, design tools and methodologies, VLSI architecture. We use full-custom techniques to design basic cells and regular structures such as data-path and
memory. There is an emphasis on modern design issues in interconnect and clocking. We will also use several case-studies to explore recent real-world VLSI designs (e.g. Pentium, Alpha, PowerPC StrongARM, etc.) and papers from the recent research literature. On-campus students will design small test circuits using various CAD tools. Circuits will be verified and analyzed for performance with various simulators. Some final project designs will be fabricated and returned to students the following semester for testing. (4 credits)

Lecture Overview
  

TA web page
General design flow Introduce tools with a NOR gate example
Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice-Hall, 1996, first edition, ISBN 0-13-178609-1. Web Page for the book including Powerpoint and PDF of all slides, MAGIC, SPICE, etc. (Important list of errors (Errata) in the book) Note that the second edition of the textbook will be available in October 2002, however this course will use the first edition.

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Terminology
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Layout
–

Mask

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TA Page
www.ecs.umass.edu/ece/vspgroup/burleson/courses/558/

or
http://vsp2.ecs.umass.edu/vspg/658/TA_Tools/index.html  TA inforamtion
 

Different tools for Grad and Undergrad Useful links for


Models and Tools


 

Design rules
Hand calculation parameters Examples!!!!



ETC

Design Methodology
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Full Custom: The designer creates layout masks by hand.
– –

Potentially fastest and most power efficient designs

Long design cycle

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Standard Cell: The designer uses high level programing language to describe the system and lets the computer make the masks.
– –

Shorter design cycle Less efficient designs

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The full custom flow can produce very compact layouts, which run fast, but doing so can be involved. Using standard cells greatly reduces designer workload, but the resulting implementations can have wasted area and typically run slower. The following design flow and links are intended to introduce you to the tools involved. Each link contains an example of the approach or a tool you may use.

Design Flow


System Level Design



Logic Design


Logic Verification



Circuit Desgn


Performance Evaluation



Layout
 

Logic Verification
Performance Evaluation

System Design


Goal: Create a high-level (Behavioral) representation of your system


Tools: Verilog, VHDL, System C



Synthesizable (PLD’s and/or ASIC)
Non-synthesizable



More in future lectures

Logic Design and Verification


Translate system level discription into transistors
 

Many logic styles Schematic representation



Logic verification
 

Simplistic models - to verify functionality Fast - can run many cases




558 - Use DSC2
658 - Use Cadence Schematic HSPICE

Circuit Design
 

Calculate trasnsistor sizes Performance evaluation
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Complex models - to evaluate timing and power



Slow - run only selected cases

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558 - Use Microwind 658 - Use HSPICE

Layout


Translate schematic into layout
 

Need to know the design rules
Layout representation may not be similar to schematic



Logic verification



Compare netlists
Simulators

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Performance evaluation


Use detailed simulations

 

558 - Use Microwind 658 - Use Cadence Vertuoso, IRSIM, HSPICE


				
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