Self-Organization in Autonomous Sensor/Actuator Networks

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Registered clients of CMC can access the design files and documentation described below from the CMC Technology Gateway at https:/ (use Search) All trademarks are the property of their respective owners On Short-Term Loan: Equipment for Embedded Systems Development Description: Access the AMIRIX AP1000 FPGA development platforms and FPGA development systems for softwaredefined radio (SDR) and video applications. Plus access add-on modules for the AMIRIX platform including analog I/O card; 4-channel, high-voltage amplifier; and AC adapter. Availability: For a list of available equipment and to book: MEMS/FPGA Prototyping Platform Description: Design and validate a microsystem from a system-level perspective by integrating signal processing and control algorithms with custom MEMS devices. Achieve this using reprogrammable hardware, embedded software, analog interfacing and high-voltage amplification. The MEMS/FPGA prototyping platform is a complete, bench-top environment, consisting of an integrated set of hardware modules, design tools, libraries, reference designs and documentation. Demonstrations and instructions to help users get started with this platform. The demonstrations include a NEW!! demo chip and programs for high voltage and low voltage devices. Availability: Equipment is available on a short- or long-term loan basis (to book, see ‘On Short-Term Loan” above). Prototyping Station Using the Virtex-II Pro FPGA (AMIRIX) Description: Includes an AMIRIX AP1000 development board installed in the 64-bit PCI-X slot of an IBM Intellistation Z Pro workstation. With large FPGA gate capacity (44000 logic slices) and two embedded IBM PowerPC hard macros, as well as up to 1.4MB of on-chip RAM, this platform gives university researchers a highperformance, multiprocessor development environment. Supported by getting started documentation, application notes, reference designs, and design examples. CMC is delivering the following enhancements to the AMIRIX platform: NEW!! Video processing interface High-bandwidth Ethernet-based hardware co-simulation interface ZigBee 802.15.4 Wireless Interface Module for AP1000 Real-time data transfer from the AP1000 to MATLAB through the PCI bus HW/SW Co-Design Flow: Implementation from MATLAB to FPGA Agility DK Tutorial for AP1000 (C-to-FPGA) Availability: 300 stations have been deployed to 35 universities. Some additional stations are available through the equipment pool mentioned above. Embedded Software Design Description: Tools, flow, and documentation to create embedded software for systems based on the architectures that CMC supports (Nios II, Microblaze, PPC405 and user-built cores using Processor Designer). Tools include Xilinx's EDK, Altera’s Nios II IDE, ELDK for PPC, Mathworks' Real-time Workshop and Coware’s Processor Designer; as well as Embedded Linux for all CMC-supported processors. Supporting materials include documents on the development flow, a HW/SW co-design flow (from MATLAB to FPGA), getting started materials, and an application note describing how to develop device drivers for Linux Kernal 2.4. Updated Embedded Software Development Flow (V2.0): provides researchers with a generic flow for NEW!! embedded software development using CMC supplied tools. Version 2 incorporates the following enhancements: system-level design, automated code generation, and running executables in a simulation or virtual environment. Embedded Linux Description: Design files, application notes, user documentation and tutorials for creating and using the Embedded Linux OS kernel on CMC's supported processors. Includes Embedded Linux for Altera Nios II (including tutorial), Xilinx MicroBlaze, Amirix AP1000 board with PPC405 processor, and ARM Integrator/CM7TDMI.

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October 8, 2008 Page 1 of 2

MATLAB/Simulink-Based FPGA Design Flow Tutorial and Design Example Description: Using MATLAB/Simulink, implement a block-level design to the Virtex-II Pro FPGA of the AMIRIX AP1000 Prototyping Station. This tutorial and accompanying design example were developed in conjunction with Dr. Aman Al-Imari and Royal Military College of Canada. Multiprocessor SOC for FPGA and Simulation Description: Four microblaze microprocessors (with BRAM), DDR SDRAM, two UARTs and other components. Communication between microblaze processors is through a FSL (Fast Simplex Link) channel, with parallel image processing. This system can be implemented in two ways: 1. In a StepNP SystemC simulation environment 2. On the FPGA housed in the AMIRIX AP1000 board The release includes design files, installation instructions and tutorials for both approaches. Celoxica C-Based Hardware Design Tool, DK Description: Design and implement hardware using a C-based language, instead of relying on a low-level language such as VHDL or Verilog. The release from CMC includes DK Design Suite, PDK (Platform Development Kit), and two RC10 FPGA prototyping boards per site license. Availability: Tools have been distributed to 22 universities. Tensilica Dual-Core Processor Description: Explore multi-processor SOC design and customizable processor technology by developing applications for the Tensilica Xtensa configurable processor core in a dual-core SOC platform architecture. Includes a reference design that can be modified to suit your application. Tensilica Xtensa LX Configurable Processor: FPGA Implementation Service Description: Access hardware implementations (targeting Xilinx FPGAs) of the Tensilica Xtensa LX configurable processor technology. This technology is suitable for prototyping designs with low-power applications. Also available from the CMC Technology Gateway: design examples, including a multi-processor design example, reference design, and documentation to help users implement the hardware and software of a Tensilica Xtensa LX-based SOC design on the AMIRIX AP1000 platform. Availability: To access the online request form visit CoWare System-Level Tools Description: Platform Architect (SystemC-based design environment, including model libraries, for simulation, debug and analysis of system architectures); Processor Designer (design and implementation of applicationspecific processors); and Signal Processing Designer (block-based graphical design and simulation environment for DSP-based systems). Forte Cynthesizer Description: Behavioural synthesis of transaction-level models (TLM) in SystemC to RTL, targeting FPGA and ASIC hardware implementation. StepNP Simulation Platform Description: A multi-processor simulation platform targeting networking applications. It includes HW SystemC models (processor, memory, bus, etc.), SOC GUI tool for simulation analysis and display, and networking application software. Created by STMicroelectronics and donated for research at Canadian universities. Includes tutorial, reference manual and user guide documentation to reduce the learning curve for users. SOC Physical Design Environment Description: Libraries and IP for large digital chip design, including Cadence’s First Encounter (floorplanning), CeltIC (signal integrity) and Digital Design Environment (SOC design methodology based on Tality flows, instructional materials, million-gate example design with AMBA bus, AMBA Transactional Verification Models and Verification Reuse Methodology), Synopsys PrimeTime (static timing analysis) and Formality (equivalency checking), Artisan Components standard cell libraries for TSMC’s 0.18-micron CMOS. Physical Design Environment Description: Best-in-class tools from Cadence, Synopsys, and Mentor Graphics to design components (digital, mixedsignal, RF, analog, MEMS) across a number of technologies (e.g., 90nm, 180nm and 350nm CMOS). For design entry, synthesis, place-and-route, simulation, design rule checking, timing analysis, etc. Availability: CAD tools delivered through the STC environment. Licenses updated and delivered on a yearly basis. For further information contact Hugh Pollitt-Smith, CMC Microsystems, 613.530.4668,
© CMC Microsystems Trademarks are the property of their respective owners October 8, 2008 Page 2 of 2

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Description: Self-Organization in Autonomous Sensor/Actuator Networks