Title HotSpot—Achipand Package Compact Thermal Modeling

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WEI HUANG
Curriculum Vitae 450 Harvard Avenue, Apt 2C Santa Clara, CA 95051 http://www.cs.virginia.edu/%7Ewh6p/research.html Phone: (434) 227-6183 Email: wh6p@virginia.edu

PARTICULARS
RESEARCH OVERVIEW My research interest spans computer architecture and integrated circuit in the field of Computer Science and Engineering. My current research mainly focuses on physically-constrained computer architecture and VLSI– especially chip-level thermal analysis and temperature-aware design. I am the primary developer of HotSpot, a chip-level thermal modeling tool that has been quite successfully used in both academia and industry. I am also currently the moderator of HotLeakage, an architectural leakage power modeling tool. I received a Best Student Paper Award at International Symposium on Computer Architecture (ISCA) 2003, a Winner’s Award at the System-on-Chip (SoC) Design Challenge sponsored by the Semiconductor Research Coorporation (SRC) in 2006, and an Honorable Mention at ISSCC/DAC Student Design Contest in 2003. I have also taken initial steps in my research to address other topics inspired by the continued semiconductor technology scaling—the power wall, process and environment variations, reliability issues, 3D integration, and manycore architectures. Looking forward, I am expecting to apply my research experience and enthusiasm to advance the state of the art and explore techniques for future high-performance/low-power processor designs that are scalable and resilient to various physical constraints. EDUCATION University of Virginia Ph. D. in Electrical Engineering University of Science and Technology of China Bachelor of Engineering, Dept. of Automation CURRENT STATUS • citizen of China • pending US permanent resident, with work authorization • currently with H1B visa DISSERTATION Title: “HotSpot—A chip and Package Compact Thermal Modeling Methodology for VLSI Design.” Advisors: Prof. Mircea Stan (ECE) and Prof. Kevin Skadron (CS) My thesis develops a framework for the thermal characterization, analysis, and their applications in dealing with the thermal constraints of modern high-performance processors and other VLSI circuits. One accomplishment of my dissertation work is the HotSpot thermal modeling software that has been widely adopted by both academia and industry. Charlottesville, VA January 2007 Hefei, China June 1998

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AWARDS
• First Place Winner (Phase One) and Second Place Winner (Phase Two) in the System-on-Chip (SoC) Design Challenge sponsored by the Semiconductor Research Corporation (SRC), 2006. • Honorable Mention at 40th ISSCC/DAC Student Design Contest, 2003. The design was a high-performance analog Turbo Decoder implemented in SiGe technology. • Paper chosen as one of the IEEE Micro Top Picks in 2003. • Bob Rau Memorial Best Student Paper Award at International Symposium on Computer Architecture (ISCA), 2003.

OTHER ACCOMPLISHMENTS
• “HotSpot” thermal modeling tool has been downloaded over 1800 times. • My research papers have been cited over 700 times according to Google Scholar.

APPOINTMENTS
• Visiting Scholar, Department of Electrical Engineering, Stanford University, Aug 2009 - present. Research collaboration with Stanford Computer Research Laboratory (with Prof. Mark Horowitz’s group), in the areas of VLSI chip generator and novel architectures. • Research Associate, Department of Computer Science, University of Virginia, Jan 2007 - present. Thermalaware manycore architecture design; Enhancing HotSpot as an industry-strength tool with better solver stability, higher speed and new features such as 3D integration, secondary heat transfer path and details of thermal packages; thermal granularity and processor thermal design power (TDP) scalability analysis for emerging manycore architecture; Identifying issues with using runtime infrared measurements for temperature-aware design; 3D architecture and 3D cooling implications. • Research Assistant, Department of Electrical and Computer Engineering, University of Virginia, Sep 2001 - Dec 2006. Research on chip-level thermal analysis, static and dynamic microarchitecture thermal management of processors; circuit and microarchitecture techniques to mitigate the impacts of thermally dependent reliability phenomena such as electromigration, negative bias temperature instability (NBTI), etc. • Research Co-op, IBM T. J. Watson Research Center, Jun 2004 - Aug 2004. Worked in IBM VLSI Design Department and characterized and analyzed the thermal behavior and leakage power of the IBM POWER5 processor. • Hardware Design Engineer, Alcatel China (now Alcatel-Lucent China), Jul 1998 - Jun 2001. Developed hardware and firmware for high-performance embedded telecommunication systems in Internet backbone network systems.

RESEARCH EXPERIENCE
• High-Performance Many-Core Design Exploration with Thermal Constraints In this research, I looked at the thermal impacts on symmetric and asymmetric manycore architectures. Small cores provide greater throughput per unit area and per watt when sufficient concurrency is available, motivating organizations with many simple cores. However, sufficient concurrency is often not available; even applications that can use many cores often have serial parts. Amdahl’s Law favors an asymmetric architecture and shows that one large, high-ILP cores are needed in these cases, but prior work has found the optimal sophistication of this core to be highly sensitive to workload characteristics. In order to deal with this problem, dynamic combination of multiple simple cores into one large, primary core for serial speedup has been proposed, but scalable solutions that can combine many cores into one have not yet been found.

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On the other hand, manycores, especially asymmetric manycores, exacerbate the thermal challenge because power scales with number of cores and complex out-of-order cores also create severe local hot spots, especially with performance boosting techniques. In this work, I extend the manycore Amdahl’s Law analysis with thermal constraints and study their impact on the manycore design paradigm. My results indicate that thermal constraints reduce performance as expected, but also make performance almost insensitive to the complexity of the primary core across a diverse range of parallelism values. This greatly relaxes the design complexity by reducing the necessary number of dynamic core combination configurations (e.g. for less than 5% performance loss, only two configurations are needed). With slightly more performance tolerance (e.g. less than 10% performance loss), dynamic core combination even becomes unnecessary. • Chip-Level Thermal Modeling and Analysis for High-Performance Architecture and Circuit Research Non-ideal CMOS technology scaling results in ever-increasing power density, especially local power density. With the shift towards a multicore and even manycore design paradigm, it is likely that the total power will also rise. The increase of both power density and total power present severe thermal challenges to chip designers. To tackle the thermal constraint, I developed HotSpot—a high-performance thermal modeling tool suitable for use in architectural and circuit studies. It is based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture or circuit blocks and essential aspects of the thermal package. HotSpot has a simple set of interfaces, making it straightforward to integrate into existing simulation tools such as SimpleScalar or Wattch. HotSpot has been used by some groups in the industry such as IBM Research, and we are starting to see its use in the EDA/CAD and ASIC/SOC design communities. • Runtime and Static Thermal Management Techniques at the Architecture Level Thermal packages have been expensive, especially for high-performance processors, making package design for the worst-case thermal scenario prohibitive. Therefore, people usually design for the typical case and as a result, to prevent thermal emergencies, static and dynamic thermal management have become indispensable for modern thermally constrained chips. I investigated several thermal management techniques. For static thermal management, proper floorplanning of circuit blocks help uniformly spread the heat, hence reducing hot spot temperature. This is especially beneficial for manycore designs—with increasing number of cores on the same die area, manycores can tolerate more thermal design power (TDP) without thermal violations and hence achieve higher performance. This is because heat transfer theory shows that smaller cores are usually cooler with the same level of power density. For dynamic thermal management, several effective methods were also introduced: “temperature-tracking” frequency scaling, localized toggling and migrating computation to spare hardware units or cores. • High-Performance Integrated Circuit Design I am familiar with the entire ASIC/SoC design flow, and have experiences with mixed-signal design for embedded applications. I am very interested in developing a technology-aware design flow for manycores/MPSoCs. I have the following hardware implementation experience: – A system-on-chip (SoC) implementation of a novel, award-winning ultrasound image enhancement algorithm, 2005-2006. (Winner of Semiconductor Research Corporation’s SoC Design Challenge) – An analog turbo decoder implemented in SiGe BiCMOS technology to demonstrate the advantages of both the turbo decoding algorithm and the strained-silicon process, 2003. (Honorable Mention at the ISSCC/DAC Student Design Contest) – Characterizations of on-chip inductors implemented in IBM 0.18µm copper process for microwave and radio-frequency circuit designs, 2001. • Reliability-Aware Architecture Design Most chip failure mechanisms are exponentially dependent on temperature, examples are electromigration (EM) of on-chip metal interconnects and negative bias temperature instability (NBTI) of PMOS transistors. Therefore, meeting the lifetime budget while maximizing performance is of great interest. My approach to this challenge was to treat lifetime as a resource whose consumption rate depends on the thermally dependent physical stresses and can be accurately estimated by a model I developed with my colleagues. With such a model, novel architecture-level techniques are developed and performance is significantly improved by reclaiming excessive design margins within the desired lifespan of a chip.

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• Thermal Characterization of High-Performance Industrial Designs High-performance chips from industry are thermally constrained nowadays, making accurate chip thermal characterization an important design and verification step. Commercial tools such as ANSYS, FloWorks are complicated and inefficient in terms of timely characterization and runtime analysis. As another approach, infrared (IR) runtime thermal imaging is gaining popularity as a direct way of detailed thermal measurements on chips running actual workloads. However, IR imaging also requires peculiar cooling configurations that are drastically different from normal thermal package, thus introducing design pitfalls. I used HotSpot to thermally characterize and validate actual industrial designs for companies such as IBM and NVIDIA. I also extended HotSpot to model what the IR camera sees during IR thermal measurements and revealed the potential problems of blind usage of IR measurements in chip thermal design without caution.

TEACHING EXPERIENCE
• Teaching Assistant. EE203: Introductory Circuit Analysis, Fall 2001 and Fall 2002, University of Virginia. • Teaching Assistant. EE204: Electrical Circuits, Spring 2002, University of Virginia. • Mentor for Undergrad Senior Theses. 1. Samuel Sierra: Silicon thermal sensing integrated circuits, 2004. 2. Shougata Ghosh (now a PhD student at Princeton): Grid-like thermal modeling for microprocessors, 2005. 3. Matthew Lindsey: On-chip interconnect thermal sensor, 2007. 4. John Burr: HotSpot in spreadsheet, in progress.

PUBLICATIONS
JOURNAL PAPERS 1. K. Sankaranarayanan, W. Huang, M. Stan and K. Skadron, “On the Granularity of Microprocessor Thermal Management”, under review with IEEE Transactions on Computers (TCOMP), 2009. 2. W. Huang, K. Sankaranarayanan, K. Skadron, R. J. Ribando, and M. R. Stan, “Accurate, Pre-RTL TemperatureAware Processor Design Using a Parameterized, Geometric Thermal Model”, IEEE Transactions on Computers (TCOMP), September, 2008. 3. Z. Lu, W. Huang, K. Skadron, J. Lach and M. R. Stan. “Interconnect Lifetime Prediction with Temporal and Spatial Temperature Gradients for Reliability-Aware Design and Runtime Management: Modeling and Applications”, IEEE Transactions on Very Large-Scale Integrated Circuits (TVLSI), February, 2007. 4. W. Huang, S. Ghosh, K. Sankaranarayanan, K. Skadron and M. R. Stan. “HotSpot: Thermal Modeling for CMOS VLSI Systems”, IEEE Transactions on Very Large-Scale Integrated Circuits (TVLSI), May 2006. 5. W. Huang, M. R. Stan and K. Skadron. “Parameterized Physical Compact Thermal Modeling”, IEEE Transactions on Component and Packaging Technologies (TCAPT), December, 2005. 6. K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, D. Tarjan, “Temperature-Aware Microarchitecture: modeling and implementation”, ACM Transactions on Architecture and Code Optimization (TACO), March 2004. 7. K Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. “Temperature-aware computer systems: opportunities and challenges”, IEEE Micro Magazine, Nov-Dec. 2003. 8. M. R. Stan, K. Skadron, M. Barcella, W. Huang, K. Sankaranarayanan, S. Velusamy, “HotSpot: a Dynamic Compact Thermal Model at the Processor-Architecture Level”, Microelectronics Journal, June 2003.

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CONFERENCE PAPERS 9. W. Huang, K. Skadron, S. Gurumurthi, R. Ribando and M. Stan. “Exploring the Thermal Impact on Manycore Processor Performance”, submitted to Annual Thermal Measurement, Modeling and Management Symposium (SEMI-THERM), Sept. 2009. 10. W. Huang, K. Skadron, S. Gurumurthi, R. Ribando and M. Stan. “Characterizing Infrared Measurements for Chip Thermal Management”, International Symposium on Performance Analysis of Systems and Software (ISPASS), April, 2009. 11. W. Huang, M. Stan, K. Sankaranarayanan, R. Ribando and K. Skadron. “Many-Core Design from a Thermal Perspective”, Design Automation Conference (DAC), June 2008. 12. W. Huang, K. Sankaranarayanan, R. Ribando, M. Stan, K. Skadron. “An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations”, WDDD workshop held in conjunction with International Symposium on Computer Architecture (ISCA), June 2007. 13. Z. Qi, W. Huang, A. Cabe, W Wu, Y Zhang, G. Rose, M. R. Stan. “A Design Methodology for a Low-Power, Temperature-Aware SOC Developed for Medical Image Processors”, IEEE International System-On-Chip Conference (SOCC), Sept. 2006. 14. W. Huang, E. Humenay, K. Skadron and M. Stan. “The Need for a Full-Chip and Package Thermal Model for Thermally Optimized IC Designs”. Intl. Symp. on Low Power Electronic Design (ISLPED), August 2005. 15. S. Velusamy, W. Huang, John Lach, Mircea R. Stan, Kevin Skadron, “Monitoring temperature in FPGA based SoCs” International Conference on Computer Design (ICCD), Oct. 2005. 16. K.-J. Lee, K. Skadron and W. Huang. “Analytical model for sensor placement on microprocessors” International Conference on Computer Design (ICCD), Oct. 2005. 17. S. Velusamy, W. Huang, J. Lach, M. Stan, and K. Skadron. “Experiences using FPGAs for TemperatureAware Microarchitecture Research.” Workshop on Architecture Research using FPGA Platforms (WARFP), in conjunction with the 11th IEEE International Symposium on High Performance Computer Architecture (HPCA), Feb. 2005. 18. Z. Lu, W. Huang, J. Lach, M. Stan, K. Skadron. “Interconnect Lifetime Prediction under Dynamic Stress for Reliability-Aware Design”. International Conference on Computer Aided Design (ICCAD), November 2004. 19. W. Huang, M. R. Stan, and K. Skadron. “Physically-Based Compact Thermal Modeling -Achieving Parameterization and Boundary Condition Independence.” International Workshop on Thermal Investigations of ICs (THERMINIC), Sept. 2004. 20. W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy. “Compact Thermal Modeling for Temperature-Aware Design”. Design Automation Conference (DAC), June 2004. 21. K. Skadron, M.R. Stan, W. Huang, K. Sankaranarayanan, Z. Lu, and J. Lach. “The Need for a ComputerArchitecture Approach to Thermal Management in Computer Systems.” IEEE International Conference on Thermal, Mechanical and Thermo-Mechanical Simulation and Experiments in Micro-electronics and Microsystems (EuroSimE), May 2004. (Keynote presentation within session.) 22. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. “Temperature-Aware Microarchitecture”. International Symposium on Computer Architecture (ISCA), June 2003. (Best Student Paper Award) 23. K. Skadron, M. Stan, M. Barcella, A. Dwarka, W. Huang, Y. Li, Y. Ma, A. Naidu, D. Parikh, P. Re, G. Rose, K. Sankaranarayanan, R. Suryanarayan, S. Velusamy, H. Zhang, Y. Zhang. “HotSpot: Techniques for Modeling Thermal Effects at the Processor-Architecture Level”. International Workshop on Thermal Investigations of ICs (THERMINIC), Sept. 2002.

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TECHNICAL REPORTS 24. W. Huang, M. R. Stan, K. Sankaranarayanan, R. J. Ribando, and K. Skadron. “Many-Core Design from a Thermal Perspective: Extended Analysis and Results”, CS-2008-05, April 2008. 25. W. Huang; K. Sankaranarayanan; R. J. Ribando; M. R. Stan; K. Skadron. “An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations”, CS-2007-07, April, 2007. 26. E Humenay, W Huang, MR Stan, K Skadron, “Toward an Architectural Treatment of Parameter Variations”, CS-2005-16, October, 2005. 27. S. Velusamy; W. Huang; J. Lach; K. Skadron. “Monitoring Temperature in FPGA based SoCs”, CS-2004-39, December, 2004. 28. W. Huang; M. R. Stan; K. Skadron; K. Sankaranarayanan; S. Ghosh; S. Velusamy. “Compact Thermal Modeling for Temperature-Aware Design”, CS-2004-13, April 2004. 29. Z. Lu; W. Huang; S. Ghosh; J. Lach; M. R. Stan; K. Skadron. “Analysis of Temporal and Spatial Temperature Gradients for IC Reliability”, CS-2004-08, March 22, 2004. 30. W. Huang; Z. Lu; S. Ghosh; J. Lach; M. Stan; K. Skadron. “The Importance of Temporal and Spatial Temperature Gradients in IC Reliability Analysis”, CS-2004-07, January 6, 2004. 31. K. Skadron; M. R. Stan; W. Huang; S. Velusamy; K. Sankaranarayanan; D. Tarjan. “Temperature-Aware Microarchitecture: Extended Discussion and Results”, CS-2003-08, April 2003. 32. M. Barcella, W. Huang, M. R. Stan, K. Skadron, “Architecture-Level Compact Thermal R-C Modeling”, CS2002-20, July 2002.

PROFESSIONAL ACTIVITIES
• Journal reviewer for over 40 papers - IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD) - IEEE Trans. on Very Large Scale Integration (VLSI) Systems (TVLSI) - IEEE Trans. on Circuits and Systems, I (TCAS-I) - IEEE Trans. on Circuits and Systems, II (TCAS-II) - IEEE Trans. on Electron Devices (T-ED) - IEEE Design and Test of Computers Magazine (D&T) - ACM Transactions on Embedded Computing Systems (ACM TECS) - ACM Transactions on Design Automation of Electronic Systems (ACM TODAES) • Conference reviewer for over 50 papers - International Conference on Parallel Architectures and Compilation Techniques (PACT), 2009 - Design Automation Conference (DAC) 2006-2009 - Design, Automation and Test in Europe (DATE) 2006-2009 - International Conference on Arch. Support for Programming Lang. and Operating Systems (ASPLOS) 2008 - International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS) 2008 - Great Lakes Symposium on VLSI (GLSVLSI) 2006-2009 - International Conference on Computer-Aided Design (ICCAD) 2006-2007 - International Symposium on High-Performance Computer Architecture (HPCA) 2005

REFERENCES
(Additional references are available upon request.) Prof. Mircea Stan (thesis advisor) Professor Dept. of Electrical and Computer Engineering

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351 McCormick Road, Room THN E209 Charlottesville, VA 22904 Phone: (434) 924-3503 mircea@virginia.edu Prof. Kevin Skadron (thesis co-advisor) Associate Professor Dept. of Computer Science 151 Engineer’s Way, Room OLS 215 Charlottesville, VA 22904 Phone: (434) 982-2042 skadron@cs.virginia.edu Prof. Sudhanva Gurumurthi Assistant Professor Dept. of Computer Science 151 Engineer’s Way, Room OLS 236B Charlottesville, VA 22904 Phone: (434) 982-2227 gurumurthi@cs.virginia.edu Prof. Robert Ribando Associate Professor Dept. of Mechanical and Aerospace Engineering 122 Engineer’s Way, Room MEC 310 Charlottesville, VA 22904 Phone: (434) 924-6289 rjr@virginia.edu