International Conference on VLSI Design

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					12th International Conference on VLSI Design

Saturday, January 9,1999 Short Tutorials
MOS Modeling for Circuit Simulation Pratheep Balasingam (Synopsys Inc., USA.) Power Reduction Techniques for Portable DSP Applications Mahesh Mahendale (Texas Instruments, India) and Sunil Sherlekar (Silicon Automation Systems)

Full Day Tutorials
CAD Techniques for Embedded System Design Srinivas Devadas (Massachusetts Institute of Technology), Sharad Malik (Princeton University), Jose
Monteiro (INESWIST, Lisbon, Portugal) and Luciano Lavagno (Cadence Berkeley Labs). The advent of deep submicron processing technology has made it possible and desirable to integrate one or more processor cores, program ROM/RAM, and application-specific circuitry all on a single IC. This level of integration has resulted in a need for CAD systems for software, as well as hardware, synthesis. A CAD framework for embedded system design requires many different tools including software compilers, assemblers, and instruction-level simulators, and HDL compilers and simulators. In addition, tools for hardware/software partitioning and co-simulation are required. In this tutorial, we will describe state-of-the-art techniques for embedded system design. We will focus primarily on the Digital Signal Processing (DSP) application domain, though most of the techniques that we discuss have wider applicability.

Manufacturability of Mixed-Signal Systems Manuel d’ Arbreu (Level One Communications Inc.) and Abhijit Chatterjee (Georgia Institute of Technology)
The complexity of mixed-signal circuits and systems is expected to increase significantly in the coming decade particularly due to enabling packaging technologies allowing high levels of component integration. This trend is driven primarily by the communications industry with particular emphasis on high-performance, high-frequency design. The component densities in these mixed-signal systems will be so high as to prohibit exhaustive functional testing. It will become necessary to design tests in such a way as to detect common manufacturing defects at every stage of the IC manufacturing process. In this tutorial classes of manufacturing defects, introduced at by various silicon processing steps will be discussed. Based on an analysis of these defects, techniques for introducing design changes to avoid such defects will be presented (design for manufacturability). This will lead to a discussion of fault models, fast fault simulation techniques, test generation methods and fault diagnosis strategies for mixedsignal integrated circuits and packages. At the same time, process and manufacturing defect based test generation will be reconciled with specification-based test methods practiced. today.

O-7695-0013-7/99 $10.00 0 1999 IEEE
12’ International Conference on VLSI Design -January 1999 h