Advanced Technology Education


For your convenience, we can make a preliminary course reservation for you until you are ready to submit your firm course registration. This is with no financial commitment from your side.

COURSE RATES: 5-day course: € 2995 (€ 2725*) 4-day course: € 2490 (€ 2240*) 3-day course: € 1915 (€ 1720*) 2-day course: € 1310 (€ 1180*) *EARLY FIRM REGISTRATION RECEIVED 2 MONTHS BEFORE COURSE START. UNIVERSITY STUDENT AND FACULTY RATES: 2 participants for 1 course fee – paid from University Funds
The Course Fee includes Tuition, Course Documents, and a Day Conference Package including lunches (except in Davos) and refreshments. Accommodation is not included.


Upon firm registration and after we have taken the final GO decision, travel information, a hotel booking form, and an invoice will be sent. In case of cancellation, the fee will be refunded less a 15% Administration Charge if cancellation is made in writing no later than 10 days before course start. Full course fee will be charged after that date. Substitutions can be made any time before course start.

Elisabet Larsson received her M.Sc. Degree in Electrical Engineering from Linköping University of Technology, Sweden, in 1992. Before joining CEI-Europe in 2002, she was employed as validation engineer at the computer companies ICL Ltd. and Fujitsu, and later as project manager at the telecom company Ericsson AB in Sweden. She is currently Vice President and responsible for the development of tailored Corporate Exclusive Training Programs for our customers worldwide.

n a complex and ever-changing world, company survival may well depend on technological flexibility. How can a firm ensure that: • Its overall expertise is up-to-date? • The scientific potential for developing new viable products is inherent in the corporate environment? • There exists a corporate knowledge base that will enable productive discussion of ideas and their implementation? Perhaps your firm has a clearly-defined information gap that calls for submersion in the latest research of one or more technological spheres. Or perhaps you wish to upgrade the overall company expertise to avoid product stagnation. In either case, the need for corporate privacy will make a self-contained learning environment indispensable.


The solution may well be a corporate-exclusive course from CEIEurope. We can provide, in a closed venue, tailored courses to fit specific knowledge needs. The course can be held on your company’s premises or at an external sequestered site. A corporate-exclusive forum extends the advantages of continuing education.

Internal issues crucial to your business can be discussed freely.

Targeted Learning
The course can concentrate on existing knowledge gaps.

Corporate Conspectus
An often noted spin-off effect is the emergence of a corporate mind-set and with it, consensus on relevant goals and action plans. Contact CEI-Europe, Elisabet Larsson, CTO, for a detailed offer.

CEI-Europe • PO Box 910 • S-612 38 Finspong • Sweden • Phone +46 122 175 70 • Fax +46 122 143 47 • •


#13 Digital Imaging: Image Capturing, Image Sensors, Technologies and Applications #20 Advanced Image Sensor Technology #14 Digital Camera Systems #50 Digital Speech Transmission: Enhancement, Coding, and Error Concealment #11 Digital Signal Analysis Techniques: Time, Frequency, and Spatial Algorithms

Pages 4-8
4 5 6 7 8

#55 Signal Integrity: Advanced High-Speed Design and Characterization #70 High-Speed PCB Design for EMC and Signal Integrity #60 Grounding and Shielding: The Essence of EMC Design #56 Power Integrity: Advanced Design and Characterization

Pages 9-12
9 10 11 12

#12 Embedded Data Converters #10 RF and Microwave Filter Design with EM Simulation #19 RF and Microwave Circuit Design – Applications and Theory #07 Analog Signal Processing and Related Bipolar and CMOS Circuit Design #85 Phase Locked Loops for Wireless Communication Systems #86 RF Component and System Measurements #91 Applied Radio Design – System Architecture to PCB Implementation #57 Synchronization and Interconnect in Multi-Clock Domain System-on-Chips, SoC

Pages 13-20
13 14 15 16 17 18 19 20

#15 Design and Simulation of RF Systems #08 Advanced RF Power Amplifier Techniques for Modern Wireless and Microwave Systems #26 Radio System Design – Theory and Practice #06 Linearisation and Modelling Techniques for RF Power Amplifiers #27 Design of Advanced Radio System Architectures #90 RF Transceiver Architecture, System Design, and Evaluation for Wireless Systems

Pages 21-26
21 22 23 24 25 26


Pages 27-31
27 28 29 30 31

#64 Next Generation Networks: Broadband Infrastructure, ATM Switching, High-Speed LAN Systems #59 OFDM and MIMO Wireless Technologies with Applications to WiMax and UMTS LTE #46 MIMO and Beamforming for 4G Wireless with Applications to LTE and WiMax #41 3GPP LTE – The Future UMTS Standard #49 4G – Fourth Generation Wireless Networking

#21 Advanced Array Antennas: Conformal Arrays and Digital Beamforming #23 Satellite Communication Systems

Pages 32-33
32 33

#58 Modern Digital Modulation Techniques for Wireless, Satellite, and Wireline Communications #81 Modulation, Coding, and Iterative Techniques for Optimal Detection in Wireless Communications

Pages 34-35
34 35

#05 Advanced Lithography Technologies #37 Micro Fabrication Technology for MEMS and NEMS

Pages 36-37
36 37


Pages 38-46
38 40 41 42 43 44 45 46

#36 Silicon Device Technology: Materials and Processing Overview #87 Plasma-Assisted Etching and Reactive Ion Etching – High and Low Density Plasmas #88 Plasma Etching for CMOS Technology and ULSI Applications #75 Chip Interconnection Technology and Process Integration #95 Copper Low-k Interconnect Technology: Processing and Reliability of Cu Low-k Int. Metallization #16 CMOS/BiCMOS Process Integration and Engineering #62 Diagnosis, Debug, and Fault Isolation of VLSI Components and Systems #61 Yield and Reliability in VLSI Development and Manufacturing


CEI-Europe • PO Box 910 • S-612 38 Finspong • Sweden • Phone +46 122 175 70 • Fax +46 122 143 47 • •

Course 13

Image Capturing, Image Sensors, Technologies and Applications
May 25-29, 2009. Copenhagen, Denmark October 26-28, 2009. Barcelona, Spain Sensor Architectures
Finally, various types of sensor architectures and technologies will be treated. The dark characteristics of the imagers will be discussed, i.e. dark current and its dependence and dark fixed-pattern noise. An exercise will demonstrate these features.

If “A picture tells more than thousand words” then imaging , will be the language of the future. In today’s emerging markets of electronic equipment, imaging plays a very important role. The digital photography market has really taken off, replacing the classical silver-halide film by a solid-state image sensor. Video-conferencing, desktop video cameras and still-picture capturing means are becoming standard products as computer add-ons. Imaging is added to mobile phones and other devices. Solid-state image sensors replaced the classical tubes in the broadcast world and are doing the same in other professional application areas. Also, in the medical world, new surgery techniques become possible thanks to the powerful characteristics of the image sensors. New developments in CMOS semiconductor technology, next to the outstanding imaging performance of CCDs, open up new applications in the imaging arena.

Optical Characteristics
The second day lectures will deal with all kinds of optical characteristics of the imagers.

Delft University of Technology, The Netherlands

• Absorption of Photons • Light Sensitivity • Fill Factor • Quantum Efficiency • Micro-Lenses • Blooming • Electronic Shuttering • Smear • Sampling • Aliasing • MTF The latter will be studied in more detail by means of a practical exercise.

The major objective of this course is to make the participants familiar and experienced with solid-state imaging and the relevant related topics. It will give an in-depth view of the possibilities and limitations of the image capturing technology of today and tomorrow. Practical sessions will form a strong backbone of the course, complemented by several tutorial lectures.

Colour Imaging
Colour imaging is an important part of the course. We will focus on the following topics:
• Colour Imaging by Means of a Filter Wheel • Colour Imaging by Means of a Prism • Colour Imaging by Means of Colour Filters The latter can come in mosaic and in stripe configuration, in primary and in complementary colours.

The course is aimed at engineers, scientists and managers with basic knowledge, either theoretical or hands-on, in engineering or physics. No detailed knowledge of device physics is assumed. The course is developed to give an in-depth understanding of image capturing to engineers and technicians who are active in the field, and to give those with a theoretical knowledge the opportunity to learn more about the practical issues of the subject. Much of the course will be of interest also to camera designers through its practical approach. The program will provide managers and research workers having related experience in industrial, governmental or academic institutions with a valuable update on the latest developments in this fastmoving imaging subject.

Colour imaging is more than just colour filters. Colour matrixing and colour de-mosaicing are important techniques that we will discuss. An exercise on colour interpolation will make these various issues more clear.

Noise and The Dynamic Range
The most challenging topic of the course, noise and dynamic range, will be treated on the fourth day. To make the subject of noise more clear, all noise sources will first be discussed separately:
• Reset of Noise • Thermal Noise • Shot Noise • 1/f • Quantization of Noise • Fixed Noise • Noise Perception and the Use of Noise as a Measurement Tool • The Overall Noise Problem, i.e. the real situation when all the various noise sources come together.

Participants will receive a comprehensive set of course notes, including digests of the lectures and detailed notes on the practical work. These notes are for participants only and are not for sale. Bring your own calculator.

Noise is a dominant factor in the definition of the dynamic range. This will be explained further and demonstrated by means of an exercise.

Charged Coupled Devices
A large part of the first day will focus on the working principle of Charged-Coupled Devices (CCDs). Emphasis will be on the output amplifiers, on one-dimensional and two-dimensional image sensors. By means of computer animations, the basic working principle of the various architectures will be demonstrated. A practical exercise will make the participants familiar with the timing of a 2D imager.

The Imager in Real Life
All topics we have treated so far in this course will be incorporated into two main problems:
• How to Measure the Various Parameters of a Sensor • How to Analyse the Specifications of an Imager

CMOS Image Sensors
The second major subject will be on CMOS image sensors. Passive as well as active imager configurations will be discussed.

Finally, a live demonstration with a camera will summarize what we have learnt. Various sensor parameters and artifacts will be illustrated.


CEI-Europe • PO Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •

Course 20

March 30-31, 2009. Barcelona, Spain October 29-30, 2009. Barcelona, Spain Wide-Dynamic Range Pixels
Pixels are getting smaller and the specs on dynamic range are becoming tighter. What kind of architectures can be implemented to extend the dynamic range?

Highly sophisticated CMOS image sensors are key components of modern cameras. Technology as well as device architectures are optimized to obtain peak performance of the image sensor and the camera system. The most advanced CMOS image sensors show pixel sizes below 2 μm. The imagers demonstrate a light sensitivity comparable to that of the human eye. Another feature, the back-side illumination, is no longer limited to high-end professional applications. In addition, the modern camera systems can present a dynamic range of 100 dB or more. The equivalent noise level is in the range of sub-electron noise. Even if all these incredible features cannot be combined in one single CMOS image sensor simultaneously, they will allow for new technology breakthroughs and new imaging applications. Furthermore, the image sensor fabrication technology is not yet pushed to its ultimate limits. Image sensors make use of CMOS technologies that are lagging 2 or 3 generations behind those of digital integrated circuits or solid-state memories. Even more interesting developments can thus be expected in the near future. It has still to be proven that imagers can break the 1 μm barrier. Will imagers ever outperform the human eye as far as light sensitivity is concerned?

Back-Side Illumination
Backside illumination to obtain extremely high quantum efficiencies is becoming very popular. Several fabrication methods will be compared. A crucial part of the technology is the passivation of the backside of the sensors. The background of the passivation issues will be highlighted.

Delft University of Technology, The Netherlands

CMOS IMAGER SYSTEMS Noise on Pixel Level
At present, the pixels and the in-pixel circuitry are the limiting noise factors. From where is the remaining noise coming? What kind of new developments can be expected? Topics such as Transfer Gate noise, RTS noise and 1/f noise will be discussed.

This is a new advanced course focussing on the solid-state image sensor technology. It is intended for the specialists in the field. A very good background of digital imaging is needed to get the most out of this course. It can be regarded as a continuation of course #13 Digital Imaging: Image Capturing Image Sensors, Technologies and Applications. The content is based on comments, suggestions, and remarks received from previous participants in courses #13 and #14, Digital Camera Systems.

Noise on System Level
Noise can be used as an interesting measurement tool in the so-called Photon Transfer Curve method. Parameters such as conversion gain, dynamic range, saturation level, noise floor, quantum efficiency, and PRNU can be deduced. If the method is performed in darkness, dark current levels as well as DRNU can be measured. Further elaboration of the method will explain that this technique is not only a useful measurement tool but a diagnostic tool as well.

Electron Multiplication in CCDs

CMOS PIXELS Pinned Photodiode
What is new in CMOS image sensor pixels after the introduction of the pinned photodiode? The pinning layer created a real breakthrough in CMOS imaging, but does the pixel development stop with the pinned photodiode? An interesting concept to create very small pixels is the so-called shared pixel architecture, primarily based on pinned photodiodes as well. Advantages and disadvantages of the shared pixels will be discussed.

In case of extremely low light level, the EM-CCD is a very interesting and powerful image sensor. This device is characterized by the fact that an electron multiplication stage is included just before the output amplifier. In this way a gain can be applied to the signal in the CCD without amplifying the noise of the output stage. Equivalent noise levels of sub-electrons are being reported.

Global Shutter Pixels
The Rolling Shutter is still an issue in imagers that is being used for instance in broadcast, machine vision, and other applications. What are the alternatives in pixel design to turn the rolling shutter into a global shutter? Pixels with 4, 5, 6 and 7 transistors will be compared to each other.

CEI-Europe • PO Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •


Course 14

March 9-12, 2009. Davos, Switzerland September 28 – October 1, 2009. Cambridge, UK

Digital cameras are an essential part of our daily life, e.g. in mobile phones, camcorders and in imaging applications for medical, industrial and broadcasting industries. All these camera applications rely on the solid-state image sensors. However, if consumers were forced to choose a digital camera on the basis of the raw data produced by the imager, it would be very doubtful that anyone would buy a digital camera. The data produced by a solid-state image sensor is contaminated by various noise sources, by defects, by inconsistencies, and many other error sources.To make matters worse, the solid-state image sensors do not themselves produce a coloured image – it is the data processing that must correct all these potential errors and even regenerate the colour information in the postprocessing stage. So, what a person actually sees on a display or hard copy is absolutely not the same as what the imager has captured – “What you see is not what you got!” As we can foresee that our homes, offices and cars soon will be fully equipped with cameras to make life safer and more enjoyable and to reduce our workload, we can recognize the digital camera technique as a forefront technology. Even today, for many applications, imaging is in the embryo stage of its development.

Digital Camera Systems
• Dark Current Compensation: The average value of the dark current can be corrected by the use of dark-reference lines/pixels. Fixed-pattern noise can be corrected by means of dark frame subtraction. How efficient are these techniques ? What is their influence on signal-to-noise performance and what about temperature effects?

Delft University of Technology, The Netherlands

• Color Interpolation: The Bayer pattern sampling is extensively used in digital imaging, but the sampling is only half of the story. The other half is the demosaicing or interpolation. Several methods will be discussed and compared with each other.

• White Balancing: The human eye is adapting easily and quickly to the spectrum of a light source, the image sensors do not adapt at all! How can we deal with this “shortcoming” of the imagers? • Defect Correction: How can defect pixels be corrected without any visible effect? Can similar techniques also be applied to correct defect columns?

This course will focus on the overall system aspects of digital cameras. The complete path from “photons-in” to “digital-numbers-out” will be discussed. The effect of light sources, optics, imagers, defects, and data processing will be covered. Computer animations and simulations will be used to achieve a realistic understanding of details and shortcomings. Many examples of images will be used to explain the various details. No detailed knowledge of device physics is assumed. It is complementary and completely different from courses #13 and #20.

Digital Camera Systems (cont´d)
• Noise Filtering: A very important issue in data processing is the filtering of any remaining noise. This can be done in a non-adaptive or an adaptive way. What are the pros and cons of the various techniques? • Color Matrixing: Nobody is perfect, neither are the imagers that suffer from optical cross-talk and from imperfections when it comes to the transmission characteristics of the color filters. Color matrixing takes care about these issues. The question is: How do we find the optimum correction matrix coefficients? • Contouring: This is a technique to “regain” details, edges and sharpness in an image. But quite often not only the details are enhanced, but the noise in the image as well. Various contouring techniques will be discusses and compared with each other.

The Image Sensor, the Optics, Image Processing: A Review
The course begins with a brief overview of the basic theory of solidstate image sensors. The imager is of course only a small, but vital, component of the complete camera system. The effect of the spectral content of the light sources will be discussed. Lectures on optics and on digital image processing are included to form a strong backbone for the remaining parts of the course.

Digital Camera Systems (cont´d)
• Lens-Vignetting: Lenses have a strong fall-off of intensity and sharpness towards the edges. On top of that, also the image sensor will add an extra fall-off of intensity. Is correction possible? How complicated does the correction need to be to become invisible for the observer? • Auto-Focusing: How can the data of the image sensor itself be used to activate the auto-focusing function? • Auto-Exposure: How can the data of the image sensor be used to optimize the exposure time of the imager? • Gamma Correction: How do you adapt the brightness of the output device to the characteristics of the human eye?

Image Quality
Noise, defects, irregularities of the video signal, and inconsistencies can all deteriorate the quality of the image. We will discuss where these problems come from and how they can be corrected. The dilemma that correcting one effect can have a negative impact on some other camera parameters will be discussed.

Theoretical Calculations
The first day of the course will end with a few calculations: How many Volts-out will a camera deliver for a single photon-in? Bring your own calculator.

How to Measure the Various Camera Characteristics
The course ends with an extended chapter on how to measure the various parameters of a digital camera. This chapter will be used as a kind of wrap-up of the course and in the meantime, extra information will be provided on how to characterize the main characteristics of a digital camera and how they can influence each other.


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Course 50

Enhancement, Coding, and Error Concealment
May 25-28, 2009. Copenhagen, Denmark
tive multirate codec, Adaptive Multi-Rate (AMR), narrowband, wideband, and wideband+ for GSM and UMTS or variable rate coding for Internet telephony are explained. ITU: G.721/G.726, G.722, G.723, G.728, G.729, G.729.1, G.711.1, G.718 (EVVBR) GSM & UMTS: Full Rate, Half Rate, Enhanced Full Rate, AMR, AMR-WB, AMR-WB+

Digital signal processing technologies play an important role for the success of speech communication devices – be it mobile telephones, digital hearing aids, or human-machine interfaces. Within the evolution of systems, the improvement of the speech quality remains one of the most important objectives. The focus is on advanced signal processing algorithms, which help to mitigate physical and technological limitations. A comprehensive understanding of the fundamental issues, standards, and trends takes into account the specific conditions due to audio-bandwidth limitation, acoustic background noise, interfering acoustic echo signals, bit-rate restrictions, and residual transmission errors from the radio channel.


RWTH, Aachen

University, Germany Wireless speech transmission systems usually include channel coding for error protection. However, due to temporarily adverse channel conditions quite frequently residual bit errors remain. The negative effects of these errors can be reduced by error concealment. • Frame Substitution and Standard Solutions (GSM) • Soft-Bits and Log. Likelihood Values • Soft-Decision Speech Decoding by Parameter Estimation • A Priori Knowledge and A Posteriori Probabilities • Graceful Degradation by Soft Decoding • Joint and Iterative SourceChannel (De-) Coding • Audio Examples: PCM, ADPCM, GSM

The course covers theory and practice of signal processing algorithms, conversion of networks and terminals to 7 kHz wideband transmission not only by using true wide-band coding but also by artificial bandwidth extension of telephone speech: • Speech Coding Standards: ETSI, 3GPP, ITU • Error Concealment: Soft decoding and iterative source channel decoding • Bandwidth Extension: With and without side information • Noise Reduction: Single- and multi-microphone techniques • Acoustic Echo Cancellation: Time- and frequency-domain, adaptive postfiltering The course is based on “Digital Speech Transmission: Enhancement Coding and Error Concealment” by P. Vary and R. Martin, Wiley, 2006, and demonstrated by many audio examples.

In the long run, the audio bandwidth of the telephone networks and terminals will be extended to 7 kHz wideband transmission. This will require new codecs at both sides of the transmission link. Many terminals have not yet been equipped with the wideband capability. In this situation, the quality of the received narrowband speech (3.4 kHz) may be improved by means of artificial bandwidth extension:
• Source Filter Model • Extension of the Excitation Signal • Extension of the Spectral Envelope • Statistical Estimation Based on a Markov State Model • Bandwidth Extension with Side Information • Implementation and Performance Evaluation

The first part of the course deals with speech encoding. State-of-theart concepts are discussed. The signal processing aspects of quantization, differential waveform coding, linear prediction, and especially the concepts of Code Exited Linear Prediction (CELP) are explained.

If the signal is degraded by acoustic background noise and a loudspeaker signal, various speech enhancement methods can be applied prior to the speech encoding and transmission. We will discuss stateof-the-art algorithms for noise reduction and evaluate new proposals such as super-Gaussian speech models and psycho-acoustic aspects. Noise suppression schemes using only one single microphone or several microphones are presented.

Speech Production Model
• Speech Production • Digital Filter Structures • Psycho-Acoustics

Linear Prediction
• Vocal Tract Models and Short-Term Prediction • Optimum Prediction • Spectral Flatness Measure • Block-Adaptive Linear Prediction • Levinson/Durbin Algorithm • Long-Term Prediction

Single and Dual Channel Noise Reduction
• Wiener Filter • Speech Enhancement in the DFT Domain • Noise Estimation Techniques and Minimum Statistics • Sophisticated Suppression Rules • Conditional MMSE- and MAP-Estimation • Complex DFT-Coefficients • Real Valued DFT-Amplitudes • SuperGaussian Models • Noise Suppression Exploiting Masking • Soft Weighting • Dual Channel Noise Cancellation • Coherence Function and Theoretical Limits • Dual Channel Noise Suppression • Noise Suppression Using Small Microphone Arrays • Audio Examples

• Uniform and Non-Uniform Quantization • Optimal Quantization • Adaptive Quantization • Vector Quantization

Speech Coding
• Model-Based Predictive Coding • Adaptive Differential Pulse Code Modulation (ADPCM) • Noise Shaping Open Loop and Closed Loop Prediction • Code Excited Linear Prediction (CELP) • Quantization and Line Spectral Frequencies (LSF) • Audio Examples

Multi-channel Noise Reduction
• Spatial Sampling of Sound Fields • Beamforming • Performance Measures • Fixed Beamformers • Multi-Channel Wiener Filter and Postfilter • Adaptive Beamformers • Generalized Side-Lobe Canceller

Post Filtering
• Short-Term Post Filter • Long-Term Post Filter • Tilt Compensation

Speech Quality Assessment
• Mean Opinion Score (MOS) • Modulated Noise Reference Unit (MNRU, CCITT) • Objective Quality Measures (PESQ)

Key algorithms for hands-free communication are explained, especially for echo cancellation combine with adaptive post-filtering.
• LMS and NLMS Time Domain Cancellation • Convergence Analysis and Control • Echo Cancellation and Postfiltering • Joint Residual Echo Cancellation and Noise Reduction • Frequency Domain Method and Block Processing • Additional Measure • Stereophonic Acoustic Echo Control • Audio Examples

Speech Coding Standards
The most relevant speech codec standards are discussed and demonstrated by audio examples. Recent developments such as the adap-

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Course 11

Time, Frequency, and Spatial Algorithms
April 20-24, 2009. Barcelona, Spain September 28 – October 2, 2009. Cambridge, UK
We explore the basis for high performance via a systematic modelling viewpoint, and illustrate the performance with actual data.
• Parametric Time Series Models: Autoregressive (AR), Moving Average (MA), and Autoregressive Moving Average (ARMA) • Parameter Relationships among AR, MA, and ARMA Models • Autocorrelation Relationships among Parametric PROFESSOR Models • AR, Linear Prediction, and S. LAWRENCE MARPLE JR., Lattice Filters • Levinson-Durbin Oregon State University, Algorithm • Reflection Coefficients Corvallis, Oregon, USA • Maximum Entropy Analysis • ARMA Spectral Estimation • MA Spectral Estimation • AR Spectral Estimation: Yule-Walker algorithm, Burg algorithm, least squares linear prediction algorithms • AR Model Order Selection • Adaptive AR Spectral Analysis Algorithms: LMS and Fast RLS computational algorithms

Conventional tools for analyzing and extracting the feature content of signals are filters (time content), Fourier transforms (frequency content) and beamforming (spatial content). Alternative tools to these conventional techniques are able to produce signal analysis results with finer temporal detail and higher spectral and spatial resolution. This course goes beyond available textbooks and extends these signal analysis tools to higher dimensions and multiple sensor channels.

Practical implementation of the latest research approaches to time series and spectral analysis are introduced. The course uses a systematic approach based on a signal modelling theme, while focusing on fast computational procedures that make the alternative higher performance analysis techniques feasible to implement in practical applications. Of special focus are the extensions of fast computational algorithms for high performance signal analysis techniques to multichannel, multi-dimensional, and non-stationary instantaneous timefrequency analysis applications, where there is little published implementation literature. The first three days focus on one-dimensional data sources. The following two days cover data from multi-channel and two-dimensional sources, and single channel data with highly non-stationary features. Application examples using telecom, sonar, radar, seismic, and biomedical data have been incorporated into the course. Emerging signal processing techniques in modern time series and spectral analysis, including bandwidth extrapolation methods, non-stationary signal time-frequency analysis, and multi-resolution (wavelet-based analysis) analysis, will be covered. An extensive software toolbox (MATLAB and C) is provided for all the algorithms and computational techniques introduced.

Exponential Frequency Estimation and Min. Variance Spectra
Even higher performance for finding signal feature extraction is achieved using minimum variance and eigenanalysis approaches, at a computational cost increase. We explore the tradeoffs.
• Prony’s Method • Damped Exponential Parameter Estimation • Relationship to AR Methods • Least Squares Prony Algorithms • Noise Excision by Eigenanalysis/Principal Components Analysis • Minimum Variance Estimation: Derivation and relationship to AR spectral estimation, signal and noise subspace concepts • Pisarenko’s Technique • MUSIC Algorithm • ESPRIT Algorithm

Multi-Channel (MC) and Two-Dimensional (2D) Spectral Analysis
Some of the techniques discussed the first three days are extended to multi-channel (multiple sensors) and higher dimensional data situations. We cover many of the important extensions and show that higher estimation performance is achieved, sometimes with unexpected artifacts for which a user needs to be aware.
• MC Spectral Analysis: MC transform theory, MC random process theory • MC Classical Spectral Estimators • MC AR/MA/ ARMA Processes • MC Block-Levinson Algorithm • MC AR Spectral Estimators • MC Minimum Variance Spectral Analysis • 2D Spectral Analysis: 2D transform theory, 2D random process theory • 2D Minimum Variance Spectral Algorithm • 2D Autoregressive and Linear Prediction • Time Delay Estimation by Application of MC Analysis • Bandwidth Extrapolation via Linear Prediction Methods • Relationship of Temporal and Spatial Spectral Analysis Techniques • High Resolution Direction Finding and Beamformation

The expected background for students is some fundamental knowledge of Fourier transforms, basic digital signal processing (filters, convolution, Fast Fourier Transform (FFT), basic matrix mathematical operations (matrix inverse, eigenvectors), and introductory random signals (correlation, spectral density). The first day reviews these topics to introduce notation and basic concepts. Some experience applying time and frequency domain techniques to signals would be helpful. This course provides alternative time and frequency domain analysis techniques. A number of data cases are used to demonstrate the practical use of the theoretical concepts.

Signal Analysis Tools and Classical Spectral Analysis
The first day reviews all the relevant concepts of traditional temporal and frequency domain analysis of signals. We will establish some important concepts for the advanced alternative temporal and frequency (spectral) techniques covered in sequel course days.
• Complex Signal Representations • Analytic Signals • Matched Filters • Issues in Spectral Estimation • Concepts from Fourier Transform Theory • Tutorial Review: Random Signal Theory • Tutorial Review: Matrix Algebra Theory • Resolution and Time-Bandwidth Uncertainty Principle • Autocorrelation and Cross Correlation • Power Spectral Density • Window Selection • Correlogram Method • Periodogram Method • Blackman-Tukey Method

Non-Stationary Time-Frequency Analysis (TFA)
Some additional performance tradeoffs and issues concerning nonstationary (time-varying) signal analysis will be summarized, again using actual data to illustrate the tradeoffs.
• Time-Recursive AR Estimation • Short Time Fourier Transform • Linear and Quadratic Time-Frequency Representations • Short Time Fourier Transform (STFT) • Wigner-Ville Distribution • 2D Methods of TFA • Ambiguity Functions in TFAs

Parametric and Autoregressive Methods
The most successful high performance analysis approach is based on autoregressive and linear prediction modelling and estimation.

Multi-Resolution and Deconvolution Analysis
• Alternative Multi-Resolution Basis Functions to Fourier Transform Frequency Representation • Scaling (time compression/time expansion) Properties of Analyzing Wavelets for Time-Frequency Analysis • Scalograms vs Time-Frequency Grams • Time Domain, Least Squares, and Frequency Domain Deconvolution Techniques


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Course 55

May 25-29, 2009. Copenhagen, Denmark

High-speed designs continue to undergo major technology changes. In recent years, parallel signaling rates exceed 1000 Mbps and main-stream serial signaling is in the 5-10 Gbps range; signal rise and fall times shrink to way below 100 ps. As a result, interconnect losses, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be understood and taken into account during the design process. With the increasing utilization of transmit and receive equalizations, validation even with eye diagrams may not be sufficient in itself. Today, equally challenging is the proper design of power distribution. A multitude of supply voltages and signaling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects eventually link the previously independent power-integrity, signal-integrity and EMC design domains.

Single and Multiple Unloaded Interconnects
• Signal Spectrum, Time and FrequencyDomain Solutions • Characteristic Impedance, Delay and Performance Regions of Interconnects • Matching and Termination Solutions and DR. ISTVÁN NOVÁK Rules; Allowable Mismatch SUN Microsystems Inc., • Time and Frequency Domain Solutions, Boston, USA Network Matrices • Crosstalk and Crosstalk-Reduction in Time and Frequency Domains • PCB Construction Rules, Stackup Options and Limitations Example: Calculation of Interconnect Parameters, Reflection, Matching

Differential, Multi-Line and Lossy Interconnects
• Differential Interconnects, Effects of Imbalance, Mixed-Mode S Parameters, Mode Conversion • Multi-Line Crosstalk, Simultaneous Switching Noise • Multi-Drop and Point-to-Point Interconnect Characteristics • Skin Loss, Dielectric Loss, Surface Roughness • Discontinuities, Through Holes and Vias, Bends, Stubs Example: Via Construction and Characteristics

This renewed course uses a series of dedicated HW and software illustrations and design examples to show and explain major rules of proper signal-integrity design. The class focuses on signal integrity in board and system interconnects with the necessary brief overview of power-integrity and EMC design principles. Detailed power-integrity design and validation is covered in the companion course #56, ”Power Integrity: Advanced Design and Characterization” . The HW and SW illustrations are shown live during the class. The teaching methodology is based on showing and explaining good and bad design choices, discussing pros and cons of options and focusing on manufacturability and robust performance. The course is taught with minimal mathematics, relying on the physical phenomena and a few easy-to-remember basic rules. For highspeed signal transmission, emphasis is put on the dispersive and lossy nature of cables, PCB and package traces, showing the link between rise-time degradation, jitter, eye closure and the frequency-domain scattering and transfer parameters. For power distribution and EMC, emphasis is put on the proper impedance profile of the bypass network and how to estimate and compare the worst-case transient noise of various design methodologies. Case studies and exercises make the learning experience complete. Participants will receive several of the tools and simulation files shown in the class.

Clock and Signal Distribution
• Grounding, Shielding and EMI Rules • Clock Sources and Drivers, Clock PLLs, Spread-spectrum Clock • Clock Distribution, Skew, Jitter • Jitter Tolerance and Jitter Transfer • ISI, Eye Diagram, Peak Distortion Analysis, Linear Network Solutions Example: Anatomy of the Clock-Network Resonance

System Design
• Parasitics of RLC Components, Integrated Passives • Cascading High-Speed Interconnect Building Blocks • Component Placement, Stackup and Layout Optimization • Design of Power Distribution Networks for High-Speed Systems • Power Distribution Vias, Planes, Bypass Capacitors Example: Robust Power Distribution Design

Simulation, Measurement, Validation
• Rules for Creating and Validating Simulation Models • Rules to Select Simulation Tools, Settings and Setups • Signal-Integrity and Power-Integrity Simulations • Selecting Probes, Cables and Instruments for Signal-Integrity Measurements • Characterization and Validation of High-Speed Systems Example: Anatomy of Simulation Accuracy

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Course 70

April 20-24, 2009. Barcelona, Spain October 12-16, 2009. Copenhagen, Denmark Reflections and Impedance Mismatch on High-Speed Digital PCBs
We now focus on the treatment of signal traces, transmission lines, and the implication of the concept to PCB design. Impedance mismatch, leading to reflections and noise are discussed in detail, and design approaches, including impedance matching, source and load termination topologies are presented. The concept of “S-Parameters” for circuit analysis will also be presented.

All EMI problems begin and end on the Printed Circuit Board. In recent years, PCBs have become increasingly complex. The use of high density VLSI on the one hand, combined with the increased processing speed and data rates, have led to the increased density of the circuits. The use of high speed/high edge rate digital circuits, along with the need for low power consumption, have contributed to higher electromagnetic emissions from circuits, on the one hand, and increased sensitivity of the circuits on the other, leading to Electromagnetic Interference (EMI) problems. A special problem is that of Signal Integrity (SI). For the adequate control of EMI, strict international standards and regulations have been developed worldwide. These standards require the suppression of electromagnetic emissions from circuits and systems, and their increased immunity to externally induced interference. The proper design of PCBs is a cost effective approach for the control of EMI in high-speed circuits.

K.T.M. Project Engineering Ltd., Kfar-Sava, Israel

Crosstalk on the PCB
The concept of crosstalk on PCB as a primary source of EMI concerns and failures is discussed. Approaches for minimizing crosstalk, with particular emphasis of routing guidelines, are presented in detail.

PCB Design for EMC

This is a design course, dealing with the theory and design of PCBs for meeting EMC and SI objectives. The course features understanding of the electromagnetic phenomena in PCBs, and in particular in high-speed digital PCBs. The course emphasizes practical applications, with mathematical derivations kept to the minimum necessary. In addition, case studies and practical “real life” examples will be provided.

Strategies for a systematic design approach of PCBs from the standpoint of EMC and SI includes such design features as layout, layer stacking, placement, power distribution and grounding/reference systems.

Treatment of Mixed (Analog/Digital) Circuits
The problem of mixed analog/digital circuits is presented. The discussion covers the problem of ADC and DAC devices, and circuit design with one or multiple devices on one and on multiple PCBs.

Introduction – Why Design for EMC and SI?
We will discuss the concepts of EMC and SI and describe the similarities and differences between the two as they pertain to circuit design and the primary parameters that govern interference modes and system performance with respect to EMC and SI.

Clock Circuits
The special problems associated with clock circuits and clock signal distribution, including classical and novel approaches for clock circuit design, are discussed.

Noise Sources on PCBs
The characteristics of noise sources on PCBs will be discussed, with particular emphasis on noise in signal, power and ground circuits. Coupling and interaction between circuits, particularly crosstalk, will be discussed in detail.

Treatment of Special Signals in PCB Design
Some commonly used digital interfaces, such as LVDS circuit design, are given particular attention.

Shielding on PCBs
Implementation of shielding as an EMI control measure, particularly on PCBs, is discussed here.

Circuit Elements
Characteristics of real world circuit elements, with special emphasis on parasitic inductance, capacitance and resistance will be discussed.

Edge Connectors
Improper design of edge connectors may cause an otherwise good design to fail both EMC and SI objectives. We will discuss the proper design of edge connectors consistent with circuit design with special emphasis on high-speed interfaces. Items covered include pin allocation, layout of power, ground pins, and the connector arrangement.

Fundamentals of Grounding Design
The concept of grounding and basics of grounding system designs will be presented. Design of the grounding tree and identification and elimination of ground loops will be discussed in detail. Application of the fundamental grounding theory to grounding on PCBs will be presented.

PCB Layout Guidelines
A verification checklist for PCB layout guidelines for EMC and SI will be presented.

Power Circuit Designs on PCBs
A discussion of the interaction via the power system on the PCB will lead to the concept of decoupling, classical and innovative decoupling strategies, filtering, and filter design for EMI control. In particular, the generation of Parallel Plate Waveguide Noise shall be discussed. Novel techniques for addressing "Ground Bounce" or ΔI Noise and its mitigation such as Electromagnetic Band Gap (EBG) will also be presented.

Measurement Fundamentals
EMC measurements, particularly the use of spectrum analyzers and oscilloscopes for observing system performance, will be discussed.

Questions, examples presented by the participants, and practical EMC and SI problems on PCBs will be treated in an interactive manner.


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Course 60

March 30 – April 2, 2009. Barcelona, Spain

The discipline of Electromagnetic Compatibility (EMC) is concerned with the design of Electronic Systems, while minimizing electromagnetic coupling and interference from within the system and between systems to their environment. Meeting the strict EMC standards, as well as ensuring the satisfactory performance of the equipment in its intended electromagnetic environment, requires the implementation of technical measures into the system’s design. Grounding forms an inseparable part of all electronic and electrical designs, from circuit through system up to installation design. Grounding is implemented for EMC and ESD protection, for safety purposes, for lightning and surge protection. Shielding, on the other hand, is a necessity for avoiding electromagnetic field coupling from and into equipment enclosure. Adequate shielding is necessary to enhance immunity of equipment, and reduce emissions from the equipment enclosure. Grounding and shielding are two of the essential concepts in EMC design. No design will be acceptable without them being properly implemented.

Ground-Loop Interaction and Coupling (GLIC)
• Concepts (and myths) associated with “ground loops” • Common to differential mode conversion phenomenon, consequent of ground loops • Mitigation techniques of ground loop generated interference such as isolation transformer, Baluns, optocouplers, and other

K.T.M. Project Engineering Ltd., Kfar-Sava, Israel

Equipment and System-Level Grounding

• Dilemma associated with interconnects between large scale systems and installations • Application of the fundamental grounding theory to different tiers of equipment and systems • Interconnection of multiple ground connections

Implementation of Grounding on Printed Circuit Boards
• Objectives of grounding on PCBs, including those of signal current return and signal reference • Implementation of grounding for each of the objectives • Concepts of power distribution and transmission line signal propagation on PCBs and the role of the grounding system in their implementation • Mixed analog/digital circuits and approaches for grounding to be applied, particularly when analogto-digital (A/D) and digital-to-analog (D/A) converters are incorporated in the circuit • Special considerations of grounding in PCBs, including moats and ground fills and chassis stitching

This is an advanced design course, dealing with the theory and practices of grounding and shielding for meeting EMC objectives. The course features understanding of the electromagnetic phenomena related to electronic equipment and system-level grounding and shielding. The course covers grounding and its topologies, leading to the implementation of grounding from circuit to system. With respect to shielding, the course will cover issues such as the shielding properties of metals, and the compromises in shielding, which are the main objective of shield design. Case studies and practical “real life” examples will be provided.

Cable Shielding and Shield Transformation
• Basics of field to cable interaction and one of the solutions, in the form of cable shielding • “How should the cable shield be grounded, at one or both ends?” • A comparison of signal circuit wiring grounding vs. shield grounding, and the fundamental difference between the two

• Manner of achieving high-quality electrical connection • Bonding as a link between grounding and shielding, and techniques for achieving acceptable bonds • Dissimilar metals and metal electrochemical compatibility between bonded structures • Manner for corrosion control

Fundamental Concepts
• Basic concepts of EMI phenomena and EMC and the primary parameters that govern interference modes and system performance with respect to EMC • A video presentation, “EMI: The Silent Threat”

Fundamental Shielding Theory
• Fundamentals of equipment shielding and mechanisms contributing to the shielding effectiveness of an enclosure • Significance, limitations and the factors contributing to reflection and absorption mechanisms • Unique approaches to shielding against low-frequency magnetic fields

Signals and Coupling Modes
• Characteristics of signals, in particular their spectral content • Concepts of common-mode vs. differential-mode signals, particularly with their effect of EMI interactions • Fundamental field concepts, with special emphasis on magnetic field interactions • Manner of signal propagation in circuits and systems • Concept whereby current follows the “path of least impedance” and the implications of this concept • Transmission line fundamentals and frequency considerations

Shield Discontinuities and Their Treatment
• Effects of discontinuities in shielding materials, and solutions to aperture and slot leakage • EMI gaskets and their application

Circuit Elements
• Characteristics of real world circuit elements, with special emphasis on parasitic inductance, capacitance and resistance

Equipment and System Shielding Design
• Implementation of shielding to equipment • External and internal (partitioning) shielding • Application of shielding at the equipment rack and console levels • Implementation of shielding on the PCBs (“shield cans”)

Fundamentals of Grounding Design
• Concept of grounding, and basics of grounding system designs • Reasons and rationale for grounding and conflicts between rounding and other system requirements, e.g., safety considerations

Shield Integrity Violations
• Manners of undesirable, yet common, violations of the shielding integrity, including shield penetrations and discontinuities • Manners and materials available for preclusion of such violations

Grounding Essentials
• Fundamental grounding topologies • Structured methodology for the design of the grounding tree

Grounding and Shielding Related Case Studies
• Real-life grounding and shielding case studies The participants will also be encouraged to share their own case studies at this time.

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Course 56

October 26-30, 2009. Barcelona, Spain

One of the biggest design challenges today is to properly design, manufacture, simulate and validate a Power Distribution Network (PDN) in systems with increasing speed, power dissipation and density. A multitude of supply voltages and signaling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects link the previously independent power-integrity, signal-integrity and Electro-Magnetic Compatibility (EMC) design domains. Eventually, the power distribution design and characterization becomes a corner stone and enabler for good signal integrity and electromagnetic compatibility.

Interaction of Power Integrity, Signal Integrity and Electromagnetic Compatibility
• Waveforms and Spectra of High-Speed Signals and Power Noise • Interaction of Power Integrity, Signal Integrity and Electromagnetic Compatibility DR. ISTVÁN NOVÁK • Grounding and Shielding Rules SUN Microsystems Inc., • PCB Construction Rules Boston, USA • Unified PDN and SI Design: Linear Network Analysis • Impulse and Step Responses, Calculating Worst-Case Noise Examples: How to Avoid Typical Pitfalls in Frequency to Time-Domain Conversion

This new five-day course is devoted entirely to power distribution design and characterization with the necessary brief overview of signalintegrity and electromagnetic compatibility principles. Detailed signal-integrity design and validation is covered in the companion course #55; Signal Integrity: Advanced High-Speed Design and Characterization. The course is based on a large number of HW and SW illustrations, shown live during the class. The teaching methodology is based on showing and explaining good and bad design choices, discussing pros and cons of options and focusing on manufacturability and robust performance. It is taught with minimal mathematics, focusing on the physical phenomena and a few easy-to-remember basic rules. The course explains the underlying physical rules for successful power distribution designs and shows how the same simple principles, which can be used to obtain worst-case eye-diagrams in signalling, can also be used to efficiently calculate the worst-case transient noise on power-distribution networks. In the design process, emphasis is put on the proper impedance profile of the bypass network and how to use the impedance profile to estimate and evaluate the worst-case transient noise of various design methodologies. The class answers (among others) such important questions as how stackup and layout details matter for power distribution, how many and what value of bypass capacitors we need, and where to place bypass capacitors for effective noise suppression. In characterization, equal time is devoted to simulations and measurements. In simulations, different modelling techniques and tools are shown for simulating components, power planes and vias. In measurements, the possible time-domain and frequency-domain instruments are reviewed and the proper set-ups, connections and calibrations are discussed. Participants will receive several of the tools and simulation files shown in the class.

Power Distribution Components
• DC-DC Converter Properties, Selection, Placement • Characteristics and Parasitics of Various Bypass Capacitor Types • Characteristics and Parasitics of Various Decoupling Inductor Types • Characteristics and Design of Vias and Planes • Designing Filters For Low-Current Circuits (Serdes, PLL, Vref) Examples: DC-DC Converter Stability

Power Distribution Design Methodologies
• Choosing the Proper Geometry for DC Power Distribution • Determining Trace Width for Supply Feeds • High Frequency Bypassing with Power-Ground Laminates, Stackup Selection, • Split Planes and Signal Routing over Splits • The Procedure of PDN Design; Determining Target Impedance Examples: Anatomy of PDN Resonances, PCB Stackup Analysis for PDN

Component Selection and Placement through Simulations
• Synthesizing PDN Impedance: Multi-Pole, Big-V, DMB Approaches • High-Frequency PDN Design, Service Radius of Bypass Capacitors vs. Matched Planes • How to Identify and Eliminate Capacitor-Capacitor and CapacitorPlane Anti-Resonances • Spreadsheet and SPICE PDN Simulations Examples: Simulation of Bypass Capacitor Service Area

Design and Validation of Power Distribution Networks through Measurements
• Frequency-Domain Measurement Set-Ups: Two-Port Shunt-Through Connections • Probes, Connections and Calibrations in the Frequency Domain • Why We Should Not Measure Noise across Bypass Capacitors • Time-Domain Measurement Challenges: Uncorrelated External Noise, Dynamic-Range Limitations Examples: How to Reliably Measure Very Low Impedance Values


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Course 12

March 9-12, 2009. Davos, Switzerland September 28 – October 1, 2009. Cambridge, UK

Powerful digital signal processing has been the key enabler of many technological breakthroughs during the last decades. Socalled ‘digital’ communications brought us a worldwide wireless communications network and high-speed wireline Internet access. Processor based mechatronical systems have increased efficiency, reduced waste, and raised security in nearly every application you may think of. The interface between the “analogue” environment and the digital signal processing is the data converter. Steadily increasing resolution and bandwidth of the A-to-D and D-to-A converters, at no additional area or power consumption, were the other key enablers of this progress. Following the trend to ever-higher integration levels today most data converters are embedded in a System-on-Chip together with a selection of RF, analog, and digital blocks, complete DSPs, Ps, or even MEMS. This defines another paradigm change, posing new chances and new challenges to the concept engineers and to the designers – now they have a complete system in their hands, with all chances for optimization, but also with the need to understand the complete system as well as the tradeoffs between the various blocks and solutions.

During the second day, we will first cover Nyquist type ADCs, studying power and/or area efficient implementations. Then figures of merit will be introduced. Derived by statistical evaluation of a large database, graphs will clearly show trends, application ranges and tradeoffs of the various ADC concepts. We will also cover DAC architectures and implementations and end the day with the basics of ΣΔ-converters.

Innovations Manager, Infineon, Munich, Germany

Efficient A-to-D Converter Concepts
• Algorithmic • Successive Approximation • Slope • Asynchronous

D-to-A Converter Concepts
• Basics • Resistor Based • Switched Capacitor • Switched Current • Figures of Merit, Some Statistics

Oversampling and Noise Shaping Converters
• Delta Modulator • Sigma-Delta ADCs: Basic concept and linear model • Single Loop, Single Bit • Higher Order • Multi-Bit • Feedback versus Feedforward Architecture • Stability for Bounded and Unbounded Inputs

This is the revised and extended version of the course ‘System Based Approach to Data Converter Design’. The objective is to teach what is necessary to select and to design the most suitable data converter under consideration of system aspects and tradeoffs. To this end, we will brush up the basics of sampling, quantization, and Fourier transforms. We will look into a complete signal processing chain, discuss tradeoffs and show how to derive the requirements for the ADC. We will talk about noise, matching, and layouts issues. Based on figures of merit and a large database the application ranges and performance limits for the various converter architectures are investigated. And, of course, we will spend most of the time understanding the basic concepts as well as the practical aspects of the relevant converter architectures. Time encoding, i.e. replacing voltage levels by quantization along the time axis, will be introduced. Finally Sigma-Delta Modulators, as the workhorse of communication ICs, will get extensive treatment. A practical example concludes the course.

The third day will continue with ΣΔ-converters, discussing some complex implementations and some unusual applications. Aspects of modelling, design flow, and a look into Schreier’s toolbox for synthesis and simulation conclude ΣΔ-converters. We will finish our examination of data converters by discussing the basic concept and implementations of time encoding converters.

Sigma-Delta Converters
• Unusual SDM Applications • Bandpass and Complex SDM • Cascaded (MASH) • Continuous Time vs. Discrete Time • Modelling, Design Flow • Schreier’s Toolbox • PDM-Filter

Time Encoding
• Basics, PDM and PWM Signals • Sigma-Delta DACs • PWM Signal Generation - Class D Amplifiers • Time-to-Digital Converter (TDC)

This course is aimed at system and concept engineers who need to better know the role of the data converter in a system, the choices, the chances and the limitations. It also targets design engineers who wish not only to understand the theoretical and the practical aspects of the different converter topologies but also to get a view beyond the converter. Pre-requisites for the course are a basic understanding of semiconductor circuits and blocks together with some (limited) knowledge of analog circuit design.

The last day will start with an introduction to analog filters and some basic topologies. The need and the methods of filter tuning to overcome PVT variations will be introduced. With this knowledge we can take another look into the signal processing chain from source to ADC, discuss tradeoffs and describe a method to derive the ADC specification. Finally some very practical aspects like design for noise, matching, and layout issues will conclude this course.


During the first day we will learn applications of data converters, brush up some theoretical background, learn the basic concepts and definitions underlying A-to-D conversion, and start looking into highspeed A-to-D converters.

• Filter Characteristics • Filter Implementation, Active Biquads • Tuning

System Tradoffs
• VGA-Filter-Converter – how do I partition my system?

Building Blocks
• Voltage references• Noise and Noise Reduction • Chopper • Correlated Double Sampling • I/O stages

Applications and Theory of Data Converters
• General Systems • Wireless Communications Systems • Sampling • Aliasing • Quantization • Discrete Fourier Transform

Layout Aspects
• Matching • Crosstalk • Reference Routing • Package Effects

High Speed A-to-D Converter Concepts
• Definitions and Error Mechanisms • Flash • Two-Step and Sub-ranging • Folding • Time Interleaved • Pipelined

Practical Example
• Selection and Top Level Sizing of a Sigma-Delta Converter

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Course 10

March 10-13, 2009. Davos, Switzerland October 13-16, 2009. Copenhagen, Denmark

Filters are one of the fundamental building blocks of RF and microwave systems, along with amplifiers, oscillators, mixers, and switches. Filter design and realization can be challenging for several reasons. No one technology or filter topology is suitable for all applications. There is also a fundamental limitation imposed by the relationship between unloaded Q and volume. Many of the simpler design procedures can sometimes arrive at geometries that are unrealizable, and the available literature is generally focused on theory rather than practical information on realization. However, with a few basic concepts in hand, even the non-specialist can achieve useful results. Electro-Magnetic (EM) simulation is also an essential component of modern filter design. We now have the ability to model and optimize complete filter structures in the EM domain. Current developments in cluster computing and multi-threading promise to enhance those capabilities as well.

Narrow Band Filter Design and EM Simulation
Our approach to narrow band filter design starts with Dishal’s method and moves a step beyond with port tuning of a full EM model. The port tuned model is a virtual prototype that can be diagnosed and op- DANIEL G. SWANSON, JR. timized before any hardware is built. ModCobham Microwave ern TEM filters often employ cascade Systems, MA, USA triplets and quads to realize transmission zeros in the stopband or flatten group delay in the passband. These filters can also be designed using our approach. At some point, practical procedures are needed to measure unloaded Q, external Q, and coupling coefficients. Systematic methods for tuning filters are also needed. All of these methods and procedures can be applied to actual hardware or to an EM simulation of the hardware.
• Narrow Band Filter Design • EM Filter Prototypes • Cascade Triplets and Quads • Unloaded Q • External Q • Coupling Coefficients • Filter Tuning

This course is devoted to the fundamentals of practical filter design for RF and microwave systems. The core material is a universal procedure for narrow band filter design that can be applied to virtually any filter technology or topology. The procedure is rooted in Dishal’s method with powerful extensions that include the port tuning concept, equal ripple optimization techniques, and efficient EM simulation. All the techniques presented can be implemented using commercially available CAD tools. Practical procedures for extracting unloaded Q, external Q, and coupling coefficients are quite important in the design process and in evaluating prototypes. These techniques will include extracting data from hardware and from EM simulations. Some tutorial material on field-solvers will also be presented. The EM simulation examples relate specifically to filter design and include tips and techniques for more accurate and efficient simulation. Example filter designs that cover a broad range of commercial and military applications will be presented with measured data and error analysis. The instructor will choose examples to develop based on the interests of the class. The course material is suitable for filter designers, designers of other components, systems engineers, and technical managers.

Designing Combline, Waveguide, DR Filters, and Diplexers
When higher unloaded Q is required, designers often turn to cavity combline, waveguide, or dielectric resonator (DR) filters. Combline and DR filters are now used in high volumes in cell phone base stations. Meeting customer requirements often requires additional transmission zeros in the stopbands, which are realized using various types of cross-couplings. Both narrow band and broadband combline filters can be found in many military systems. Some applications also call for these high performance filters to be diplexed or multiplexed. Again, strategies for efficient design and EM simulation will be discussed for all the topologies presented.
• Cavity Combline • Waveguide • Dielectric Resonator • Base Station Filters • Diplexers and Multiplexers • Strategies for Design and EM Simulation

Filter Design, Optimization, and Port Tuning
We will present the briefest possible introduction to basic filter design concepts. Starting with lowpass prototypes, we will touch on Chebyshev and elliptic prototypes and finding prototype element values. Next we will turn to a brief overview of the most common filter design techniques. Topics will include synthesis from an insertion or return loss function, the coupling matrix approach, and synthesis by optimization. The use of general purpose linear simulators for equalripple optimization will also be discussed. Finally, we will introduce the port tuning concept.
• Basic Filter Concepts • Chebyshev and Elliptic Prototypes • Synthesis From Insertion Loss Functions • Coupling Matrix Approach • Synthesis by Optimization • Equal-ripple Optimization • The Port Tuning Concept

Designing Planar Filters
Filters in planar form can be built using several different topologies and technologies. Various single and multilayer ceramic and soft substrate (PCB) technologies are available to the filter designer. We will cover the more common distributed topologies including edge-coupled, hairpin, and interdigital. More recent coupled and cross-coupled loop topologies will also be presented. At lower microwave frequencies a pseudo-lumped approach using printed inductors and capacitors is more space efficient. Lowpass, elliptic lowpass, and bandpass filters using this approach will be presented. Strategies for efficient design and EM simulation will be discussed for all the topologies presented.
• Planar Filters • Single and Multilayer • Ceramic and PCB • Edge-coupled, Hairpin, and Interdigital • Coupled and Cross-coupled Loops • Pseudo-lumped Lowpass and Bandpass • Strategies for Design and EM Simulation


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Course 19

May 25-29, 2009. Copenhagen, Denmark October 26-30, 2009. Barcelona, Spain

Although RF circuits are generally considered to be circuits that operate from tens of MHz up to 1GHz, and microwave circuits at frequencies beyond that, boundaries based purely on frequency are rarely appropriate. Analog integrated circuits based on lower-frequency design methodologies can now operate well into the microwave range, purely because of smaller feature sizes that are now available in CMOS and silicon-germanium technologies. BiCMOS integrated circuits that operate in the microwave frequency range, designed using low frequency architectures, are now abundant. However, microwave circuit design techniques are still important to model and understand problems arising from noise, mismatch, circuit losses, and limited bandwidth. We will focus on circuits that are differentiated from their historically lowerfrequency counterparts by several features. In RF and microwave design, the phase shift of the component is significant because its size is comparable with a wavelength, its reactances and parasitics must be accounted for, and reflections occur between elements. We need to consider circuit losses that degrade the Q of an element as well as introduce noise, and nonlinearities that introduce distortion into the signal path. Electromagnetic radiation and capacitive coupling will also be features of such circuits. With integrated circuits, these ‘RF and microwave’ effects are most commonly observed when assembling circuits together at higher frequencies into systems, or when using discrete or custom devices.

Small-Signal RF Circuit Design
To introduce linear active circuits, we start with the fundamental principles of impedance matching and move on to examine the effect of mismatch on performance.
• Revision of S-parameters, Matching and DR. ROWAN GILMORE the Smith Chart • Unilateral Gain Circles in University of Queensland Small-Signal Amplifier Design • Unilateral and Australian Institute and Figure-of-Merit and Bilateral Design for Commercialisation, • RF Circuit Stability: Graphical and analytiBrisbane, Australia cal techniques • K- and μ-Factors, Nyquist Stability Analysis Example: Broadband Transistor Stabilization • Stability of Cascaded Amplifiers • DC Bias Circuits • Simultaneous Conjugate Match, Bandwidth Considerations • GMAX and MSG Definition Example: 1900MHz Amplifier Design for Maximum Gain

Discrete Low-Noise and Broadband Amplifiers
We examine the three commonly used techniques used in maximum small-signal gain, low-noise, and linear power amplifiers.
• Amplifier Design Alternatives: Low-noise vs. maximum output power • Transducer-, Operating-, and Available-Gain Techniques • RF Noise Sources, Noise Figure and Noise Measure • Constant-Noise and Constant-Gain Circles in LNA Design • Available-Gain Design for Minimum Noise • Trade-Offs Between Gain, Match, and Noise Performance Example: 900MHz LNA Design • Broadband Amplifier Design Techniques • Reactive Mismatch and Lossy Matching Techniques • Cascade Equalization • Feedback Amplifiers Combined with Impedance Matching • Circuit Optimization for Gain, Match and Stability • Feedback Effects on Stability and Noise Example: 1-4000 MHz Feedback Amplifier Design

This course reflects modern trends. While focusing on the design of discrete RF and microwave circuits to show classical microwave design techniques, examples of integrated circuits are presented to compare the ‘two worlds’. Impedance matching, device modelling, circuit stability, biasing, power output, distortion, power combining, and component losses and parasitics are all examined, using state-of-the-art low-voltage transistors. This is illustrated in a number of applications such as smallsignal, large-signal, low-noise, and feedback amplifiers with discrete transistors. Low-noise design considerations are also introduced, using CAD modelling of reactive and resistive types of applications. Reflecting its importance as a fundamental building block of most systems, amplifier design is treated exhaustively. Oscillators and mixers are also designed to meet demanding systems requirements. We stress the importance of modeling parasitic elements that arise in design or when interconnecting components at high frequencies. Nonlinear design techniques are examined using a harmonic balance simulator, with bipolar, FET, and HEMT devices. The course emphasises hands-on design and simulation of many circuit types, considering their linearity, efficiency, and power requirements. Many examples are related to telecommunications circuits in the 950 MHz to 5 GHz frequency range. Interactive circuit simulation techniques are used throughout to simulate parasitic and layout effects on circuit performance. To benefit most, bring your own laptop computer, and prior to attending the course, obtain a free trial license of Microwave Office (MWO) from Applied Wave Research at

Power Amplifier Design
• Design for Optimal Power • Quasi-Linear Methods to Achieve Power Matching • Load Line Characterization • Load Pull Characterization – Measurement and Prediction • Classes of Power Amplifiers: A, AB, B, C, and F • Harmonic Tuning to Optimize Efficiency

Power Amplifier Design (cont’d)
• Distortion Reduction Techniques Example: Bipolar Power Amplifier Design (CDMA)

Low Noise (LC) Oscillators
• Oscillator Design Considerations • Device – Circuit Interaction (Series and Shunt Resonances) • Deriving the VCO Tuning Curve • Phase Noise and Its Impact on System Performance

Low Noise (LC) Oscillators (cont’d)
Example: Bipolar Transistor (HBT) VCO Design in the 4 GHz Band

Mixer Design
• Revision of Diode Mixers • Bipolar and MESFET Mixer Analysis • Comparison of Mixer Types • The Importance of Quadrature Balance • Modulators and Image-Reject Mixers Example: FET and Bipolar Transistor Active Mixer Designs

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Course 07

June 8-12, 2009. Cambridge, UK Analysis and Design of Sampled-Data Circuits
• The Four-Port Analysis of SwitchedCapacitor (SC) Networks • Signal-Flow Graph Analysis of SwitchedCapacitor Circuits

Analog integrated circuits play a critical role in most modern communication systems as well as in applications where miniaturization, low cost, and low power have a high priority. Examples include the so-called Analog Front End (AFE) of most integrated systems that interface with the physical world, such as wireless transceivers, Ethernet LAN cards, and xDSL modems, as well as the electronic interfaces in most micro-systems used in household appliances and medical electronic equipment. Since IC technology is mostly dominated by the requirements of digital VLSI processing, analog integrated circuit design must generally be adapted to the characteristics of this dominant technology. Typically these characteristics include a lack of precision passive components, and a high degree of interference from the surrounding digital circuitry. With the inevitable combination of analog and digital, i.e., mixed-mode, signal processing on a chip in modern integrated systems, not only the analog designer, but also the digital IC designer, must become familiar with the characteristics and limitations of analog signal processing and its on-chip building blocks, i.e. components, such as transistors, amplifiers, and filters. The latter occur on a chip both as discrete-time circuits in the form of switched-capacitor circuits as well as, more recently, as continuous-time active RC filters. In order to ease understanding of each topic, the basics - leading up to the actual material - are first reviewed.

Design of Switched-Capacitor Filters
• Designing SC Integrators • Design Techniques for SC Filters and Networks: Parasitic effects and parasitic insensitivity • Design of SC Biquads and Ladder Filters

ETH Zurich, Switzerland

Selected Topics from Continuousand Discrete-Time Signal Processing
• Analysis and Design of Switched-Capacitor Circuits • Sensitivity Theory and Its Application to Component Tolerances and Filter Specifications • Designing On-Chip Continuous-Time Active RC Filters for the Analog Front End of Integrated-Circuit Systems • Parasitic Effects of Distributed IC Resistors

ETH Zurich, Switzerland and Bar-Ilan University, Israel

CMOS/BiCMOS Technology and Component Design
• CMOS, BiCMOS Technology and Scaling Trends • Transistor Characteristics and Modeling • Component Design • Precision and Matching

The emphasis of this course is on design of analog circuits in an integrated circuit context. For this purpose, analysis, design, and optimization of continuous- and discrete-time circuits are covered in detail. The lectures will be evenly distributed between devices and circuits in bipolar and CMOS technologies, filter design, as well as analog and sampled-data signal processing. The course is intended for engineers with experience in the field of MOS circuit design. It also contains introductory subjects in order to bridge the gap between the technology and IC circuit designers on the one hand, and the systems engineers applying analog and sampled-data signal processing techniques and filtering, on the other.

Basic Circuit Building Blocks
• Simple Amplifiers, Active Load • Current Sources • Cascode and Regulated Cascode Concepts • Single-Stage Amplifiers, DC Gain • Unity-Gain Bandwidth, Phase Margin

Requirements of Integrated Circuits
• Charge Transfer in SC Circuits • Transient Analysis of SC Circuits • Requirements of Op-Amps for Accurate Charge Transfer • Noise and Interference Coupling through Substrate and Power Supply • Circuit Response to Power Supply Variations, the PSRR • Circuit Response to Common-Mode Signals, the CMRR

Continuous-Time Signal Processing
• Mixed-Mode Signal Processing • Filter Specifications and Approximation Theory – Basics for the Design of Filters of Any Kind • Filter Tables and Computer Programs • Signal-Flow Graph Theory – Essential for the design of inductorless filters • Basic Building Blocks and Concepts: Controlled sources, active gain devices, impedance converters and inverters, frequency-dependent negative resistors, etc.

Design of Operational Transconductance Amplifiers
• Single-Stage Operational Transconductance Amplifiers (OTAs) • Folded Cascode OTAs • Two-Stage Amplifiers • Regulated Cascode Amplifier • Optimization of the Regulated Cascode Amplifier • Differential Implementation of OTAs • Variants of Single Stage OTAs • Common-Mode Feedback Biasing of Differential Amplifiers • PSRR in Miller Compensated Amplifiers • Variants of Two-Stage Amplifiers

Active-RC Filter Design
• Passive and Active-RC Filters • Active Filter Design Techniques • A Morphological Approach to Design • Converting LC Filters into Active-RC Filters Amenable to Chip Design • Increasing Dynamic Range by Balanced Filters • A Comparison of Design Techniques

Second-Order Effects and Reduction
• Mismatch in Differential Circuits • Offset and Circuit Design • Clock Feed-Through • Thermal Noise and Flicker Noise • Noise in Operational Amplifiers • Noise in Switches • KT/C Noise in Sampled Circuits • Correlated Double-Sampling • Chopper Stabilization

Discrete-Time Signal Processing
• Transformation from Continuous-Time to Discrete-Time Signals: The sampling process, the sampling theorem, and the analysis of sampled signals, the z-transform, aliasing, convolution, and the transformations between s- and z-plane • Bilinear, LDI, Backward and Forward Euler Integrators • Pre-Warping • Conversion of Continuous-Time to Discrete-Time Filter Specifications

Low Voltage Design Considerations
• Low Voltage Amplifiers • Layout Considerations • Matching and Layout of Precision Analog Circuits • Substrate Coupling in Integrated Circuits

Advanced Analog ICs


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Course 85

March 30 – April 2, 2009. Barcelona, Spain October 26-29, 2009. Barcelona, Spain The Integer N PLL in a Wireless IC
As the loop filter is a key element in any PLL, its dimensioning is based on lock time and spurious requirements.
• Loop Filter Dimensioning from Lock Time Requirements • Compromise between Spurs, Noise and Lock Time • Sources of PFD Spurs • Charge Pump Issues • Problems Linked to Speed-up Circuits

Phase Locked Loop frequency synthesizers are key building blocks in wireless communication systems. Good knowledge of its potential and the constraints of PLLs are important not only for circuit system engineers but also design engineers. In the past, discussions on synthesizers have been centred on performance optimisation and concept partitioning. Today, the industry is making huge progress towards total integration into one piece of silicon together with other building blocks needed for a complete radio, all with the goal to make future wireless products affordable and comfortable in use. This general trend is supported by usage of various more digital synthesizer techniques. They were introduced into measurement equipment 15 years ago to increase performance.

The Fractional N PLL in a Wireless IC
An approach to overcome the constraints of lock time, phase noise, and spurious suppression is the fractional N concept.
• Basics of Operation • Spurs Due to the Fractional Concept • Analog and Digital Fractional Compensation • Limits of Fractional Compensation Circuits • The Impact of Phase Detector Linearity • The Measurement of PLL Parameters • Phase Noise Measurement with a Spectrum Analyzer • Phase Noise Measurement by Down Conversion • Delayed Self Homodyne Phase Noise Measurement • Simple and High Precision Lock Time Measurement Methods • Measuring the PLL Phase Transfer Function

RF Consult GmbH, Irschenberg, Germany

This course enables engineers to understand the principles of PLL circuits and its applications and to design PLL synthesizers optimized for a given application. It introduces advanced technologies of frequency synthesis used in modern communication devices.

Texas Instruments A/S, Aalborg, Denmark

Control loop basics are the foundation of any detailed PLL consideration. The concepts of open and closed loop gain, phase and amplitude margin and their link to the dynamical behaviour are introduced. The Z-transformation as a method to describe and optimize the behavior of time discrete control loops is explained.
• Open and Closed Loop Gain and Phase Transfer Function • Bode Plot, Phase Margin, Amplitude Margin • Poles and Zeros, Characteristic Function • Closed Loop Transfer Function, 3dBBandwith, Dynamic Control Behavior • Describing Time Discrete Control Loops by Z-Transformation • Principals of Modulators

We review various transceiver/synthesizer concepts. Special focus is on how to modulate a carrier for TX and maximize reuse HW for RX in half-duplex systems. • On-Channel Modulation • Offset-Loop
• Open-Loop Modulation • Closed-Loop Modulation

Direct Digital Synthesis
The architecture of a DDS is analyzed in detail. The noise and spurious response of the system is considered for each building block. Other system parameters like lock-time and frequency resolution will be touched. • Accumulators • Phase and Amplitude Quantization
• Frequency Resolution • Spurious Analysis • DAC

Phase Noise in a Wireless System
Parameters that describe the phase fluctuations and establish relationships between different sets of parameters are introduced. The impact of the noise behavior of a PLL on the receiver and transmitter performance in a wireless system is discussed.
• The Phase Angle as a Random Process • Parameters Describing Phase Fluctuations and Relations between Them • SSB Phase Noise, Phase and Frequency Error • Effect of the Phase Noise on the Blocking and Adjacent Channel Power Performance

Sigma-Delta PLL
Starting from a classical PLL, the mathematical description of the noise behaviour of a Sigma-Delta PLL with multi-modulus divider is developed. The digital fractional spurious compensation is modelled, and in a second step we perform a quantization noise simulation and extract a rule of thumb for practical usage. Frequency resolution and other key parameters are treated before advantages are summarized.
• Sigma-Delta Modulator • MASH • Divider Control • Quantization Noise • SSB Phase Noise • Frequency Resolution

PLL Components
We focus on the components that build a PLL. All building blocks of a PLL are described in terms of their linear transfer functions.
• VCOs • Phase Noise in VCOs • Phase Detector Types • Charge Pumps • Use of Op-Amps • Dividers and Mixers in a PLL

Generate Modulated Signals with Digital PLLs
The advantage of this PLL architecture to generate phase- and frequency modulated signals is presented. For vector modulated signals the sigma-rho concept is compared to a classical on-channel modulation concept. • In-Band and 2-Point Modulation • Modulation Bandwidth • Sigma-Rho Modulation • Vector Modulation • Impairments • IQ Modulator • On-Channel Modulation

Based on the linear description of the building blocks, we will derive the transfer functions of a PLL and their implications on the system performance such as switching time and spurious suppression. A discussion of the noise behaviour of the PLL will complete this section.
• The Phase Transfer Function • Transfer Functions for Noise and Spurious Signals • Lock Time, Natural Frequency, Damping Factor, and Phase Margin • 2nd-, 3rd-, and High-order Filters • Correlation between Phase Comparison Frequency and Loop Bandwidth Requirements • Phase and Frequency Modulation in a PLL • Sources of Phase Noise in a PLL and Its Simulation

Complete Digital PLL – Digital Controlled Oscillator (DCO)
Silicon technology trends allow new PLL architectures and increase its digital content. Starting point is the analysis of a DCO and basics of a non-linear control loop. Means to increase the frequency resolution and quantization noise will be treated on architectural level before discussing the benefits. • DCO • Digital Loop Filter • All Digital Loop
• Quantization • Non-Linear Control Loop

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Course 86

May 25-28, 2009. Copenhagen, Denmark October 12-15, 2009. Copenhagen, Denmark

Radio frequency and microwave techniques are of increasing importance to industrial, communication, home, and office applications. Production testing, design verification, and sometimes even the design itself require highly specialized measurement and test techniques. Accordingly, there is a rising demand for engineers who have a sound knowledge in RF and microwave laboratory measurement techniques.

RF Signal Generators
Operation principles of synthesizers and modulators used in microwave signal generators will be discussed. The design of generators requires certain compromises and practical generators always have their limitations. Practical hints for the use of signal generators in a measurement system will be revealed.

RF Consult GmbH, Irschenberg, Germany

This course will familiarize the participant with distinctive features and tools of RF and microwave techniques, such as features of resonant circuits, distortion and noise problems, reflection and matching, the S-parameters, and the handy Smith Chart tool. Based on this acquired basic knowledge, we will focus on features and applications of signal generators, spectrum analyzers, network analyzers, and signal analyzers, including the most commonly used accessories. Hands-on exercises and practical examples will demonstrate the proper use of RF measurement equipment.

• The PLL Synthesizer • The Direct Digital Synthesizer • Frequency Accuracy and Drift • Analog Modulation • Digital Modulation • I/Q Modulation • σ/ρ Modulation • Correction of the Frequency Deviation Error • The Use of Generators in Harmonics and Distortion Measurements

Swept Tuned Spectrum Analyzers
The function of a swept tuned spectrum analyzer will be studied via a practical example. From this we will understand the importance of the spectrum analyzer settings and their impact on the performance. Like any other electronic device, the spectrum analyzer introduces nonlinear distortions and noise to the signal under test. These effects are described in detail. We will learn to find optimum settings to maximize the dynamic range for a given measurement.
• Basic Function • Spectrum Analyzer Settings and Their Impact on the Performance • Nonlinear Distortions and Noise • The Dynamic Range of a Spectrum Analyzer

The Approach to RF and Microwave Technology
This first lecture will demonstrate typical ways to approach and deal with RF and microwave techniques and problems. We introduce parameters that describe reflections and mismatch and learn how to use the Smith Chart as a powerful tool for impedance transformations. Building blocks and components are often described by 2-port parameters. We therefore introduce measurement setups for Z-, Y- and S-parameters and learn how to use the parameters to describe the behaviour of circuits.
• Basic Definitions • Passive Components at RF • Reflection and Matching • The Smith Chart • 2-Port Parameters

Vector Signal Analyzers
By use of the Fast Fourier Transform (FFT), the vector signal analyzer can perform the same measurements as the swept tuned spectrum analyzer. That includes frequency and level, harmonic distortion, and intercept point measurements. However, the dynamic range is smaller. As opposed to the swept tuned spectrum analyzer, the vector signal analyzer also provides information on the phase of the signal. Further, due to the increased Intermediate Frequency (IF) bandwidth, it can display time-dependant signals. The decomposition into in-phase and quadrature components gives information that is necessary if Quadrature Phase Shift Keying (QPSK) or Quadrature Amplitude Modulation (QAM) modulation formats are used.
• Basic Function • Frequency Domain Measurements • Time Domain Measurements

The Effect of Transmission Lines
Transmission lines form the connections between RF and microwave measurement equipment and the devices under test. Therefore, we need to understand the characteristics of those transmission lines and their possible impact on the measured parameters. Practical situations in measurement setups will be demonstrated and discussed in great detail.
• Transmission Lines • The Characteristic Impedance • Transmission Line Input Impedance • Transmission Line

Network Analyzers
The function of various types of network analyzers will be studied. Systematic errors will be discussed and available methods of their correction introduced. We learn how to use vector network analyzers for reflection and transmission measurements as well as for the measurement of nonlinearity parameters.
• Network Analyzer Architectures • Systematic Errors and Their Impact • Calibration of Network Analyzers • Measurements at Differential Ports

Nonlinear Distortions and Noise
Nonlinear distortions and noise limit the performance of any wireless system and in the same way of RF measurement equipment. We will introduce the underlying sources to nonlinear distortion and noise and identify the characteristic parameters to describe those effects.
• The Generation of Nonlinear Distortions and Noise • Noise Figure • Intercept Points • Phase Noise and Its Characterization

Hands-on Exercises
Participants will apply their acquired knowledge on measurements on prepared devices.
Spectrum Analyzers: Acquiring a Signal, Measuring Power and Frequency • Measuring the Occupied Bandwidth of a Modulated Signal • Intermodulation Measurements, OIP2 And OIP3 • Measuring the Signal to Noise Ratio • Phase Noise Measurements • Frequency versus Time of a FSK Signal Network Analyzers: Calibration with the Calibration Kit • S Parameters of an LNA • Measurements on SMD Components

RF Laboratory Accessories
RF laboratory accessories are different from those used at lower frequencies and can substantially affect the dependability and accuracy of measurements. We will therefore focus on the use of cables, attenuators, couplers, filters, mixers, and low noise amplifiers in a RF lab.
• RF Cables • RF Connectors and Their Handling • Attenuators • Combiners and Splitters • Directional Couplers • Non-Reciprocal Components • RF Filters • Mixers • Low Noise Amplifiers


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Course 91

From System Architecture to PCB Implementation
April 20-24, 2009. Barcelona, Spain

Wireless technology penetrates more and more applications in the industry, the home and the office. The semiconductor industry offers a wide range of IC devices for wireless transmitters and receivers. It is the charter of the RF circuit designer to implement these ICs on a PCB according to the system architecture.

Building Blocks of Wireless Transmitters and Receivers
Based on the knowledge obtained in the previous section, building blocks of wireless receivers and transmitters will be treated. The course lets the participant understand the principal function and the specifications of low noise amplifiers, power amplifiers, oscillators, and mixers. Practical hints to use integrated circuits that contain these building blocks are given.

RF Consult GmbH, Irschenberg, Germany

Starting from a system level consideration and ending with an example of a practical realisation, the course enables the participant to implement a wireless data transmission system on the PCB level. Particular attention is paid on the tuition of immediately applicable knowledge. The tools most frequently used in RF engineering are introduced, their application is exercised on practical examples.

• Amplifier Design • Stability of Amplifiers • Loci of Constant Noise Figure • The available gain concept • LNA Design Example • Power Amplifiers • Oscillators • VCO Tank Circuit Design • Mixers

Thursday Monday
Wireless Data Transmission on the System Level
This section gives an overview on the modulation formats and multiple access techniques used in wireless transmission systems. Typical transmitter and receiver architectures are introduced; their advantages and disadvantages will be discussed.
• Analogue Modulation Methods: AM, FM, PM • Digital Modulation Methods: ASK, FSK, m-PSK • BER vs. Signal-to-Noise-Ratio • Multiple Access Techniques • Examples of Wireless Standards • Typical Transmitter and Receiver Architectures

Phase Locked Loop Synthesisers
We begin with a discussion of the control loop basics needed for the analysis of the dynamical behaviour of PLLs. Parameters that describe the phase fluctuations are introduced and the impact of the noise behaviour of a PLL on the receiver and transmitter performance in a wireless system is discussed. As the loop filter is a key element in any PLL, its dimensioning based on lock time and spurious requirements will be treated in great detail. We will also discuss sources of phase detector spurs, speed-up circuits and the problems linked to it. At the end of the session, we introduce fractional-N and σ-δ-PLLs.
• Transfer functions • Stability Criteria • Characteristic Function • Bode Plots • Description of Phase Noise • Impact of Phase Noise on the System Performance • Lock Time, Natural Frequency, Damping Factor, and Phase Margin • 2nd-, 3rd-, and High-order Filter • Phase and Frequency Modulation in a PLL • Sources of Phase Noise in a PLL and Its Simulation • Loop Filter Dimensioning from Lock Time Requirements

RF Basics
We discuss the exceptional features of the radio frequency range, complex numbers, logarithmic scales, impedance and admittance concepts. The features of ideal and real passive components at radio frequencies will be explained.
• Complex Numbers • Logarithmic Scales • Passive Components • The Impact of Parasitics

RF Basics (cont´d)
We consider resonant circuits, transmission lines, reflection, and matching. The use of the Smith Chart as a tool to solve matching tasks will be extensively practiced. A discussion of S-parameters, nonlinear distortions and noise completes the RF basic section.
• Resonant Circuits • Reflection and Matching • The Smith Chart and Its Application • 2-port-parameters and S-parameters in Particular • Transmission Lines • Nonlinear Distortions • Noise Behaviour and Sensitivity Considerations • Network Analysis Software Tools

Antennas and Propagation
We explain parameters describing antennas and discuss the relationships between them. Antenna types for small and handheld devices are introduced; their advantages and disadvantages will be discussed from a practical point of view. Then we will consider the propagation of RF waves in free space and inside buildings, and introduce methods of predicting the maximum reach of a RF link. At the end of the session practical hints for the measurement of antenna parameters are given.
• Antenna Parameters • Electrical Antennas • Magnetical Antennas • Practical Comparison of Antenna Types for an Example Application • The RF Link Budget • Path Loss Prediction in Free Space and Inside Buildings • Multipath Effects and Their Mitigation • Measurement of Antenna Parameters

Application Example
The course concludes with an exercise starting with the requirements of a simple practical design task, ending up with the practical implementation using ICs including PCB layout and antenna.

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Course 57

March 10-13, 2009. Davos Switzerland September 29 – October 2, 2009. Cambridge, UK

Larger and faster Systems-on-Chips employ multiple clock domains on the same die for several reasons: Communications with external real-time or pre-defined clocks require chips to incorporate multiple, unrelated clock frequencies; it is more economical in very large chips to break down the system into independently clocked domains, saving some of the power required for clock distribution; and dynamic scaling of voltage and frequency creates multiple clock/voltage domains. Interfaces among different clock domains are problematic and are only partly supported by commercial EDA tools. As a result, synchronization problems are sometimes discovered only in working silicon, and even then they are hard and expensive to correct.

Synchronization of Asynchronous Clock Domains
• Control Synchronizers • Formal Specification Using STG • Data Validity of Synchronizers • Push Synchronizers • Timing Assumptions • Faster Synchronizers • Shared Latch Synchronizers • FIFO Synchronizers • Reset Synchronization • Clock Gating and Selection Synchronizers • Scan Insertion Synchronizer • Mutual Exclusion and Arbiters

VLSI Systems Research Ctr., Technion, Haifa, Israel

Common Synchronization Errors
• Avoiding Synchronization • One Flop Synchronizers • Sneaky and Greedy Paths • Half Protocol • Async Clear • Pulse Synchronizers • Slow-to-Fast Synchronizers • Metastability Blocker and Filters • Parallel, Shared Latch, and Conservative • Synchronizers • Patented Circuits for Fast Resolution and Pre-Sampling • Shaker and Dual Shaker Synchronizers

The course teaches the science, engineering and art of synchronization. We define the problems, survey existing solutions, study the best designs, and learn how to select the better synchronizer for each purpose. We review clocking in digital chips, study the required theoretical basics, learn how to understand synchronization problems, identify them, create reliable solutions, and verify their correctness. We consider SoC/ASIC and FPGA, mostly at the logical level. Implications on physical design are briefly reviewed. We also review voltage domains, power gating, voltage scaling and their effect on clock domains and synchronization.

Verification of Synchronizers
• Identifying Domain Crossings • Structural Verification • Sorting the Domain Crossings • Grouping Synchronizers • Connecting Bi-Directional Protocols • Recognizing Synchronizers • Employing Formal Tools • Functional Verification • Data Verification • Manual Verification

• VLSI/ASIC/SoC/FPGA design engineers, architects and managers engaged in the design of advanced SoC • VLSI/ASIC/SoC/FPGA CAD engineers and developers • Academic researchers, university professors, and graduate students interested in advanced SoC design Basic knowledge of digital VLSI/ASIC/FPGA design is assumed. Prior exposure to issues and pitfalls of synchronization is an advantage, but neither such exposure nor prior knowledge of synchronization is necessary. General background in electrical or computer engineering is useful.

Multi-Synchronous and Periodic Synchronizers
• Mesochronous/Multi-Sync Synchronization • Delay Variations • Data Delay Synchronizers • Conflict Detection • Clock Delay Synchronizers • FIFO Synchronizers • Clock Edge Synchronizers • Periodic Domains and Predictive Synchronizers

Multi-Synchronous and Asynchronous Long Interconnect
• Definition of Long Interconnects • Point-to-Point, Buses and Networks on Chip • Source-Synchronous and Adaptive-Clocked Interconnect • Data Encoding: Dual rail and 1-of-4 • Four- and TwoPhase Protocols • Asynchronous Interconnect • Dual Rail and 1-of-4 Interconnect • Two-Phase Dual Rail Interconnect • Fast Serial Interconnect • Asynchronous and Mixed-Timing FIFO • Pipeline Synchronizers • LDL Synchronizer

• Problem Definition and Motivation • Course Description

Multi-Clock Domain and GALS SoC
• Synchronizer-Based GALS • Arbitrated and Handshake Stoppable Clocks • Wrappers and Asynchronous Ports • GALS Methodologies • Desynchronization • Synchronization in Networks on Chips (NoC)

Clock Distribution Networks
• Problem Definition • What’s Ahead: The technology roadmap • ASIC/SoC vs. Full-Custom Design Methodologies • Standard Clock Trees for SoCs and FPGA • Min-Delay and Max-Delay Problems • Data Delay Insertion and Delay Line Circuits • Clock Delay Insertion and Clock Tuning • Unbalanced Tunable Clock Distribution Networks • High Performance Clock Trees • Passive and Active Deskew in Clock Trees • Local Clock Generation with Tunable Frequencies

Multiple Voltage Domains
• Definitions, Sources of Multiple Voltages • Level Shifting and Isolating Gates • Combining Voltage and Clock Domains • Floor-Plan and Layout Constraints • Dynamic Voltage and Frequency Scaling • DVS versus DVFS • Global versus Multi-Domain Scaling • Methods of DVFS

Metastability and Synchronization Failures
• Metastability • Latches and Flip-Flops • Measuring Metastability • Probability and MTBF • Synchronizer Circuits • Symmetric Booster Synchronizer • Latency and Settling Time • Simulating Metastability

Conclusions and Summary


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Course 15

March 9-13, 2009. Davos, Switzerland September 28 – October 2, 2009. Cambridge, UK Characterization of Transmitters
• Power and Harmonic Distortion • Spurious Products • ACPR, Spectral Regrowth and Linearity with Different Modulation Formats • Efficiency

The increasing level of complexity and circuit integration in modern wireless systems requires not only understanding of the design of circuits, but of subsystems as well. RF circuits are typically designed to meet power, efficiency, gain, linearity and noise specifications when driven by single or two- tone excitations; whereas the RF system is driven by much more complex signals and must be designed to meet specifications like bit error rate, dynamic range, and minimum detectable signal in the presence of interferers. Only through understanding the interactions between circuits, and through careful simulation, can all the specifications be reconciled.

Frequency Selection
• The Image Frequency • Choosing the Correct Intermediate Frequency



This course will focus on tradeoffs in designing wireless systems, and how to seamlessly move between both the circuit and system level in radio transceivers and other RF systems. We do this by looking at typical radio architectures, exploring the design tradeoffs, and simulating at both the circuit and system level. The course treats digitally coded signals in RF and IF components, and explores the compromises that are inherent in the design of a radio transceiver. From the RF perspective, the need to minimize interference from nearby unwanted stronger signals and to allow detection of a desired signal in noise is critical. Avoiding corruption of other signals sharing the spectrum is equally critical. Achieving both together is not so simple! We will interactively simulate a double super-heterodyne, dualband radio receiver, a direct conversion receiver, and an I-Q modulator and transmitter, as well as various components that make up these systems. This provides the opportunity to explore ‘what if?’ scenarios. To benefit most, bring your own laptop computer. On completion of the course, you will be: • Familiar with the air-interface specifications of a mobile radio system, and understand how the key parameters relate to RF hardware • Able to simulate various types of RF and IF systems and component interactions • Able to specify the key components within a system to meet its RF requirement • Comfortable with reading integrated circuit data sheets for wireless systems, their architecture, and specifications • Able to understand the compromises in choosing architectures and circuits to meet given system requirements.

Next, we will see how these system parameters can be met by assembling a number of components. We will turn to their data sheets to discover how each is characterized, and examine the tradeoffs involved in selecting them. We will extract key defining features that describe the behaviour of each circuit, and then simulate both the component and the system in the systems simulator.

University of Queensland and Australian Institute for Commercialisation, Brisbane, Australia

Systems Simulation – Behavioral Modeling Simulation of a Dual-Band CDMA Superhet Radio Receiver
• Spreadsheet-Based Linear Systems Analysis • Calculation of Sensitivity and Dynamic Range • Systems Simulation • Using AGC to Increase the Dynamic Range • Effect of Changing the Gain, Intercept Point, and Filtering

• Spurious Analysis • Image Reject Mixers • I-Q Modulators and the Importance of Quadrature • Basics of Mixer Design

We will explore how the key RF functions of amplification, frequency synthesis (oscillation), and frequency translation (mixing) are achieved at the circuit level. This process will highlight some of the key tradeoffs in design, for example, between the power, efficiency, and linearity in a transmitter, and enable us to model these tradeoffs. We will focus on discrete design and review some IC designs.

• Basic Concepts of Oscillator Design • Deriving the Oscillator Tuning Curve and Explaining Mode Hopping • Phase Noise in Oscillators • Calculating Allowable Phase Noise from System Specifications

Radio Systems and Digital Communications
We start by reviewing digital wireless communications and a variety of modulation formats, and the tradeoffs between capacity, bandwidth, signal power, and noise. We look at the upconversion and downconversion processes in typical receiver and transmitter architectures, and the effects of filtering.
• Revision of Communication and Information Theory Principles • Coding and Modulation Formats • Baseband Filtering and Digital Sampling • Typical Receiver System Architectures - Direct Conversion, Superheterodyne, Dual Conversion Superheterodyne

Power Amplifiers
• Design Tradeoffs between Linearity, Power, and Efficiency • Classes of Amplifier Operation • Simulation of Spectral Regrowth with Different Modulation Formats

Examples of Commercial Integrated Sub-Systems-on-Chip Simulation of a Radio Transmitter

Finally, we look at a variety of challenges facing the systems designer; we examine some ‘real’ air interface specifications, and we work an example of the complete design process, from air interface specification through to circuit design.

We will look at a simplified form of the air-interface specification for a basic (CDMA) radio system. This describes the overall radio system requirements and enables multiple system operators to co-exist and interoperate. We will examine the key system parameters that have to be measured – parameters such as noise, distortion, sensitivity, selectivity, and interference. We also examine how the IF is chosen.

Topics in Software Defined Radio: ADC, DSP, Transceiver Issues Simulation of a Direct Conversion Receiver
• Trade-Off between Modulation Scheme, Data Rate, RF Bandwidth, Channel Filter, Power, Noise, Phase Noise, and Bit-Error Rate

Characterization of Receivers
• Noise in Receivers • Selectivity, Sensitivity and Minimum Detectable Signal • Nonlinearities and Third-Order Intermodulation Distortion • Reception in the Presence of Interferers • Dynamic Range and How to Improve It with AGC

Interpreting Air Interface Specifications
• CDMA (Narrowband and Wideband) • Sample 3G WCDMA Requirements

Design Considerations of a Typical Wireless GaAs and CMOS Chip Sets

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Course 08

March 9-12, 2009. Davos, Switzerland September 28 – October 1, 2009. Cambridge, UK

In any system, the power amplifier (PA) is a critical component. It is typically the most costly single item and consumes most of the supply power. Knowledge of the possibilities for trading power per unit cost with efficiency and linearity often forms the basis for the entire system architecture design. The increasing use of linearisation techniques, and especially the emergence of high speed digital processing as an enabling technology to implement predistortion on the PA input signal, represent an important paradigm shift in PA design. The PA component can now be designed with more emphasis on efficiency, without the traditional constraints of meeting stringent linearity specs simultaneously. Maximising the utility of a lineariser in order to obtain optimum efficiency has thus become a new subject area in modern RF PA design

Class AB PA Design
We will focus on practical issues in the design and manufacture of PAs for RF and MW systems. Several design examples will be demonstrated, including a GaAs MESFET, a GaAs HBT, and a high power LDMOS device.
• Class AB circuits • Harmonic Terminations • CAD Design Examples

University of Cardiff, UK

Power Amplifier Non-Linearity and Signal Environments
We will focus on the non-linear properties of RF PAs, their source, manifestation, and methods for their characterization and modeling. A topical issue of great impact in modern linearised multi-carrier PA (MCPA) applications is memory effects. This subject will be illustrated with device measurements, and physical causes and remedies will be discussed. There will be a full treatment of bias network design. The process of converting a measured PA gain compression and AM-PM characteristic into spectral and EVM distortion, and the issues involved, will be discussed using several different modulation environments, including GSM-EDGE and WCDMA.
• Non-Linear PA Characteristics, Gain Compression, AM-PM • Physical Origins of AM-PM, Analysis • Peak to Average Power Ratio Issues in Modern Signal Environments • Spectral Regrowth and EVM • Power Series, Volterra Series. Model Fitting using measured Data • Envelope simulation using EDGE, OFDM signals • Memory Effects, definition, dynamic gain/phase measurements, causes and remedies • Bias Network Design and Stability

This RF PA design course deals with the theory and design of RF power amplifiers for wireless, satcom, and microwave applications. The course features in-depth treatment of PA design, PA modes, envelope power management, and non-linear effects.

This course presents an overview, fundamentals, theory, practical and advanced power amplifier design which will be of interest to engineers and technical staff, who plan to pursue this technology, or compete with it.

Enhance your understanding of: • Power amplifier basic concepts, classes of operation, stability, linearity, bias technique • Impedance matching techniques based on lumped elements and transmission lines • High-efficiency techniques including well-know Classes F and E and newly developed classes, Efficiency Enhancement Techniques • Power Amplifier Non-Linearities and Signal Environments • PA Architecture

Efficiency Enhancement Techniques
We will focus on the key issue of power back-off (PBO) efficiency, and LINC (linear amplification using non-linear components). Envelope management methods and tracking techniques in PA design will be presented. These include classical techniques such as the Chireix outphasing method, the Khan and the Polar Loop envelope reconstruction approaches and the Doherty PA. Other less well-known techniques will be discussed, with emphasis on the broader band requirements, which WiMax systems require. Ultra high efficiency amplifier modes, Classes C, D, E, and F will be analyzed as possible candidates for LINC implementation and as stand-alone possibilities in systems using digital pre-distortion or feed forward linearization. Finally, PA architecture, including multistage effects, power combining techniques, and load pull design will be discussed. The course will conclude with a discussion on microwave PA design at higher GHz frequencies and will address the various issues such as efficiency and linearity in the context of higher frequency and broader bandwidth applications.
• Power Combining Techniques • Balanced and Push-Pull Operation • Load-Pull Techniques • Microwave PA Design

Power Amplifier Basics and Signal Environments
Linear amplifier modes are described with quantitative analysis of power, efficiency and linearity tradeoffs in uncompensated form leading into a discussion of the device technologies currently available for PA design, including LDMOS, GaAs MESFET and HBT, SiC and GaN. Differences between bipolar and FET devices, and the effects of different kinds of parasitic effects will be discussed using circuit analysis and CAD models. Possibilities for tailoring the characteristics of devices for optimum efficiency and linearity will be presented. Particular emphasis is given to correct fundamental and harmonic matching. The impact of non-ideal harmonic terminations in practical Class AB designs will be analysed quantitatively. Various modulation systems (QPSK, EDGE, CDMA, OFDM) will be reviewed from the viewpoint of PA requirements.
• Introduction • Classical PA Modes, Class A, Class AB, Class B, Class C • PA Device Technology • Optimum Device Characteristics for Class AB Operation • Modulation Systems in Wireless Communications QPSK, GSM, EDGE, OFDM • Effect of Signal Environment on RF PA Design


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Course 06

April 20-23, 2009. Barcelona, Spain October 12-15, 2009. Copenhagen, Denmark

The increasing use of linearisation techniques, and especially the emergence of high speed digital processing as an enabling technology to implement predistortion on the PA input signal, represent an important paradigm shift in PA design. The PA component can now be designed with more emphasis on efficiency, without the traditional constraints of meeting stringent linearity specs simultaneously. Maximising the utility of a lineariser in order to obtain optimum efficiency has thus become a new subject area in modern RF PA design

Introduction to PA Non-Linearity Effects
Day 2 will start with an introduction to nonlinear effects in RFPAs. The relationship between gain non-linearities and system level specifications such as ACP and EVM will be discussed. Memory effects will be discussed from a practical viewpoint. Later in Day 2 the modelling part of the course will start, defining various model types and their use in modern digital communications systems.
• AM-AM, AM-PM • IM and ACP for Typical Digital Modulation Environments • Memory Effects

University of Cardiff, UK

This course takes a “system-level” approach to the linearization and behavioural modelling of RF Power Amplifiers. As such the course will not cover RF PA design in detail and can be considered as complementary to CEI course #08. Special emphasis is given to a detailed treatment of PA modelling, both as a means of allowing more meaningful system level simulations, and also as a necessary starting point to the development of advanced predistortion algorithms for PA linearization. The course is a newly revised and updated RF PA design course, dealing with system level issues in the specification and performance impact of RF power amplifiers in wireless, satcom, and microwave applications. It features in-depth treatment of behavioural modeling of PA non-linear effects. The main focus is to understand, characterize and model the non-linear behaviour of RFPAs, and to demonstrate the evolution of these models into successful predistortion algorithms. Particular emphasis will be given to the treatment of memory effects.

Nonlinear Modelling Basics
• Compact Models: Applications and advantages • Usefulness of Behavioural Models and Their Applications • Review of Wireless Communications Signals and Systems, and Implications for Modelling

Freescale Semiconductor, Inc, Tempe, AZ, USA

Wednesday - JOHN WOOD
Advanced Behavioural Modeling
Day 3 will continue the discussion on behavioural modeling, getting into some mathematical detail with the power series, the general Volterra formulation and its approach to model memory effects.
• System Identification Techniques: Mathematical models, including power series • Volterra Series Formulations • Artificial Neural Networks • Behavioural Model Implementations • Memory Effects

This course presents an overview, fundamentals, theory, practical and advanced power amplifier design, which will be of interest to RFPA designers and RF system designers. DSP developers who will be implementing the linearization algorithms will find this course beneficial, providing the necessary background knowledge in RFPA techniques and non-linear properties.

Enhance your understanding of: • Power amplifier basic concepts, classes of operation, stability, linearity, bias technique • PA Linearisation techniques • PA non-linearities including memory effects • Behavioural modeling of PAs, including memory effects • Use of behavioral models to formulate accurate predistortion algorithms • Application of pre-distortion linearization to RF PAs

Thursday - JOHN WOOD
Day 4 will focus on the theory and implementation of digital predistortion, building on some of the models that have been introduced on previous days. ”Linearizability” will be defined and several case studies will be considered.
• ”Linearizability” • Digital Pre-Distortion: Implementation, algorithms, reprise of memory effects • Case Studies in Behavioural Model Generation • RF PA Linearization Using DPD

Power Amplifier Overview
Day 1 will start with a brief review of RFPA technology and basic RFPA theory, focussing on mode classifications widely used in PA literature. This will be a functional overview of the subject, circuit topologies will not be covered. The second part of Day 1 will focus on various system level approaches to PA efficiency enhancement.
• RF PA Semiconductor Technologies • PA Modes A to Z • Efficiency Enhancement Techniques (Doherty, EER, ET, Outphasing)

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Course 26

April 20-24, 2009. Barcelona, Spain October 12-16, 2009. Copenhagen, Denmark
in frequency. Large signal behaviour in terms of spurious signal responses is described. Prediction of spurious signal frequencies and estimation of the levels is demonstrated. We end with the design of different configurations of IQ mixing for both transmitters and receivers. We present a practical approach to understanding filters and what is possible without resorting to complex circuit theory. Design tools for estimation of standard filter responses are presented and expanded to cover the more general case with prescribed finite frequency poles.

In order to design cost effect radios, designers must understand the whole system. Only then can the various interactions and trade-offs be appreciated and the design optimised for a particular application. Fortunately, understanding the whole system does not require detailed knowledge of the design of each circuit. By isolating key parameters it is possible to relate the system specification to block level requirements to see the whole picture.

Radio System Design, Leeds, UK

This course presents the necessary theory, principles and practical design information to identify the key system design parameters as well as how they compound in a given configuration and hence how they relate to the top-level specifications. It builds from basic models and descriptions of system behaviour. Describing common receiver and transmitter architectures, understanding the key impair-ments to reliable communications and looking at system solutions to modulation, multiple access and air interface standards. Practical tips with various tools are used to provide accurate initial estimates of component performance as well as show the relative contribution of each circuit block to the total. The more advanced design concepts are illustrated with examples using Microwave Office VSS software. Illustrations show how such tools help isolate critical parameters allowing designers to focus on the key aspects.

Mixers: Signal Conversion • Image Band – Signal and Noise: Noise figure of mixers • Calculating Spurs: Frequency and level, identifying worst ones • Phase Noise and LO Effects • I/Q Conversion Filters: Selectivity: Estimating complexity, effects of diplexing • Passband Loss: Qu considerations, bandwidth considerations • Filter Functions without the Circuit Theory: Standard methods, transfer functions

System Architecture
The architecture of superhet systems is described with a discussion on how to distribute gain and choose the LO, where to put the IF and considerations of near zero IF and direct conversion or zero IF schemes. The main differences in the design of transmitters and receivers are also considered. The expanding role of DSP and Software Defined Radio is discussed, how it enhances present architectures and the possibility of new alternatives.
Choosing the Correct IF: High and low side mixing, up/down or multiple conversion, direct conversion • Gain Distribution • Special Considerations for Transmitters • The Role of DSP • Design Tools • Spreadsheets - Plusses and Minuses • Examples and Uses of Low Cost Programs • Commercial System Simulators and Examples

This course deals with the system performance from constituent component block characteristics, how they interact and how they can be related to top-level system specifications. Examples and some historical perspective explains why modern radio systems work. The course is suitable for system designers wishing to better understand component level implications or practicing component design engineers interested in managing more complex sub-assemblies and systems. It is suitable for those working in radio as well as in the mobile phone industry, handset or base station, satellite communications, radar and EW/ECM.

Signal Transport – Link Budget and Modulation
Successful radio communication requires transport though a highly variable channel. We describe the key details of the radio link and various signal impairments. We introduce analogue modulation as a pre-requisite to more detail on various digital modulation schemes. This is then related back to the key link impairment mechanisms to see how different system ideas relate to preserving the signal content through the highly variable and error prone radio channel.
• Antennas • Free Space Propagation Path Analysis• Effects of Fading, Delay Spread and Doppler • Balancing the Link Budget • Modulation • Analogue Modulation AM and FM • Digital Modulation Schemes, BER • Advanced Schemes OFDM, Bandwidth Utilisation and Channel Capacity

SI – Noise, Intermodulation Distortion and Compression
The characteristics of two port blocks in the system are introduced using standard concepts. Methods to extend simple cascade analysis to multi-stage systems are described along with practical tips to better understand how the cascade builds up and how to evaluate the relative contribution of each stage. A new approach to the analysis of signal compression is described, using a method not found in textbooks.
Noise: Origins and Definitions: Noise figure, noise factor and noise temperature • Cascade Calculations: Standard formulae, single step simplification, calculating per stage increase and percentage contribution Intermodulation: Textbook Definitions – input or output reference, 2nd, 3rd and Nth order IM • Cascade Calculations: Single step cascade – phase addition, calculating per stage increase and percentage contribution • Sensitivity, Selectivity and Spur Free Dynamic Range • Compression • Useful Approximations • Cascade Calculations • Example Illustrating the Linear/Non-Linear Continuum

Multiple Access Methods, Radio Layer Standards
Drawing on the examples from earlier topics, multiple access concept of FDMA, TDMA, CDMA and OFDMA are described with detailed descriptions of the operation of some existing standards such as GSM, EDGE, IMT2000 and IEEE 802.11, finishing with systems such as HSDPA, MIMO AdHoc Networks and Cognitive Radio.
• Multiple Access Methods • The Distinction Between Modulation and Access Methods • The Dimensions of Frequency, Time and Symbols • Examples of FDMA, TDMA, CDMA and OFDMA • Multiple Access Planning, Frequency Re-Use Capacity and Efficiency • Radio Layer Standards • Physical Layer Standards • The Evolution from GSM to EDGE and IMT2000 • Newer Standards, IEE802.11 and DAB Radio Evolution • Advanced Concepts • 3G Long Term Evolution, HSDPA and Beyond • 4G Networks, MIMO, Ad-Hoc Networks and Cognitive Radio

Signal Translation – Mixers and Filters
We describe the issues associated with frequency translation of signals. Building on the IM discussions, mixer operation is described in terms of the small signal translation of modulated signals up or down


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Course 27

October 26-28, 2009. Barcelona, Spain

The ideas associated with sampling and digital signals that revolutionised modulation systems and are now revolutionising radio system design. This course continues the theme of block diagram rather than circuit diagram design, presenting an upto-date view on concepts for advanced radio systems that incorporate digital signal processing at RF frequencies and the concepts of software defined radio. It is a practical approach for technical professionals to understand the latest designs and architectures for radio systems that include DSP.

Sampling, DSP and Software Defined Radio
Sampling of analogue signals is well established in the baseband, but with advances in analogue to digital converters (ADCs) and digital signal processing, it is now possible to DR. apply these techniques directly to signals at RF frequencies. The important features of RICHARD G. RANSON ADC and DAC are described with reference Radio System Design, to sampling theory, baseband filtering and Leeds, UK Eb/No. Also examples of digital processing such as digital down conversion and filtering are covered with a view towards application to software-defined radio. The focus is on system level parameters such as signal and noise levels, intermodulation and dynamic range. Standard cascade analysis is extended to incorporate the ADC function.

This course builds on the Radio System Design –Theory and Practice course, but does not require that course as a prerequisite. The key basics are part of the introduction, which then builds and expands the necessary theory, principles and practical design information for radio transceiver design for standards such as CDMA2000, W-CDMA, WLAN, Bluetooth, WiMAX and Zigbee. Tools such as spreadsheets and system design examples using Applied Wave Research VSS software are used to illustrate topics though out the course. The course is illustrated with some custom applications, various spreadsheets, simulations and other useful information from application notes. These and other valuable information available on the web are included on a CD for future reference.

Local Oscillators, Mixers and Frequency Synthesisers
Most systems require at least one local oscillator. Essential details of oscillators, such as stability, tuning range and linearity are discussed. Similarly most systems employ at least one mixer and key features such as the image band, choice of IF and spurious signal responses are illustrated with examples. Options and designs for frequency synthesisers are described using examples of direct, indirect and digital synthesisers. System level performance is emphasised, mixers, multipliers and phase locked loops (PLL) are analysed in terms of spurious signal and noise generation. Measurement techniques for gain and phase margin in PLLs as well as phase noise are described. With the importance of IQ techniques, the methods for creating accurate IQ signals are described with examples of modulators and demodulator systems.

This is an intermediate to advanced level course for system architects, design engineers and managers looking for up to date information on recent advances in the field of radio system design. The objective is to expand the range of radio design into the DSP era. Learning objectives include identifying the critical RF parameters in wireless transceiver technology, understanding the various trade offs in different architectures and understanding the balance of analogue to digital processing for cost effective design solutions. These concepts have a broad range of application from low cost terminal devices for mobile communications, multifunction radio systems, remote sensing, advanced concept radios for radar/surveillance and enabling wireless connectivity in a variety of product and services. The course is suitable for those working in radio as well as in the mobile phone industry, handset or base station, satellite communications, radar and EW/ECM.

Transceiver Architectures Incorporating DSP
Bringing all the concepts of the previous days together, this section examines real system architectures. Using well-chosen examples, the strengths and weaknesses of different systems are examined. Essential principles of the superhet radio are described with different approaches such as single/multiple IF designs as well as direct conversion (zero) and near zeros IF options. Different frequency and gain planning and distribution options are highlighted, including the incorporation of automatic gain and frequency control loops. Finally, trends in DSP and the relevance to radio system architecture are described with special emphasis on the balance of analogue to digital functional blocks and the balance of hardware to software. Understanding these different ways of achieving the essential functions of a system will mould the architectural concepts in the future.

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Course 90

March 30 – April 3, 2009. Barcelona, Spain October 12-16, 2009. Copenhagen, Denmark

Wireless communication is expanding with the introduction of new standards and functions. Higher data rates for transmission and reception of voice, data, and video are being designed into RF hardware with additional unique innovative functions. New emerging systems require the transceiver to operate with multiple functions, standards, and frequencies. The transceiver architecture is a paramount in this process with demands for more function in a smaller volume with lower cost and power consumption. Transmitters need to employ effective efficiency enhancement and distortion reduction techniques. Receivers need to be simplified and made smaller with lower power, good sensitivity, selectivity, and stability. Spurious free operation with low distortion and the capability to operate with high signal levels and blockers is essential. Utilization of CAD tools which now includes complete system analysis is essential in reducing the design cycle time to get the products into the marketplace. Multifunction MMICs are being developed and are now available for insertion into transceivers for lower cost, higher reliability, and smaller size.

Transceiver Architecture and System Design – Receiver
Zero IF, low IF, and superheterodyne receiver types will be compared and the limitations and advantages of each type will be highlighted. The receiver A/D types, design rules, noise properties, and dynamic range will be DR. EDWARD C. NIEHENKE Niehenke Consulting, presented with actual system design examBaltimore MD, USA ples. Receiver system design will be presented to meet receiver sensitivity, noise figure, frequency accuracy and stability. Techniques to demodulate signals will be shown. The BER versus Eb/No for all system types are presented. Selection criteria for the IF for spurious free operation as well as power conditioning, filtering, circuit board layout and shielding will be shown with class examples.
• Receiver Block Diagrams and Important Receiver Parameters • Receiver Types, A/D Considerations • Receiver Elements Description • Receiver Demodulation and IF Frequency Selection • Receiver Calibration Techniques to Mitigate Imperfections • Transceiver Packaging, Layout, Interconnection, and Shielding Considerations with CAD

This course provides engineering tools to architect, design, and test multifunction, multi-standard wireless systems. Specifications will be presented for many advanced wireless standards such as EDGE, GSM, CDMA, CDMA2000, Wideband CDMA, 802.11, 802.16, and Bluetooth. The critical requirements will be highlighted for each system. CD’s will be distributed to each participant which include the latest transceiver reference papers, MMIC products, free design and evaluation software programs, and class exercises. In addition to the lecture, class exercises led by the lecturer will acquaint participants with the latest CAD tools and programs to design and trouble shoot the transceiver.

Multifunction Transceiver Architecture and Design
Receivers must operate in an environment with extraneous signals. Nonlinearities such as DC level shift, blocking, harmonic generation, intermodulation, cross modulation, and reciprocal mixing will effect system performance. Each nonlinearity will be fully described and system design parameters will be presented to meet all requirements. Frequency synthesizers including the latest phased lock loop techniques will be presented.The key parameters for various system types will be presented and a common receiver will be specified to meet the requirements. Commercially available receiver chips will be shown with their performance. Numerous transceiver design examples will be demonstrated.
• Nonlinear Effects, Frequency Synthesizers, Phased Lock Loops • Link Budget Design, Commercially Available Transceiver Elements • Complete System Design and Architecture of the Following Systems: GSM/EDGE, CDMA, Wideband CDMA, CDMA 2000, 802.11, Bluetooth • Multifunction Transceiver Design

Transceiver Architecture and System Design – Transmitter
Transceiver systems will be introduced including block diagrams, critical system parameters, multiple access and duplex methods, modulation types, and digital wireless terminology. The important transmitter parameters will be discussed and include: PAE, EVM, AM/AM, AM/PM, harmonics, intermodulation, and spectral regrowth. Digital and analog techniques to generate the modulated signals are compared. Modulator imperfections including calibrating techniques to mitigate the effects on system performance will be presented. Transmitter direct and dual upconversion systems will be compared with synthesis techniques for multicarrier complex signals. Transmitter spur location and techniques for all the various analog and digital formats will be shown.
• Transceiver System Introduction • Transmitter Block Diagram, Generation and Modulation of RF Signals • Modulator Imperfections and Calibration Techniques • Balanced Circuits, Direct and Dual-up Conversion Examples • Synthesis of Multi-Carrier Signals and Transmitter Spur Locations

Testing/Troubleshooting of Transmitter/Receiver Systems
Various transceiver measurement techniques including in channel as well as out of channel will be presented including trouble shooting techniques.
• Transmitter In-Channel Measurements: Channel power, occupied bandwidth, peak-to-average power ratio, complimentary cumulative distribution function, burst width, rise time, on-time, off-time, peak power, EVM, and phase/frequency error • Transmitter Out-of-Band Measurements: Spurious, harmonics • Factors Effecting Transmitter Impairments: Compression, incorrect filter coefficient, LO instability, I/Q amplitude/phase imbalance • Transmitter Impairments Trouble-shooting • Receiver In-Channel Measurements: SINAD, Sensitivity at specified BER, co-channel rejection • Receiver Out-of-Channel Testing: Spurious immunity, intermodulation immunity, and adjacent/alternate selectivity • Receiver Impairments and Detection Techniques: I/Q impairments, interfering tone/spur, incorrect symbol rate, baseband/IF filtering problem

Transmitter Architecture and System Design (cont´d)
• Transmitter Noise: Contributions and techniques to reduce noise to acceptable levels • Transceiver Filter Usage, Types, and Design Features • PA Transistor Types: Typical usage for the various systems • Efficiency Enhancement Techniques at Reduced Power Levels and Distortion • Reduction • Design Parameters Characteristics, Advantages, Disadvantages and Usages of Alternate Transmitter Types • Transmitter Distortion Reduction Techniques • Various Complete Transmitter Designs


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Course 64

Broadband Infrastructure, ATM Switching, High-Speed LAN Systems, The Internet Architecture, and Wireless/Mobile Technology
April 20-24, 2009. Barcelona, Spain
Challenges with Internet Access: The “Last Mile” Problem • Digital Subscriber Line Technologies • Passive Optical Networks (PONs) • Cable TV Architecture; DOCSIS • Broadband over Power (BOP) • Wireless Local Loops and WiMAX SDH WAN Technologies: Signal Hierarchy and Multiplexing • Logical and Physical Structure of SDH • Fiber Optic WAN Infrastructure • LEO and MEO Satellite Systems

Telecommunications and computer networking have undergone remarkable change over the last several years. The networks landscape has been forever altered by revolutionary developments in wireless, IP-convergence and security. This convergence phenomenon is best exemplified by the ITU’s initiative to define a Next Generation framework architecture based on emergent IP-related developments. The IP-based Internet offers the default architecture for all modern networking initiatives. Everyone with a career commitment to technologies that are affected by these events has little alternative but to embrace this revolution.

Telematix Institute, Burnaby, BC, Canada

The Internet Architecture
The previously unimaginable scale of Internet development and success has led to a wide-ranging initiative to convert all network-related services to this model - a process referred to as convergence. The elements of this core subject, combined with emerging applications, are the focus here.
Elements of The Internet Computing Architecture • Internet Protocol; Key Features and Dependencies • ICMP, ARP and Other Auxiliary Protocols • Transmission Control and User Datagram Protocols • Limitations of Current Versions of IP and TCP • Next Generation IP and TCP Real Time Service: Adapting IP for Multimedia • Quality of Service Issues • QoS; Integrated versus Differentiated Services • IPv6 ‘Flow’ and RSVP • Real Time Protocol • Multicast and Streaming Media Voice Over IP: Configuration Models • Voice Encoding and Packet Delay • Echo Control and Signalling • IPTV and IP Multimedia Systems (IMS)

Advanced LAN Systems and Extended Hub Architectures
LAN systems are the heart of modern networked environments – they are the basis of locally autonomous services, and universally, the point of connection to external infrastructure.The elements of modern, high capacity LAN connectivity are basis of this module.
• Network Timing and Control • Call Control Procedures • Multiplexing and Multiple Access • Bridged/Routed Connectivity • Network Reengineering Strategies • Extending Hub Architectures: Switching Hubs • Switched and Routed Connectivity • Virtual LANs; IEEE 802.1q and alternatives • Policy-Based Switching • Backbone Architectures

High Speed Desktop and MAN Technologies
We focus on extending the vision of LAN-connected systems to include solutions based on bigger, better and faster Ethernet architectures, and non-traditional solutions to this class of service. From there, we develop a vision of the MAN – its unique requirements and alternative solutions to the challenge of metro-scale networking.
Baseline Desktop Technologies: 100 Base-T (Fast Ethernet) • Switched 100 Base-T configurations • Gigabit Ethernet (IEEE 802.3z) • 10 Gbps Ethernet (IEEE 802.3ae) • 100 Gbps Ethernet Initiatives • IEEE 802.1p Frame Tagging • MAN Solutions Adapted from ATM • Dynamic Synchronous Transfer Mode (DTM) • Switched Ethernet in the MAN Other Technologies: Resilient Packet Ring (IEEE 802.17) • Fibre Channel and HIPPI • FireWire (IEEE-1394)

Mobile Computing, The Wireless Web, Security Challenges and the Relationship to the ITU Model for NGN
The individual wireless-related technologies (e.g. GSM, 3G mobile,WiFi and WiMAX) have much to offer, but the synergy of their integration into a seamless wireless infrastructure has even greater promise. Anarchy in the larger Internet and high profile security failures of wireless technology have led to a vital and growing interest in the essential elements of security. Lastly, we summarize the key elements of the ITU model for Next Generation Networks, and consider how the technologies covered in class relate to the ITU’s vision.
Mobile Computing: Mobile IP • Mobile Packet Data; GPRS, 3G Mobile and WCDMA • The Wireless Web; Adopting Streaming Media Services Wireless LANs and Bluetooth: IEEE Standards Summary • Practical WLAN Design and Configuration Models • MIMO and Ultra-Wideband (UWB) Developments • Ad Hoc and Mesh Networks • Bluetooth • Adapting WiFi (IEEE 802.11) to Community-Wide Applications • WiMAX (IEEE 802.16); Technology and Applications • Mobile Broadband Wireless Access (IEEE 802.20) MultiProtocol Label Switching (MPLS) Concepts • MPLS Relation to Quality of Service, RSVP and Tag Switching • Frame and Cell Mode MPLS • Generalized MPLS and Lambda Switching Network Management Automation: SNMP and the MIB • Web-Based Network Management Security Developments: The vital role of standards • Encryption Methods • Firewalls and ‘Deperimeterization’ Initiatives • Intrusion Detection and Prevention Systems • Wireless Security • Virtual Private Networks; IPSec, SSL, MPLS Reconciling the ITU NGN Architecture • A unified IP-Based Core Infrastructure • Access Network Services Based on Wired Telephony Infrastructure (xDSL-based) • Access Network Services Based on Cable Infrastructure (DOCSIS/Cablelabs Based) • Application Elements; VoIP, IPTV, etc.

Broadband Wide Area Networks, WAN and LAN
The WAN infrastructure has traditionally been the exclusive domain of the telephone industry, with their long-standing preference for synchronous technology and ATM. IP-oriented developments utilizing non-traditional core technology (e.g. wireless, cable TV plant, power distribution networks) are making serious inroads into the domain of the mainstream telecommunications carriers.The objective is to cover traditional WAN technologies and compare them to emerging alternatives.
Bandwidth-on-Demand: Limitations of traditional networks • Packet Switching • In-Band versus Out-of-Band Control • Congestion Control Modern Packet Networks: IP, ATM, DTM… • Virtual Paths, and Traffic Shaping • Classes of Service • Converging ATM and IP

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Course 59

March 9-12, 2009. Davos, Switzerland October 26-29, 2009. Barcelona, Spain

The expansion of information services in the last decade has affected the way we live and work. Notwithstanding dampened early unrealistic expectations, the Internet continues to grow faster than any other global infrastructure in history. Alongside the Internet, we have witnessed a phenomenal growth in wireless communications. Third Generation (3G) cellular service is being launched in various parts of the globe. Metropolitan area networks supported by the newly established IEEE 802.16 /WiMax standards are starting to appear in cities and towns around the world. Looking forward, UMTS Long Term Evolution (LTE) is being specified and it will provide a new physical layer and higher layer protocol architecture for the fourth generation (4G) of mobile communication systems. Increasingly, the driving force behind future growth in the telecommunications industries is seen to be broadband wireless access to the Internet and wireless data connectivity to mobile users. Orthogonal Frequency Division Multiplexing (OFDM) and Multiple Input Multiple Output (MIMO), which are increasingly seen as the physical layer technologies capable of supporting the ever-increasing appetite for capacity and data rates, are the topic of this course.

OFDM for Multiple Users
We now focus on multicarrier schemes for multiple users. Design tradeoffs and complexities are discussed. Performance metrics of the course are extended to the multiple user case. System design issues such as intra-user interference are addressed.


ALEXANDER HAIMOVICH • Peak-power Problem: Harmonic distorNew Jersey Institute of tions, techniques for reducing PAPR, single-carrier frequency-domain equalTechnology, Newark, USA ization, clipping • Multiple Access Techniques: OFDMA, MC-CDMA • Multiuser Diversity • Applications: Cognitive wireless networks (IEEE 802.22)

MIMO Principles
The main concepts in exploiting the spatial dimension in wireless communications and the use of multiple antennas is discussed in depth for free-space and multipath channels. Multipath scattering is the enabler to huge communication gains. Key concepts such as spatial diversity and spatial multiplexing are discussed in depth. Systems with multiple antennas at the transmitter and at the receiver are contrasted.
• Properties of Adaptive Arrays, Beam Pattern, Array Gain, Transmit and Receive Arrays • MIMO Channel Models, Channel Estimation • MIMO Capacity, Channel Known at the Transmitter

The course focuses on two key wireless technologies, OFDM and MIMO, and it contains details on the applications of these technologies to new wireless systems such as WiMax and UMTS LTE. The course seeks to enable participants to acquire a thorough understanding of the underlying principles of OFDM and MIMO and their relation to the medium in which they operate. Design principles and tradeoffs are discussed in detail. Matlab software is used to demonstrate key concepts. Participants may use the software for hands-on analysis and simulations. At the end of each section, participants have the opportunity to work through review problems that reinforce key notions introduced in the section. The course will prepare participants to: • Understand the limitations of current wireless systems as drivers for the development of emerging technologies. • Become familiar with characteristics of the wireless transmission medium and use them to motivate the development of new wireless technologies. • Become knowledgeable with the salient features of key new wireless technologies, including design principles and performance tradeoffs. • Be able to appreciate the latest and emerging technologies in this fast-moving field.

MIMO Systems and Techniques
Multiple transmit antennas can be exploited to obtain diversity gains, spatial multiplexing gains, or both. Space-time codes combine the benefits of spatial diversity and coding gains.We discuss examples of space-time codes, their design, performance, and complexity and their emergence in various standards. This is followed by systems and techniques that focus on spatial multiplexing. The availability of channel state information (CSI) at the transmitter supports MIMO systems with enhanced data rate performance. Techniques utilizing CSI feedback from the receiver are presented.
• Diversity with Receive Antennas: MRC, optimum combining, correlated channels, Matlab examples • Diversity with Transmit Antennas, Alamouti’s Scheme, Space-time Block Codes, Matlab Examples • Transmit Diversity Schemes for 3GPP and 3GPP2 • Phase Sweeping, Delay Diversity, Cyclic Delay Diversity • Spatial Mutliplexing Systems: BLAST, layered schemes, Matlab examples • Closed Loop Systems: Diversity systems, spatial multiplexing over eigenmodes • MIMOOFDM

Multicarrier Technologies
We begin with the characteristics of the wireless channel. Fundamental concepts of OFDM are explained in the context of performance over multipath fading channels.
• OFDM: FFT-based OFDM, power spectrum • Optimizing OFDM Transmission: Guard time, cyclic extension, pulse shaping, adaptive modulation, system design example • Synchronization and System Imperfections: Preambles and pilots, time synchronization, frequency offset synchronization, phase noise, channel estimation, equalization, Matlab examples • Channel Coding for OFDM: Convolutional coding, puncturing, performance over frequency-selective channels, Matlab examples

UMTS LTE and WiMax Applications
OFDM and MIMO will serve as the physical layer of two key technologies for future mobile communication systems: UMTS LTE and WiMax. In this part, we will discuss the role of OFDM and MIMO in the evolving standards for LTE and WiMax. LTE is the 4G evolution of cellular systems, while WiMax is a technology that is expected to deliver last mile wireless broadband access.
• Background to LTE: HSPA Release 7 • LTE Design Goals • Frame Structure • Downlink MIMO Modes • Physical Resource Block • LTE Oplink: Single carrier (SC) – FDMA • WiMax: Overview of MAC layer, MAC protocol data units • Frame Structure • Ranging • Quality of Service Classification • ARQ • Scalable OFDMA • Adaptive Modulation and Coding • OFDMA Channelization: PUSC, FUSC, AMC, Matlab example • Multiple Antenna Technology in WiMax


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Course 46

May 25-28, 2009. Copenhagen, Denmark

Even as Third Generation (3G) cellular service is being deployed, the wireless community is busy designing the fourth generation (4G) of wireless cellular systems. While the definition of 4G has not been finalized, there is a consensus that the expected data rate requirements will be an order of magnitude higher than 3G. Current technologies based on TDMA/CDMA are not capable of handling the wideband signals required to reach the 4G target data rates. Two technologies working in tandem are emerging as likely candidates for 4G implementations. Orthogonal frequency division multiplexing (OFDM) has already proved successful in providing high speed communication over wireless LANs. OFDM greatly facilitates handling wideband signals, but, by itself, it cannot deliver the data rates targeted by 4G. Multiple input-multiple output (MIMO) is seen as the key technology to complement OFDM to support high data rates in future wireless systems. MIMO schemes enable a variety of functions including multi-stream transmission for high spectrum efficiency, improved link quality through diversity mechanisms, and adaptation of radiation patterns for signal gain and interference mitigation through adaptive beamforming.

Receive and Transmit Diversity
Diversity mechanisms are commonly applied to overcome fading over wireless channels. We discuss the use of antennas at the receiver and at the transmitter to the design of diversity systems. Space-time codes are introduced. The PROFESSOR concepts of coding gain and diversity ALEXANDER HAIMOVICH gain are shown to determine the perNew Jersey Institute of formance of space-time codes. Technology, Newark, USA We discuss examples of space-time codes, their design, performance, and complexity, and their emergence in wireless cellular standards.
• Diversity Concept: Time, frequency, and spatial diversity • Diversity with Receive Antennas: MRC, equal gain, selective, and optimum combining, correlated channels • Channel Estimation Error • Diversity with Transmit Antennas, Alamouti’s Scheme, Space-time Block Codes • Transmit Diversity Schemes for 3GPP and 3GPP2 • Phase Sweeping, Delay Diversity, Cyclic Delay Diversity


This course covers MIMO communications on all its aspects. Simple examples designed to reinforce the concepts, supplement the material. Design principles and tradeoffs are discussed in detail. Matlab software is used to demonstrate key concepts. Participants may use the software for hands-on analysis and simulations, and work through review problems that reinforce key notions introduced in the section. Application examples include 3G and beyond 3G (B3G) cellular systems. The last day of the course presents in detail the application of MIMO to 3GPP LTE and WiMax. The course will prepare participants to: • Understand the concepts of adaptive beamforming, i.e., the use of antenna arrays to control radiation patterns over line of sight channels • Grasp the phenomenology and theory that underlie the dramatic increases in data rates enabled by MIMO • Become familiar with the fading characteristics of the wireless transmission medium and the ability of diversity systems to mitigate fading effects • Understand the concept of spatial multiplexing and the various schemes for its implementation • Learn about major system applications of MIMO to 3G and 4G cellular communication systems • Become familiar with the application of MIMO to single user and multiuser communication

MIMO Systems, OFDM, and Multiuser MIMO
In this part, we focus on the capability of MIMO systems to support the transmission of multiple streams of data. Specific schemes that implement spatial multiplexing are discussed. The effect of channel state information on the performance of MIMO systems is discussed. The availability of channel state information at the transmitter can support higher data rates, but requires a feedback mechanism from the receiver. We discuss the advantages of channel state information at the transmitter and the tradeoffs between feedback overhead and performance. We present the basics of OFDM technology, and discuss MIMO OFDM systems. Advanced concepts that optimize system performance with respect to multiple users are introduced.
• Spatial Mutliplexing Systems: BLAST, layered schemes, • Closed Loop Systems: Diversity systems, spatial multiplexing over eigenmodes • MIMO Applications: Standardization in 3GPP and 3GPP2 • OFDM Basics, Cyclic Prefix, Rate Adaptation, Channel Equalization, OFDMA • Multiuser Communication and Diversity • Multiuser MIMO: Successive interference cancellation, superposition coding, and WiMax proposal

UMTS LTE and WiMax Applications
OFDM and MIMO will serve as the physical layer of two key technologies for future mobile communication systems: LTE and WiMax. LTE is the 4G evolution of cellular systems, while WiMax is a technology that is expected to deliver last mile wireless broadband access. Both 3GPP LTE and WiMax technologies make extensive use of MIMO. We will discuss requirements for the two systems, followed by a description of the physical layer, which is expected to be based on OFDMA. MIMO schemes under consideration for 3GPP LTE and already standardized for Mobile WiMax IEEE 802.16e will be described in detail.
• Background to LTE: HSPA Release 7 • LTE Design Goals • LTE Downlink; MIMO Modes • LTE Uplink; MIMO Modes • MIMO OFDM for LTE • WiMax Network Architecture • OFDMA Physical Layer; Scalable OFDMA • Adaptive Modulation and Coding • OFDMA Channelization: PUSC, FUSC, AMC • Multiple Antenna Technology in WiMax • MAC Layer, MAC Protocol Data Units • Frame Structure • Ranging • Quality of Service Classification • ARQ

MIMO Channels and MIMO Capacity
We start with a quick review of communications over line of sight and fading channels. Antenna arrays are introduced. Beamforming and adaptive antenna pattern adaptation are presented. The properties of distributed arrays are discussed. From the line of sight channel, we move on to the fading channel. In this part, we introduce properties of the MIMO channel, and present standardized models. The discussion underscores the multipath MIMO channel as the enabler to the high spectral efficiency MIMO communications. Fundamental properties of MIMO communication are introduced and explained through the concept of channel capacity.
• Properties of Adaptive Arrays, Array Gain, Beampattern, Transmit and Receive Arrays • Distributed Arrays • MIMO Channel, Physical, Analytical, Deterministic, and Stochastic Models • Standardized Models: COST, 3GPP, WINNER, IEEE 802.11n, SUI Models for WiMax • MIMO Capacity, Channel Known at the Transmitter • Capacity of Deterministic and Fading Channels

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Course 41

April 1-3, 2009. Barcelona, Spain September 28-30, 2009. Cambridge, UK

Wireless broadband Internet access providing IP based services to mobile users is growing rapidly worldwide. State-of-the-art systems cannot support this increasing demand for higher bit rates at reduced cost and do generally not meet future requirements. 3GPP Long Term Evolution is the new UMTS standard making use of latest technologies such as OFDMA based access, frequency based scheduling, MIMO and higher order modulation. With LTE substantial gains regarding capacity, peak data rates, user and control plane latency and deployment cost can be expected, while minimizing terminal complexity. The scalable OFDM technology allows a flexible spectrum allocation in existing and new frequency bands. LTE is the natural evolution of GSM/EDGE and UMTS/HSPA network technologies making 3GPP standards competitive over other cellular standards in the next decade. 3GPP does not only define a completely new air interface called Evolved UMTS Terrestrial Radio Access Network (EUTRAN), it also works on a System Architecture Evolution, the Evolved Packet Core (EPC). This is based on a flat, simplified all IP based architecture with a reduced number of network entities, a new Quality of Service (QoS) concept and the support of seamless mobility between heterogeneous access networks. 3GPP is currently working on the completion of the standard. Extensive trials are under preparation. Service start is expected to be around 2010.

After an overview of state-of-the-art 3G technologies and market, the drivers and requirements for Long Term Evolution are derived. An introduction to the downlink and uplink Physical Layer will be given, namely OFDMA and SC-FDMA (DFT-FDMA). After a short recap of MIMO techniques we will get acquainted with the details of the LTE numerology and physical layers specification.

Chief Technical Officer, Nomor Research GmbH, Munich, Germany

• Market and Technology Drivers • Current and Upcoming 3G Cellular Technologies (UMTS/WCDMA, HSDPA, HSUPA, Wimax, CDMA2000) • Requirements for Future Systems • 3GPP Structure and LTE Standardization Schedule • OFDMA Downlink and SC-FDMA Uplink Transmission • LTE Resource Allocation and Scheduling Algorithms • Fundamentals of MIMO Antenna Technologies • Physical Layer Numerology and Processing Chain

Subsequently the specifics of the LTE physical layer procedures are introduced, particularly different means of link adaptation. After having taken a look at LTE performance figures the different physical layer signals and channels will be introduced including layer 1/2 control signaling.
• Uplink and Downlink Channel Estimation Based on Reference Symbols • Link Adaptation, Adaptive Coding and Modulation, HARQ and UL Power Control • Terminal Capabilities and LTE Performance Analysis • OFDMA Interference Analysis and Interference Coordination Techniques • Downlink Physical Signals and Channels (SCH, PBCH, PDSCH, PMCH) • Uplink Physical Signals and Channels (PRACH, PUSCH) • Uplink Channel Sounding and Channel Quality Reporting (CQI) • Layer 1/2 Control Signaling (PCFICH, PHICH, PDCCH, PUCCH)

This course provides a detailed understanding of the physical layer, the protocol and the architecture of LTE access networks as defined in the 36-series of 3GPP specification Release 8. The course introduces basic principles of the OFDM/SC-FDMA based physical layer and related procedures. In particular it covers uplink and downlink link adaptation and signaling, radio resource management and scheduling algorithms. Furthermore, a good understanding of the radio and network protocols of LTE/SAE is given. The RRC, PDCP, RLC and MAC layers are explained in detail and the different network entities and interfaces of the Evolved Packet Core as well as the underlying QoS concept is introduced.

The course is meant for engineers that already work on LTE and want to get an overall system overview as well as for those who have technical background in 2G/3G wireless communication and are interested in future technologies such as Long Term Evolution. Therefore, the course will be beneficial for system engineers, for research and development engineers as well as people from LTE product planning and technical marketing.

An overview of the LTE/SAE network architecture and related interfaces is presented, followed by a thorough discussion of the radio protocol stack. Furthermore LTE procedures like cell search, random access, connection setup, handover procedure etc., are introduced.
• LTE/SAE Network Architecture and Functional Split • QoS Architecture and Bearer/Label Concept • S1 and X2 Interface Transport Protocol • User and Control Plane Architecture • Medium Access Control, Radio Link Control, Radio Resource Control • Logical Channel And Transport Channel Structure • Downlink Synchronization, Cell Search and Random Access • Broadcast Channel and Overview of System Information • Handover Procedure and Timing Advance • Introduction to LTE Advance and 4G


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Course 49

June 8-12, 2009. Cambridge, UK October 26-30, 2009. Barcelona, Spain
Fixed Mobile Convergence (FMC) • 4G: Long Term Evolution and System Architecture Evolution (LTE/SAE)

We are on the threshold of Fourth Generation (4G) wireless networks that will define a wireless century characterized by pervasive broadband wireless communications and networking. This transformation is being driven by an explosion in bandwidth-intensive multimedia applications (e.g., mobile television service), as well as the expanded technological capabilities of personal communications systems, air interface technology (LTE, WiMax, 802.11n), IP networking, and new architectures, such as mesh networking, that will deliver the freedom of anywhere, anytime, multimedia wireless communications. In this course we focus on the enabling 4G technology to realize universal high speed wireless networks that seamlessly interface with wireline backbone networks, under the control of IMS (IP Multimedia Subsystem).

Foundation Communications Technologies for 4G – the Wireless Channel
• The Wireless Environment • Propagation Basics: Carrier Frequency, RF spectrum, wavelength • Antennas • The Gaussian Channel • Path Loss, Multipath, and Shadow Fading • Fading Multipath Channels, Delay Spread, Rayleigh and Rician Channels, Doppler Shift • Propagation in Macrocells and Microcells

University of South Florida, Tampa, FL, USA

Foundation Communications Technologies for 4G
• Modulation Methods: OFDM, QAM • Channel Codes: Convolutional and Turbo Codes • Spatial Domain Processing (Smart Antennas, MIMO) • Time Domain Processing: MLSE Viterbi Equalization • Speech and Video Processing • Multiple Access Technologies: TDMA, CDMA, OFDMA

After a comprehensive review of current wireless market drivers, we present the underlying core communications technology advances that are enabling 4G networks, including OFDM (Orthogonal Frequency Division Multiplexing), MIMO (Multiple Input Multiple Output) smart antennas, and cognitive radios. These new technologies, when combined with significant networking technology advances in security/encryption, mobile IP, MPLS/IP networking, IPv6, mesh networks, and IMS-based fixed mobile converged (FMC) networking, provides the foundation for emerging 4G networks such as 3.5G HighSpeed Downlink/Uplink Packet Access (HSDPA/HSUPA), 4G Long Term Evolution (LTE), broadband wireless 802.16/WiMax (Worldwide Interoperability for Microwave Access), Metropolitan Area Networks (MANs), 802.11/WiFi Local Area Networks (LANs), and the Wireless Internet based on the IP Protocol. We describe how these systems will evolve into 4G networks, the most prominent being the UMTS 3GPP Long Term Evolution (LTE) and System Architecture Evolution (SAE), often referred to as LTE/SAE, which will provide IP-based pervasive, adaptive broadband wide area wireless networking. The larger 4G picture will include the smooth interworking of LTE/SAE with other WAN networks, such as WiMAX, personal area networks such as WiFi, Femtocells, Bluetooth, Zigbee, Ultrawideband, and Sensor Networks, as well as other advanced applications and services, e.g. RF ID and mesh networking, and Fixed Mobile Convergence (FMC). The unifying signaling and control architecture is the IP Multimedia Subsystems (IMS), which service providers have embraced as the key enabler of wireless and wireline converge and many advanced services. It is expected that IMS will set the stage to achieve FMC and thus dramatically enhance subscriber experiences while creating compelling new integrated service bundles for the converged wireless and wireline network.

Foundation Networking Technologies for 4G
• Cellular Systems Engineering: Frequency reuse, sectorization, and hierarchical systems for TDMA, CDMA, and OFDMA • Networking Architecture and Protocols • Security and Encryption • Wireless Backhaul: MPLS and pseudowire networking • Femtocells • Mobility Management, Handoffs, Channel Assignment, and Signaling • Mobile IP

Wireless LANs (WiFi/802.11)
• Overview of the LAN Industry: Market and technology • Service Requirements • IEEE 802.11 Standard(s) • Centralized and Distributed Architectures • Ad-hoc Packet Networks • PHY and MAC Layers • Bluetooth, Zigbee • Mobility Management and Routing Protocols • Power Conservation, Security, Network Performance

3G Systems: IMT-2000/UMTS/WCDMA/CDMA-2000
• 3G Wireless Standardization: UMTS, WCDMA and CDMA-2000 • IP Multimedia Subsystem (IMS): Enabler of value-added wireless networks • Network Model and Architecture • Resource Management • UMTS Bearer and Service Architecture • Security in 3G • UMTS: Radio communications, Radio Access Network (UTRAN), core network, services, security, protocols • Quality of Service (QoS), UTRAN, IP packet access, FDD/TDD modes • CDMA 2000 • TD-SCDMA • Beyond 3G

Emerging 4G Systems
• HSDPA, HSUPA, and HSPA • WiMax • DVB-H – Mobile Video • 3G Long Term Evolution (LTE) and System Architecture Evolution (SAE)

Overview of Wireless Communications and Networking
Overview emphasizing the important role of the cellular concept and the various means of increasing capacity of wireless systems. Topics that will be covered include:
• What is 4G? • Market, Technology Drivers, and Evolution of Wireless • The Cellular Concept and Technology Platform: Frequency reuse, handoffs, signaling, Mobile Switching Center (MSC) • Internetworking with Wired Systems • Digital Radio Elements and Strategic Technologies: Modulation, channel coding, equalization, and smart antennas • 2G Wireless Systems: GSM • Network Engineering: Traffic loading and performance • Satellite-Based Systems and GPS • Wireless LANs/PANs: 802.11 (WiFi), Bluetooth, Zigbee, Ultra Wideband (UWB) • Wireless Loop/ Broadband Wireless: 802.16 (WiMax), 802.20, • 3G/3.5G Wireless Systems: UMTS/WCDMA, CDMA2000, HSDPA, WiMax • IP Multimedia Subsystem (IMS) and

4G – The Wireless Century
• LTE/SAE • Extended 4G Vision • Ultra Wideband (UWB) Radio • Cognitive Radios • Sensor Networks • Mesh Networks • RF ID • Fixed Mobile Convergence (FMC) • The Wireless Century

This course provides thorough coverage of the key market, architectural, and technological concepts driving 4G wireless networks, many of which are developing now. Also presented are a detailed description of the main features of modern wireless systems and standards. The course is meant for product planners, system architects and design engineers, who are new to wireless, as well as those who are experienced in wireless and wish to learn the leading-edge trends and technologies that will create 4G networks.

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Course 58

March 9-13, 2009. Davos Switzerland October 26-30, 2009. Barcelona, Spain Shannon Information Theory
Shannon information theory has led us to the concepts of multitone modulation (DMT), OFDM, and adaptive modulation and coding. DMT and OFDM are the standards for the IEEE 802.11 and 16 broadband wireless systems, and 3G-LTE, as well as ADSL and VDSL. We present an in-depth discussion of OFDM, OFDMA, Scalable OFDMA and SC-FDMA.
• Introduction to Shannon Information Theory • Channel Capacity for Ideal and General Gaussian Channels

Modern digital modulation techniques and multiple access techniques are basic building blocks of the physical or radio interface of all digital communication systems. OFDM, OFDMA, SOFDMA, SC-FDMA, DMT, MIMO and BLAST, and adaptive modulation and coding methods are becoming very important parts of the implementation of modern communications systems, especially for broadband wireless communications.These concepts are being utilized in new mobile and broadband wireless systems including 3G-LTE, Mobile Wi-Max (IEEE 802.16) and Wi-Fi (IEEE 802.11) systems, as well as xDSL systems, to greatly improve both bandwidth and power efficiency.


We will describe the digital modulation techniques used in the major wireless and wireline communication systems in use today and those planned for the near future. We begin with a discussion of the major communications channels including the fading channel of wireless communications. We continue with a description of the classic modulations, e.g., QPSK, QAM and GMSK. We will also discuss the important multiple access techniques, with special emphasis on OFDMA and CDMA. New techniques, including SOFDMA, SC-FDMA, OFDM-MIMO, Alamouti space-time coding, iterative techniques, and adaptive modulation and coding, are also described. We will also discuss the information theory limits on communications.

Tel Hai College, Israel, Columbia University, New York, USA Multitone-DMT • Discrete Multitone (DMT) – Implementation • The Twisted Pair Channel • Multitone over the Twisted Pair Channel (ADSL and VDSL)

OFDM-Orthogonal Frequency Division Multiplexing
• OFDM – for Broadband Wireless Communications • Adaptive Modulation and Coding Techniques • Physical Interfaces of IEEE 802.11 (Wi-Fi), IEEE 802.16 (Wi-Max and Mobile Wi-Max) and 3G-LTE • OFDMA as a Multiple Access Technique • Scalable OFDMA • SC-FDMA (Single-Carrier FDMA-3G-LTE) • OFDM-MIMO-Wi-Media Standard • UWB-OFDM

Trellis Coding and The Viterbi Algorithm
Trellis coded modulation concepts, including a discussion of the Viterbi Algorithm. Interleaving for improving the performance of modulations on Rayleigh fading channels.
• The Viterbi Algorithm (VA) • Ungerboeck Trellis Coding • The VA Equalizer • Interleaving for Rayleigh Fading

Rayleigh Fading Channel and Baseband Nyqvist Signaling
We begin with a description of the channel models for mobile and/or wireless and wireline systems. This is followed by discussions of Nyquist baseband signalling, as well as ISI and linear equalization.
• System Model-The Channel • The Multipath Channel (Rayleigh, Frequency-Selective Fading) • Twisted-Pair Channel • Brief Review of Fourier Transform, Power Spectral Density, White Noise • Nyquist Signaling • ISI, Optimum Filtering, Linear Equalization • Partial Response Signals-Why the MLSE and the Viterbi Algorithm?

A topic of increasing importance is the turbo-coding (iterative decoding) concept and its use in areas such as antenna diversity, equalization and OFDM. • Turbo Coding • Iterative Decoding Techniques
• Turbo-Equalization • LDPC Codes

Capacity of Rayleigh Fading Channels
Shannon’s work has been updated to include bounds on the performance of Rayleigh fading channels. This work led to the concept of MIMO and space-time (Alamouti) coding. • Bounds on Communications for Fading Channels • OFDM-MIMO-Coding • Space-Time Coding • Alamouti Coding • Multi-User Diversity Techniques

Signal Space, Optimum Detection
The concept of signal space is used to define the classical modulation techniques and derive the optimum detectors.
• Signal Space • BPSK, QPSK, MPSK, QAM, BFSK and MFSK • Optimum Detection of Binary Signals • Matched Filter

CPM Type Modulations
CPM signals (e.g., GMSK) are constant envelope, bandwidth efficient modulations, suitable for use with nonlinear power efficient, transmitting power amplifiers. • Continuous Phase Modulation (CPM)
• Gaussian MSK (GMSK) • Tamed FM (TFM) • Generalized TFM (GTFM) • Adjacent Channel Crosstalk in CPM Signals

The Rayleigh Fading Channel and Antenna Diversity
The performance of modulations, transmitted over Rayleigh fading channels, followed by the concept of space diversity (BLAST and MIMO), used to greatly improve spectral efficiency.
• Detectability Performance over Rayleigh Fading Channel • Classic Antenna Diversity (SIMO) • MIMO • BLAST

Non-Coherent Detection
• DPSK • FM Detection of CPM Signals-Bluetooth, DECT

MSK-type Signals and M-ary Signals
• QPSK, SQPSK, π/4 – QPSK, EDGE “8PSK” • MSK-type (MSK, SFSK) Signals • Adjacent Channel Interference (ACI)

Cellular Communications – Radio or Physical Interface
Multiple access techniques, with emphasis on CDMA and WCDMA. We describe the radio interfaces of the IMT-2000 WCDMA system, as well as GSM, IS-136, GPRS, 1xEV, EDGE and the physical interface of IS-95.
• FDMA • TDMA • GSM and IS-136

QPSK, SQPSK, and MSK are essentially constant envelope modulations, which are used in many satellite and wireless systems.

M-ary signals are used in many systems, e.g., analog modems, ADSL, VDSL, microwave radio, and in the EDGE-based 3G Physical Interface Standard.
• Optimum Detection of M-ary Signals • MPSK • QAM-Nyquist Signaling • MFSK

CDMA and WCDMA Systems
• The RAKE Receiver • Pseudo-Random Sequences • Power Control • Intra and Inter-Cell Interference and Capacity • IS-95 Physical Interface • WCDMA Physical Interface: Walsh and OVSF functions

UWB Radio, DFE and Tomlinson Filtering (Time-Permitting)


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Course 81

March 30 – April 3, 2009. Barcelona, Spain September 28 – October 2, 2009. Cambridge, UK

Wireless communication systems were designed primarily for voice services. First generation cellular systems were analog in nature, thus unsuitable to data transmission. The driving force for the second (digital) cellular generation was increased capacity to accommodate the high demand for new customers, so that data services came just a fall-out of the digital technology, and were limited to very low data rates. The explosion of Internet usage, with the ever-increasing demand for the downloading of large bulk of data in multimedia services, on one hand, and the gradual predominance of wireless communication over the wired one, made second-generation cellular systems fully inadequate. For this reason, third generation was designed focusing on Internet, rather than voice, services, and this will be even more the case for the generations to follow. The high data rates and severe limitations in the available bandwidth devoted to cellular services, force wireless communication systems to face ever increasing challenges on severe bandwidth and energy constraints. The future of wireless communications depend on the possibility of fully exploiting the available bandwidth by increasing the efficiency of its use. Moreover, the time-varying characteristics of the wireless channel, and its frequency selectivity induced by the multipath fading, pose severe challenges to the system designer in order to cope with the high quality of service required for multimedia applications. Recent tools like adaptive coding and modulation, multi-antenna transmitter and receiver (MIMO), turbo and LDPC codes, iterative co-decoding and reception techniques, based on the turbo principle, are revolutionizing the of digital communication.

Linear Channel Impairment and Adaptive Equalization: The Nyquist Criterion to Avoid Intersymbol Interfer-ence • Linear and Decision Feedback Adaptive Equalization • Maximum-Likelihood Sequence Receiver: The Viterbi processor The Wireless Communication Channel: The Free-Space PROFESSOR Propagation Equation • Antenna Gain and Effective Area • Impairments of Real Radio SERGIO BENEDETTO Channels • The Multipath Fading Channel: Politec. di Torino, Italy Frequency and time selectivity • The Taxonomy of Fading Channels Constraints Imposed by the Fading Channel on Modulation Schemes: From QPSK to Offset-QPSK to MSK: Nonlinear impairments and interchannel interference • The π/4-QPSK Modulation Constant Envelope, Continuous Phase Modulation: MSK, Full and Partial Response CPM • GMSK, SFSK • Coherent and Non-coherent Receivers for CPM Signals Performance of Digital Modulation over the PROFESSOR Fading Channel GUIDO MONTORSI Modulation Schemes Adopted in Wireless Politec. di Torino, Italy Communication Standards Computer Session: Linear, Decision-Feedback Equalizer and Maximum-Likelihood Sequence Receivers • CPM Spectra and Receiver

Channel Coding – A Taxonomy
Block Codes: Linear Block Codes • Detection and Correction Capability • Design Parameters • Cyclic Block Codes • BCH and ReedSolomon Codes • Performance of Algebraic Hard Decoding of Block Codes • Performance of Soft Decoding of Block Codes Convolutional Codes: Trellis Description • The Viterbi Decoding Algorithm Interleaving for the Bursty Channel. Concatenated Codes Turbo Codes: Maximum-Likelihood Performance • Design • Iterative Decoding Algorithm • Performance • Practical Implementation: DSP, FPGA, VLSI Low-density Parity-Check Codes: Regular and Irregular LDPC Codes • Iterative Decoding Algorithm

This course focuses on techniques to reliably communicate digital information over the wireless channel. It provides the fundamental trade-offs between bandwidth, energy and performance, and explains the main tools available to improve the performance of digital wireless transmission, such as bandwidth-efficient modulation schemes, MIMO and space-time coding, turbo and LDPVC codes, iterative demodulation and decoding, carrier and clock synchronisation. A unique feature of the course is the focus on the ”how” and ”why” (as opposite to the ”how” only) those techniques have been choosen at the standardization level. Each day will end with a software-lab session, in which C-language programs implementing the main algorithms described during the day will be explained, used, and made freely available to course attendees.

Iterative Techniques
Turbo Iterative Decoding Algorithm: A heuristic Justification of the Iterative Algorithm • Optimum and Sub-Optimum SISO Algorithms • Additive Version of the SISO Algorithm Message-Passing Decoding Algorithm for LDPC Codes Practical Implementation Issues: Degree of parallelism, fixed-point implementation Bandwidth and Power Efficient Codes: Trellis-Coded and Turbo-Trellis-Coded Modulation Computer Session: The Iterative Turbo Decoding Algorithm and the Message Passing LDPC Decoding Algorithm

Wireless Communication – A Bit of History
The Limits Imposed by Information Theory to Communication Systems: The Shannon Theorem • The Rate-Distortion Capacity of Additive White Gaussian Noise and Fading Channels • The Minimum Signal-to-Noise Ratio vs. Bandwidth Efficiency for Reliable Communication

Access Techniques: CDMA and MIMO
Multi-User Detection: Optimal and Sub-Optimal Detectors • Turbo Multi-User Detection Single User MIMO: Fundamentals of Wireless Channels • Performance of Fading Channels • Diversity • Space Diversity: SIMO, MISO • Channel Capacity • Fixed Channel • Slow and Fast Fading Channels • Point-to-Point MIMO • Multipath Fast Fading Channel • DiversityMultiplexing Trade-Off Multi User MIMO: Uplink-Downlink Duality Principle and Capacities Space Time Codes: Block and Convolutional ST Codes • Orthogonal and Quasi-Orthogonal ST Codes Computer Session: TCM and ST Codes Bounds

M-ary Coherent Modulation: QPSK and M-PSK Modulation • M-QAM Modulation • Optimum Coherent Receivers • Differential Demodulation of PSK Signals • Orthogonal Frequency Modulation Modulation Schemes on the Performance Plan: Spectral Efficiency versus Signal-to-Noise Ratio per Information Bit • Practical Applications of the Various Modulation Schemes Carrier and Symbol Synchronization in Digital Transmission Computer Session: Capacity Evaluation of Various Channels by Analysis/Simulation

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Course 21

April 20-23, 2009. Barcelona, Spain October 12-15, 2009. Copenhagen, Denmark Singly Curved Array Antennas
Their characteristics are discussed, using waveguide-fed apertures and microstrip-patches as examples. The focus is on mutual coupling and its effect on radiation characteristics.
• Mutual Coupling vs. Surface Shape • Embedded Element Patterns • Dielectric Radome Effects

The demand for evermore-sophisticated information from communication and radar systems leads to concomitant requirements on antenna performance. Conformal array antennas and digital beamforming are emerging technologies that can meet these demands. Conformal arrays, i.e. array antennas on curved surfaces, are suitable for integration on various vehicles: cars, aircraft, satellite bodies, etc. They can provide wide angular coverage, which makes them attractive for several communication and surveillance applications. With modern high-density packaging of microelectronic components a complete antenna system can be made as a thin multilayer design, a “smart skin” . Digital beamforming is a powerful technique to enhance antenna performance. DBF arrays digitize the received signals at the element level, thus preserving the total information available at the aperture, and then process these signals in the digital domain to form the desired beams. Microwave ICs, highspeed digital electronics and signal processors are now making DBF practical in many applications such as fast adaptive interference rejection, high resolution direction finding, ultra-low sidelobes, and various forms of adaptive space-time processing, both for communication and radar (incl. MIMO systems).

Doubly Curved Array Antennas
• Polarization and Element Distribution • Mutual Coupling and Radiation Properties

Consultant, Lars Microwave, Gothenburg, SE

• Cross Polarization Effects, Definitions • Sources of Cross Polarization in Curved Arrays • Controlling Cross Polarization

Analog Beamforming (ABF)
ABF and beam scanning principles for conformal array antennas are presented. Solutions for commutating the active sector as well as beam steering and multiple beam generation for circular and cylindrical arrays are discussed. • Feed
Networks, Matrix Feed Systems • Quasi-Optical Feeds

Ericsson AB, Gothenburg, SE


This course spans a range of technologies significant for the development of advanced antenna systems. Arrays on curved surfaces are compared with traditional planar arrays. Practical conformal array configurations are presented taking examples from base stations, radar, and satellite communication applications. Basic DBF systems are contrasted with analog beamforming systems. Typical DBF applications, their components and system architectures, are reviewed. We discuss applications where both DBF and conformal antenna technology are likely to be combined in future antenna systems.

Conformal Array Synthesis and Design
Pattern synthesis is just the starting point in a design problem. We include mechanical design aspects and mutual coupling effects.
• Conformal Array Shape Optimization • Pattern Synthesis: Linear vs. circular arrays • Accounting for Mutual Coupling

Conformal Array Antenna Scattering
Radar Cross Section (RCS) characteristics of conformal antennas are presented, incl. scattering vs. radiation performance trade-off.
• Scattering Cross Section • Impedance Load Effects and Curvature Effects

Consultant, S4 Inc, Hanscom AFB, MA, USA

Conformal Array Antennas
Basic concepts are reviewed to establish a common understanding of important characteristics and definitions. Array antennas in general are discussed, starting with linear and planar arrays.
• Radiation Mechanisms, Antenna Impedance • Mutual Coupling Effects, Bandwidth, Beam Steering Performance • Applications

Demonstration of Analysis and Design
• Theoretical Design Using Software Tools • Practical Design Examples

Digital Beamforming (DBF): System and Components
A generic DBF receiver system and the effects of the subsystems on overall system performance are discussed. Basic system parameters are defined and present commercial component performance indicated. • Review of Sampling Theory and Channel Capacity • Receivers,
A/D Converters, Digital Beam Former, Beam Controller, Calibration Network • DBF in the Transmit Mode, Direct Digital Synthesis (DDS)

Circular Array Antennas
The circular array is a building block of many conformal array antennas, arrays on cones and cylinders. We give examples of typical performance based on computer simulations. Phase modes are a tool for analysis and design. Omnidirectional patterns, pattern bandwidth, and suppression of spectral harmonics are treated. • Phase Modes and
Pattern Characteristics • Suppression of Harmonic Radiation

Typical DBF Applications
DBF offers several unique capabilities:
• Review of Matrix Algebra. • Open- Loop Adaptive Interference Suppression: Various adaptive criteria, array tolerance effects

Computational Methods for Conformal Antennas
We discuss commonly used methods for analyzing conformal antennas to get a physical understanding rather than specific details of the different methods. Canonical examples are given. • Modal Solutions,
MoM, FEM, and FDTD • Asymptotic and Hybrid Methods • Geodesics

Thursday – STEYSKAL
Typical DBF Applications (cont´d)
• Spatial Multiplexing: Simultaneous transmission of independent signals in different directions on the same frequency • Multiple Input, Multiple Output (MIMO) Systems for Communication and Radar • Array Element Decoupling • Array Calibration

Conformal Array Characteristics
General characteristics of conformal array antennas are reviewed. Canonical array designs and expected performances are discussed.
• Mechanical Aspects, Active Surface Definition • Phase Scanning, Commutating • Grating Lobes, Tapering, Element Impedance Variations

Partial DBF and Subarraying Architectures, DBF Systems
Trade-offs between DBF system performance and cost.
• Periodic and Random Sub-Arrays, Thinned and Wideband Arrays • Experimental DBF Systems with Planar and Conformal Arrays


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Course 23

October 26-30, 2009. Barcelona, Spain

Satellite communication systems allows exchange and delivery of information contents. Satellites are particularly appealing whenever large coverage is desired, and when either collect or broadcasting applications are considered. High reliability and flexibility for setting up links make satellites unique for specific applications. There are also use to complement terrestrial networks. However, satellites are faced with links impairments, limited bandwidth and power, and must be operated so as to allow access from multiple users without interference. From system designer to service provider, one should understand the specific constraints and opportunities of satellite communications.

Link Analysis (cont’d)
• Overall Carrier to Noise Power Ratio • Intermodulation and Interference

Digital Communications
• Link Performance Evaluation and Availability Performance Objectives PROFESSOR • Digital Transmission Techniques: MICHEL BOUSQUET M-PSK and APSK modulations • Spectral Efficiency, BER vs. E/No ISAE, Toulouse, France performances • Channel Coding and Decoding, Concatenated Coding • Use of Channel Coding for Bandwidth and Power Trade-Off • DVB-S, DVB-S2; Interest of Adaptivity

Multibeam Satellite Systems

This course presents the techniques that are used and points out the performances that can be expected from geostationary satellite systems. Emphasis is placed on the trade-offs that can be exercised within the constraints of technology and regulations. The course is as practical as possible, underlying those techniques that are, or soon will be in use, with emphasis on performance trade-offs. The course is designed to provide the attendees with an appropriate background on satellite link design and communications techniques, including those used for broadcasting and multimedia communications (DVB-S, DVB-S2). Networking aspects are analysed, focussing on physical layer (multiple access such as FDMA, TDMA, and CDMA), and satellite network architectures. Specific issues in connection with the operation of multibeam satellites and on-board regeneration are dealt with. A detailed overview on satellite communication payload, repeater and antennas, and earth station technology is given. Satellite communications engineering requires a combination of know-how in many various fields such as propagation, RF systems, antennas, signal processing, etc. Several practical exercises are to be solved during the course to allow the attendees to practice the acquired knowledge. It includes a project on the design of a European multibeam satellite communications system. The design considers performance and technology trade-off and aims at a cost efficient design of the earth segment.

• Advantages and Constraints • Beam-to-Beam Interconnectivity: Transponder Hopping, On-board switching Project Work: European Multibeam Communications Satellite System, Step 1

Satellite Networking
• Multiple Access Techniques: Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Code Division Multiple Access (CDMA) • Network Architectures: Mesh, star • DVB-S2 and DVB-RCS Systems

Regenerative Satellite Systems
• Link Budget for Regenerative Systems • Performance Comparison with Transparent Systems • On-board Processing Features • FDMA/TDM Systems, Impact on Earth Stations

Satellite Communication Payload
• Performance Objectives and Functions • Repeater Architecture: Channelisation Concept, Redundancy Project Work: European Multibeam Communications Satellite System, Step 2

Engineers, scientists and technical managers involved in the planning, design and operation of satellite communications systems; designers and technical salesmen concerned with the manufacturing of satellite communication systems equipment; technicians involved in the operation and maintenance of earth station or in the control of the satellite.

Satellite Communication Payload (cont’d)
• Characteristics of Repeater Equipment • Antenna Subsystem Coverage Concepts • Antenna Technology • Examples of Payloads Project Work: European Multibeam Communications Satellite System, Step 2 (cont’d), Step 3

Satellite Communications Systems
• Description of a Satellite Communication System • Types of Orbits • Radio Regulations • Applications of Communication Satellites • Examples of Systems

Earth Station Technology
• Earth Station Architecture • Antennas and Tracking Equipment, • RF Equipment (Low Noise and High Power Amplifiers) • Ground Communications Equipment (Up-Down Converters, Modems) • Interface with Ground Networks (Echo Control, DSI, DCME) Project Work: European Multibeam Communications Satellite System, Step 4 and Conclusion

Link Analysis
• Carrier and Noise Budget • Influence of Rain

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Course 05

June 8-12, 2009. Cambridge, UK Resist Chemistry
• Chemistry and Processing of I-Line Resists • Chemically Amplified Resists for 248nm and Beyond • Environmental Stability: T-top formation, line-width variation • Possible Solutions to Overcome Problems: Improved chemistry, interfacing of track and stepper, chemically filtered air

The explosive growth in the capability of semiconductor devices has to a large extent been due to advances in lithography. Miniaturization has enabled both the number of transistors on a chip and the speed of the transistor to be increased by orders of magnitude. At the same time, one has managed to reduce the power per transistor so that the chips do not overheat. This trend still continues uninterrupted. Sustaining Moore’s Law requires continuous advancements in lithographic resolution. Mainstream optical lithography has kept pace with this evolution for several decades and has always been the workhorse for patterning the critical layers in semiconductor applications. However, the physical limits of optical lithography are coming closer and alternative (non-optical) lithography technologies are expected to take over at some point in time. Besides semiconductors, non-semiconductor nano- and micro-technologies, e.g. MEMS, sensors, magnetic storage media, are emerging and will eventually find their place in volume markets as well. The lithography requirements for these technologies are often totally different from the semiconductor requirements. As a consequence other types of lithography may be preferred for these applications. The ability to replicate patterns from micro-scale to nano-scale is of crucial importance to the advance of micro- and nano-technologies and the study of nano sciences.

Practical Resist Implementation Issues
• Contributions to CD Variation Due to Bulk Effect, Reflective Notching, Swing Curve and Standing Waves Correlated to the Optical Parameters of the Resist • Advanced Resist Technologies: Addition of dyes, top- and bottom anti reflective coatings, dry development, top surface imaging

IMEC, Leuven, Belgium

Tuesday – KURT RONSE
Advanced Optical Imaging
• Phase Shifting Masks • Off-Axis Illumination • Optical Proximity Correction • Lens Aberrations

Optical Lithography Roadmap
• 157nm Lithography Roadblocks • Immersion Lithography Status and Challenges • Double Patterning Techniques

E-Beam Consulting Services, Monterey, CA, USA

Extreme UV Lithography, EUVL
Mainstream optical lithography is ultimately limited by diffraction and, since some time, shorter wavelength alternatives have been pursued to prepare for post-optical applications. EUVL is being developed for the 22nm or smaller generations. It is currently the most favoured of the emerging lithography options for volume manufacturing due, in part, to its extendibility beyond the 22nm half pitch node without loss in throughput. The CD entry-point, commercial infrastructure, and tool availability are described. The worldwide efforts in EUVL will be summarized.
• Description of EUVL and Overview of Worldwide Efforts • Status and Challenges of EUV Sources, EUV Optics, EUV Masks and EUV Resists

The goal of this course is to give a broad overview of various micro- and nanolithography technologies that are being used or considered for semiconductor and non-semiconductor applications. For each technology, the strong and weak points and typical applications will be treated. For all mask based lithographies, the status and challenges for mask (template) manufacturing will be discussed.

CEA/LETI, Grenoble, France

Since the mid-90th, Nano Imprint Lithography (NIL) has become an emerging lithographic technology that promises high throughput patterning of nanostructures on large areas. Based on the mechanical embossing principle of a polymer, NIL can achieve pattern resolutions beyond the limitations set by the light diffractions or beam scatterings in other conventional techniques. It has been recently demonstrated that it was possible to achieve sub-10nm resolution and alignment with NIL, and large area pattern fidelity. This technology has been applied to fabrication of various devices, including patterned magnetic disk, microoptics, compact disk, micro-fluidics and Micro-Electro-Mechanical System (MEMS) devices, field-effect transistors.
• Principles of Imprint Lithography: Hot embossing, microcontact printing, step and flash, and reversal imprint technologies • Fabrication of Imprint Stamps (hard and soft) • Adhesive Properties of the Molds: Issues and solutions • Process Issues: Large area, high resolution, defects • Associated metrology • Applications

This course is intended for engineers who are active in the field of lithography or have to take strategic decisions on lithography for their company. It will form the basis for a better fundamental understanding of the capabilities and limitations of each type of lithography, and may also suggest better, cheaper or alternative lithography technologies to be considered for their applications.

University of Michigan, Ann Arbor, USA

• The Continuous Trend of Miniaturization in Integrated Circuit Manufacturing. ITRS Roadmap • The Importance of Lithography as Enabling Technology • Evolution of the Exposure Tools Towards Advanced Step and Scan Systems

Nanoimprint Technology and Applications
Nanoimprint technology can greatly simplify the production of nanostructures by creating molds that can emboss intricate patterns onto various substrates and materials. This technique allows for the creation of devices and mi-

Theory of Optical Imaging
• The Principle of Image Formation in the Optical Lithography Process • Formation of Aerial Image by Means of Current Projection Tools • Performance Parameters: Depth of focus, exposure latitude, E-D windows • Focus and Exposure Dose Budgets


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Course 37
crosystems with nanometer features at higher rate and lower cost than possible in today’s high resolution patterning techniques. Nanoimprint could be used in the future manufacturing of nanometer scale integrated circuits and a broad range of nanosystems for use in optics, storage, sensor, and biomedical applications. In this lecture, various nanoimprint technologies and systems will be reviewed including thermal, UV, and reversal nanoimprint. Reversal UV nanoimprint will be highlighted which can be used to fabricate three-dimensional nanostructures, fluidic channels, and microsystems. Conventional semiconductor fabrication processes for 3D structures involve multiple and costly process steps such as deposition, planarization, lithography, and etching. In contrast, reversal UV nanoimprint has the unique capability of building 3D nanosystems with simpler technology and better control.
• Thermal, UV, and Reversal Nanoimprint Technology • Nanoimprint Systems • Electronic, Photonic, Storage, Sensor, and Biomedical Applications of Nanoimprint

June 8-10, 2009. Cambridge, UK

In Micro Electro Mechanical Systems (MEMS), both electrical and mechanical devices are formed. Often, the mechanical devices consist of movable components that are partially separated from the substrate they are anchored to. In some cases, special films with unique properties for sensing or mechanical movement are needed. Although the basic principles of the IC technologies used in silicon can be applied, there are many unique requirements for MEMS fabrication.

University of Michigan, Ann Arbor, USA

In this course, various micro-fabrication technologies for MEMS will be introduced. Process design and factors for precise dimension control for MEMS will be covered. Issues related to integrating mechanical and electrical components will be discussed. Current technology trends for MEMS with examples in mechanical, optical, and chemical sensing and actuation will be given. The new development of MEMS technology will be addressed.

Electron beam lithography has been pursued for many years as a means to achieve higher pattern feature resolution, needed for the advancing miniaturization, and to generate integrated circuit patterns without the need for masks. This pattern generation capability, in combination with high resolution, has also made electron beams the technology of choice for mask making. This lecture provides a comprehensive knowledge of recent advances in electron beam lithography based on an in-depth understanding of the challenges and opportunities in charged particle optics. We present the physics factors limiting throughput and compare the various techniques developed to overcome these limitations. A specific focus is on massively parallel pixel exposure, which has been achieved with Electron beam Projection Lithography (EPL) and which is currently being developed for Maskless Lithography (ML2). The advantages of using advanced electron beam tools, in a mix and match lithography with optical tools, will be presented.

MEMS Overview
• Definition of MEMS • MEMS History and Development • MEMS Examples • Resources for MEMS

MEMS Requirements
• Complex 3D Microstructures • Technology Considerations • Material Requirements • Measured Signals and Performance

Patterning Technology for MEMS
• Lithographic Patterning: Patterning by optical, X-ray, and focused ion beam lithography • Selective Wet Etching Processes • Directional Dry Etching Processes • Thin Film Deposition: Evaporation, sputtering, electroplating, chemical vapor deposition, and laser assisted deposition

• Competitive Position/ITRS Roadmap • Basic Electron Optics • Challenges and Opportunities

State-of-the-Art of Various E-Beam Techniques
• Gaussian Beam, Shaped Beam, Character, Cell, Block Exposure • Multi-Beams, Multi-Columns, and MultiEmitters • Electron-beam Projection Lithography (EPL) • Progress and Recent Results with EPL

Micromachining Technology
• New Materials for MEMS • Surface Micromachining • Bulk Micromachining • Release of Microstructures

Maskless Lithography (ML2)
• Direct Write Experience • Review of Worldwide ML2 Activities • Progress in Projection Maskless Lithography (PML2) • Issues and Prospects

MEMS Packaging and Integration
• Wafer Bonding • Chemical Mechanical Polishing • Packaging and Circuit Integration • Sensors and Circuits Integration

E-Beam Mask-Making
• Mask-Making Trends and Challenges • Electron Beam Pattern Generators in Photomask Production • Resolution Limits Imposed by Coulomb Interaction of Beam Electrons • Proximity Effect

MEMS Design and Applications
• Design of Sensors and Actuators: MEMS technology for mechanical, optical, and chemical sensors • Integrated Microsystems • MEMS Applications

Ion-Beam Lithography
• Unique Physical Characteristics of Ion-Beams • Ion-Beam use in Lithography Compared with the Use of Electron Beams • Possible Application of Scanning and Projection Ion Beam Systems for Mask and Wafer Exposure • Application of Ion Beams for Mask Repair and Inspection

Future Trends and Developments
• Mechanical, Optical, Biomedical, and Chemical Transducers • Multidisciplinary Applications and Development • Miniaturized, Portable, Low Power, Low Cost, Multiple Functions, and High Performance Microsystems

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Course 36

June 8-12, 2009. Cambridge, UK SIMOX, Wafer Bonding, SiGe and Other Emerging Technologies
Several technologies are emerging to meet the demands for higher speed, higher density, and lower voltage integrated circuits. Silicon-on-Insulator (SOI) technology, with both SIMOX and wafer bonding approaches, are now commercially available. Promises and limitations of SOI will be presented to ease the decisions in wafer specification. The SiGe1-x alloy is another advanced material that is currently emerging into the marketplace. These alloys allow the properties of Si to be engineered through composition control. Applications include intrinsic gettering through strain field control and high-speed devices. The impact of the growth process on the properties and an overview of the device applications will be presented.

The rapid growth of the semiconductor industry has relied on the continual evolution of materials and processing compatible with fabricating modern silicon-based integrated circuits. Several technologies are emerging to meet the demands for higher speed and density, and lower voltage integrated circuits. Silicon-on-Insulator (SOI) technology with both Separation by Implantation of Oxygen (SIMOX) and wafer bonding approaches are now commercially available.

University of Florida, Gainesville, USA

This course will provide an overview of the entire fabrication process. It will include all the key materials involved and the process areas utilized in device manufacturing.This course is thus addressed to a broad audience and is not intended as a research review, although it will be taught at a high level and in many areas requires familiarity with the subject matter.

Silicon Epitaxy by CVD
Silicon epitaxial deposition is a strategic process technology in large volume manufacturing. The understanding and control of this technology is critical to the success of the production of high quality devices and circuits.
• Substrate Crystal Orientation, Deposition Parameters, and Choice of Silicon Source Material • CVD Fundamentals for Si Deposition Chemistries • Reactor Design to Illustrate Deposition Mechanisms • The Influence of Deposition Parameters on Film Quality • Procedures to Prepare Wafers for Epitaxy • Film Quality and Device Performance • Si Etching by Wet Processes • Isotropic and Anisotropic Etchants

University of Texas, Austin, USA

Si Front-end Manufacturing
The entire front-end manufacturing process will be presented. A perspective on process bottlenecks and future trends, as outlined in the most recent ‘International Technology Roadmap for Semiconductors’, is presented.
• Si Wafer Production • Epitaxy • Oxidation • Dielectric Deposition • Ion Implantation • Metallization • Lithography • Etching

Silicon Oxidation
The role of the native oxide of Si as an enabler of VLSI technology cannot be overstated.This section outlines the fundamental aspects of silicon oxidation.
• Gate Oxide, Surface Passivation, Mask, Device Isolation • Growth Models for Wet and Dry Oxidation • Surface Preparation • Charge and Atom Transport • Dopant Redistribution • Orientation Effects • Properties of Ultra-thin Oxides • Novel Processes Such as Rapid Thermal Oxidation

LTM/CNRS, Grenoble, France

Device Technologies and Semiconductor Materials
The basic device technologies will be discussed, including bipolar and CMOS.
• Electrical, Optical, and Structural Properties of Silicon • Control of the Point and Extended Defect Densities • Origin of Defects and Their Influence on Device Performance • IC Materials Characterization for Process Improvement and Achieving High Yield

Process Induced Defects and Device Performance
Common impurities introduced during crystal growth and their influence will be discussed.The crystallography of the diamond structures and the formation mechanisms and structures of extended defects, i.e. stacking faults, misfit dislocations, twins, will be reviewed. Both intrinsic and extrinsic gettering technologies will be described with a discussion of their effects on subsequent device processing and device parameters.

Deposition of Metals and Dielectrics by Physical and Chemical Methods
The various physical and chemical approaches to the deposition of metal and dielectric materials are outlined and compared. The ‘Roadmap’ predicts that Atomic Layer Deposition (ALD) methods will eventually become the dominant process because it is well suited for deposition of ultra-thin, highly conformal films over small device features.

Integrated Circuit Metallization Systems
• Multilayered Interconnect Structures: High density and high performance • Scaling and Wiring Requirements of ULSI Circuits • Interconnect Performance and Density • Requirements for Metallization Systems in Device Contacts and Interconnecting Lines • Major Factors Affecting Reliability of Multilayered Sub-micron Interconnects • New Interconnects with Cu and Low k Material

Large Diameter Wafers
It is essential to have the highest quality Si wafers to achieve high process yields. The wafering process and issues related to quality assurance and acceptance will be addressed.


CEI-Europe • Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •

Dielectrics for Multilayered Metallization
• Thin Film Dielectrics • The Evolution of Interlevel Dielectrics from SiO2 to Low k Dielectrics • Material Requirements and Integration Issues • Development of Organic and Inorganic Low k Materials • Tradeoff of Thermo-Mechanical Properties • Impacts on Reliability

Plasma Etching and Plasma-Enhanced CVD
• Reactive Gas Glow Discharges: Plasma etching, reactive ion etching, and PECVD • Operation of Low and High Density Plasma Sources • Surface Science Aspects of Plasma Etching • The Role of Energetic Ion Bombardment in Obtaining Etch Profile Anisotropy • Etching of Silicon and Its Compounds in Halogen-based Etching • PECVD and Its Role in Plasma Etching • PECVD Processes of Greatest Importance in Semiconductor Manufacturing

CMP for Microelectronics Applications
Chemical Mechanical Planarization (CMP) is an enabling technology for the microelectronics industry. The empirical nature of CMP and how it bridges many engineering disciplines for resolution of its numerous challenges will be emphasized.
• How to Effectively Utilize CMP • Evolution and Revolution of CMP Equipment and Consumables • Characterization Techniques for Process Development and Control • Advantages and Limitations of CMP Processes for Advanced Microelectronics Applications

Applied Materials, Austin, TX, USA

Ion Implantation and Diffusion
Critical issues of ion implantation and junction formation in silicon devices are discussed.
• Process Issues in Applying Ion Implantation/Annealing • Materials Issues of Ion Penetration, Damage Production, and Masking • Annealing Implanted Layers in Silicon: Oxidation over implanted layers, furnace annealing, Rapid Thermal Processing (RTP) • Critical Issues for Creating pn Junctions in Silicon: Low leakage junctions, removing damage, controlling diffusion during the annealing of implantation damage, scaling of pn junction depths, contacting, diffusion through thin oxides in doped polysilicon gate/oxide/ silicon devices • Process Simulation for Design and Control of Implanted and Annealed Junctions

IMEC, Leuven, Belgium

High k Dielectric Materials
Alternate gate dielectric materials are being developed, as the continuously reduced SiO2 thickness is approaching its physical limitation and direct electron tunneling results in unacceptably high leakage currents.
• Potential High k Materials Ranging from 10 to 100: Transition metal oxides, ferroelectric materials, metal silicates • The Impact of Thin Gate Oxides on Device Performance • Benefits of the Use of High k Dielectrics • Material Properties, Growth Methods, and Impact on Device Performance

Reliability and Yield
The success of an IC manufacturing facility is directly connected to IC reliability and product yield. An overview of failure mechanisms and yield limitations will be presented. The discussion will include approaches to circuit and layout design, device design, materials selection, process optimization, as well as thermo-mechanical considerations. Proven yield improvement management processes will be outlined.

IBM Microelectronics Essex Junction, Vermont, USA

Optical Lithography
The continuous trend of miniaturization in IC manufacturing and the importance of lithography as an enabling technology will be presented. Optical lithography has till now always been the workhorse of the industry. The lithographic process of optical lithography will be analyzed.
• Image Formation in the Optical Lithography Process • Basics of the Resist Chemistry • Issues Encountered when Applying Resists to Real Device Processing • Resolution Enhancement Techniques: Phase shifting masks, off-axis illumination, optical proximity correction

Recently, immersion lithography has been introduced as a next technique to further scale down the resolution limits of optical lithography. This course will also address the fundamentals of immersion lithography, give an update of the issues and status, and finally give an outlook to the ultimate resolution limits using immersion lithography.

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Course 87

June 8-9, 2009. Cambridge, UK
The surface science aspects of this complex chemical environment will be discussed in detail both on the wafer and on the reactor walls. The importance of energetic positive ion bombardment of the surface being etched in obtaining anisotropic etching will be highlighted. Other factors that determine the degree of anisotropy (neutral radical/ ion flux ratio, degree of spontaneous etching, sidewall passivation layers, temperature) will be included. Examples of the importance of wall reactions (deposition, radical-radical recombination, ion neutralizations) will be presented.
• Introductory Concepts • Physics of Plasma Sources • High Density vs. Low Density Plasma Etching • Surface Science Aspects of Etching Reactions • The Role of Energetic Positive Ions in Etching • Etching Anisotropy

Plasma-assisted etching is used in many technologies. It is most critical in ultra large scale integrated (ULSI) circuit fabrication and is used many times during the processing of a single wafer. Other areas that rely heavily on plasma-assisted etching include micro-electrical-mechanical (MEMS) structure fabrication, many so-called nano-science processes, micro-optical and photonic activities and numerous other material processing where near room temperature chemical reactions are required.

LTM/CNRS, Grenoble, France

The objective of this course is to describe the extent to which the fundamental processes in plasma-assisted etching are understood and to relate this understanding to the practical applications of the technology. The reactive gas plasma environment is very complex and depends strongly on the type of plasma source that is used. Atoms, molecular radicals and energetic positive ions dominate the etching surface chemistry. The fundamental aspects of the reactions of these species with solid surfaces have been studied extensively and a qualitative understanding of this complex surface chemistry has been developed.

Etching Chemistries, Plasma Diagnostics
The mechanisms that control the densities of radicals in the plasma will be discussed. Examples of the importance of wall reactions (deposition, radical-radical recombination, ion neutralizations) will be presented, including a discussion on process drifts issues. The etching of silicon and its compounds (SiO2,Si3N4, SiC), as practiced in present-day ULSI device fabrication will be summarized. Included in this discussion are such topics as selectivity, loading effects, aspect ratio dependent etching, sidewall charging and other feature-scale phenomena such as notching and trenching. The etching of other materials (Al, organics solids, silicides, tungsten, titanium, III-V compounds, Cr) will be described but in less detail. Etching uniformity (including critical dimension control) and equipment related issues are discussed in some detail. Plasma and surface diagnostic methods (optical emission spectroscopy, mass spectrometry, and reflectometry) are described briefly including their application to process control and process development.
• Wall Effects • Loading Effects • Feature Scale Phenomena • Fluorine-to-Carbon Ratio Concept in Fluorocarbon Plasma • Etching of Si and Its Compounds • Selectivity (SiO2/Si and Si/SiO2) • Etching of Other Materials • Etching Non-Uniformity • Contamination and Damage • Plasma Diagnostics

Any person with a technical background wishing to obtain a better understanding of the mechanistic aspects of plasma-assisted etching, or of reactive gas plasma-surface interactions in general, should benefit from taking this course. Although the emphasis of the course is on the ULSI circuit fabrication applications, much of the information presented should be of value in the implementation of other processes involving reactive gas plasmas. A familiarity with the basic concepts of plasma-assisted etching would be helpful but is not essential as the course includes a short summary of the basics.

Plasma Sources and Etching Mechanisms
An introductory discussion of reactive gas plasmas will be given, emphasizing phenomena that are known to be important in reactive gas plasmas such as electron impact induced dissociation and ionization and the electron energy distribution in the plasma. The significance of the vapor pressure of etch product molecules will be discussed. The operation of the various types of plasma sources (e.g., capacitive, dual and triple frequency capacitive, inductive and wave generated) that are used in this technology will be covered in detail. The importance of the self-bias voltage and the plasma potential, including the reasons for the existence of these voltages, will be described. A global model of high density discharges will be described, which allows calculating the ion flux and ion energy impinging on the wafer. A short summary of the evolution of plasma etching equipment will be presented along with the rationale for the equipment changes that were made.


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Course 88

June 10-12, 2009. Cambridge, UK

Extensive efforts to miniaturize semiconductor devices is largely attributed to lithography and etching technologies that allow semiconductor thin films patterning in the range of dimensions determined by the semiconductor road map. During more than 30 years, classical materials, such as aluminum, SiO2, and polysilicon, have been integrated in semiconductor devices. Nowadays, the technology imposes to work with new materials at each technological node. The integration of new high k and low k dielectric materials, metals at the front and back end of device fabrication, bring on new problem categories. This imposes the necessity to quickly build up expertise at a rate unprecedented in all the history of semiconductor manufacturing.

Fundamentals in Plasma Processing
• Ion Neutral/Synergy • Impact of Neutral Flux to Ion Flux Ratio on Plasma Processes • Etch Anisotropy • Passivation Layer Formation in Plasma Processes • Temperature Effects in Plasma Etching • Microscopic Uniformity in Plasma Etching • Impact of Aspect Ratio on Etching Processes • Charging Effects in Plasma Etching • Impact of Reactor Wall on Plasma Processing • Micro-Trenching Formation • Etch Mechanism of Silicon in Halogen Based Plasmas • Sio2 Etch Mechanisms • Polymer Etching for Microelectronics Applications

LTM/CNRS, Grenoble, France


This course is intended to provide an understanding of plasma processes for CMOS applications and ULSI technology. We will discuss fundamental and practical aspects of front end and back end plasma processes for deep submicron CMOS logic processes. The course is based on experimental results obtained using commercial etchers connected to very powerful diagnostics of the plasma and the plasma surface interaction. The discussions cover several aspects of etch processes of materials integrated in advanced CMOS devices, etch mechanisms, and situations that may be encountered for some important plasma processes. Fundamental parameters obtained from advanced characterizations are used to discuss and analyze plasma etch processes. The emphasis is on real problems, fundamental understanding of processes used in manufacturing, considerations for integration with other steps, and issues brought by the fast device scaling. Processes covered in detail include silicon gate patterning and all the problems related to critical dimension control as well as preliminary results on high k dielectric etching. The etch processes associated with the integration of low k materials will be extensively discussed. Emphasis will also be on advanced process control techniques that are used to improve the reliability of plasma processes in a real environment.

Silicon, Metal and High K Etching Processes for CMOS Applications
• Thin Gate Oxide Behaviour during Gate Etch Processes • Silicon Recess During Gate Etch Processes • Impact of Plasma Processes on 193 Nm Resists • Hard Mask Opening Processes • Silicon Gate Etching in Inductively Coupled Plasmas: Hbr/Cl2/O2, Hbr/Cl2/O2/CF4, SF6/CH2F2 Chemistries • Metal Gate Etching • The Etch Challenges of High K Materials • Chamber Wall Coating during Si/Metal/High K Etching • Chamber Wall Cleaning Strategies for CMOS Applications

Oxide and Low k Etching
• Fundamentals in SiO2 Etching • Low k Materials in Advanced Interconnects

Oxide and Low k Etching (Cont’d)
• Mechanisms of Low k Polymer Etching in Medium Density and High Density Plasmas • Etch Mechanisms of SiOC-based Materials • Selectivity Issues • Fluorocarbon Film Thickness Measurement by XPS • The Impact of Porosity on Etching Mechanisms of SiOC-based Materials • Dual Hard Mask Strategies • Impact of Ashing Plasmas and Chemistries on Low k Material Modifications

See also course #87, June 8-9, 2009

CEI-Europe • Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •


Course 75

June 8-10, 2009. Cambridge, UK
state in line structures with distinct characteristics in contrast to the biaxial stress state in thin films. The impact of the stress states on the deformation mechanism and interconnect reliability such as interfacial delamination and stress-induced voiding will be examined.

With continuing device scaling, wiring interconnect becomes increasingly important in limiting chip density and performance. The evolution of the interconnect technology brings forth new and increasingly stringent materials and processing requirements. The driving forces that dictate the materials and processing requirements of metallization systems for high density circuits will be examined, emphasizing the current approaches used for Al-based and Cu-based interconnect development. As the device technology continues to advance, the interconnect development presents significant challenges for materials, process integration and reliability. Discussions will include interconnect development for specific applications, such as power devices and automotive modules.

Thermal and Mechanical Properties of Thin Films
Thermodynamics and kinetic aspects of thin film deposition will be reviewed. The relationship between microstructure, deposition processes and stress in thin films will be presented. The effects of annealing, encapsulation, and alloying will be described. Examples will be taken from multilevel interconnections.

University of Texas, Austin, TX, USA

This course provides an overview of on-chip interconnect technology with emphasis on Al-based metallization systems and the evolution to Cu-based metallization will also be discussed. First the technology trend of interconnect development for integrated circuits will be identified and examined. The trade-off between density and performance with scaling will be discussed. Then key areas in materials and processes for interconnect metallization systems will be reviewed, including contact metallurgy, dielectric materials, barriers and contacts, and damascene processes. This will include interconnect systems development for special applications, such as power devices and automotive modules. Materials requirements, deposition, processing and characterization of thin films and interconnect structures will be reviewed. Electromigration and stress voiding reliability will be discussed, focusing on the effects due to interconnect scaling, materials and structure changes.

Thin Film Deposition and Control of Film Properties


Thin film deposition processes will be preSemiconductor/IBM sented with emphasis on physical deposiTechnology Alliance, tion methods. Evaporation (PVD), SputterHopewell Junction, ing and Chemical Vapour Deposition (CVD) NY, USA of metals, alloys, and compounds will be described with examples taken from silicon technology. The relationship between thin film properties and deposition processes will be presented. The effects of ion bombardment, temperature, and reactive gases on the composition and microstructure of thin films will be described. Case studies will be used to illustrate the techniques for controlling film properties.

This course is intended for individuals who wish to expand their knowledge in the materials, processing and reliability aspects of ULSI metallization systems.The subjects covered in this course extend from fundamentals of deposition and processing of metal and dielectric films and structures to the current technology of Cu/low-k interconnects.

Processing of Advanced Multilayered Structures
Multilayered interconnect structures designed to achieve high density and high performance will be discussed. Processing issues for Al metallization will be compared with Cu metallization, projecting the challenges for future technologies. Planarization processes using the damascene structure and chemical mechanical polishing will be reviewed. Barrier layers and deep trench filling for submicron interconnects will be described.

Interconnects for Specific Device Applications

Monday – PAUL HO
Trends in Interconnect Technology
The scaling of VLSI and ULSI circuits and the impact on interconnect performance and density will be reviewed. Past and future trends in interconnect development and technology roadmap will be presented. Key issues for controlling interconnect density and performance will be examined, including effects of device scaling and wiring optimization. New interconnects with copper and low dielectric constant material will be introduced.

Interconnect schemes for specific device applications such as power devices and automotive modules will be discussed. Due to different device requirements such as high power consumption or elevated temperature usage, interconnect structures have to be tailored towards their specific needs. An overview of these various usage types will be given and their impact on the choice of interconnect scheme will be discussed.

Wednesday am– MARTIN GALL
Metallization Reliability
Major reliability issues for multilevel submicron interconnects will be discussed, focusing on electromigration and stress-induced void formation. Electromigration characteristics for Al and Cu interconnects will be compared, including damage formation mechanisms and effects due to interconnect materials and damascene structures. The statistical approach for early failure detection in high-density interconnect systems will be presented. Stress-induced void formation will be discussed, emphasizing thermal stress behaviour in confined line structures, stress measurement of interconnect structures, and analysis of stress voiding reliability.

Contact Metallization
The basic requirements for metallization systems in device contacts and interconnect structures will be examined. Key aspects of contact metallization will be discussed, including formation of Schottky and ohmic contacts, interfacial reactions, self-aligned silicidation processes and contact reliability. Materials and processing issues for future contact metallization will be discussed addressing the effect of device scaling and deep submicron technology.

Thermal Stresses in Thin Films and Line Structures
The characteristics of thermal stresses in thin film and line structures will be discussed. The dielectric confinement leads to a triaxial stress


CEI-Europe • Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •

Course 95

Processing and Reliability of Cu Low-k Interconnect Metallization
• Deposition Options • Deposition Seeding: PVD • Alternative Seed Processes: ALD, CVD, electroless plating • Copper Electroplating: Role of additives, super filling of high aspect ratio structures • Post Annealing and Line Resistance Control • Electroless Deposition of Refractory Metals

With continuing device scaling beyond the 90nm node, wiring interconnect becomes increasingly important in limiting chip density and performance. Fundamental changes in interconnect materials are needed with Cu replacing Al and low permittivity dielectrics replacing SiO2. The integration of these two advanced materials results in significant reduction in signal delay, cross-talk, and power dissipation, enabling the semiconductor industry to continue device scaling. The fabrication of Cu low k interconnects requires novel materials and processes, including electroplating Cu, dual damascene structures, chemical-mechanical polishing, ultra-thin barriers, and passivation layers. These novel materials and processes give rise to distinct structure and defect characteristics raising yield and reliability concerns for Cu/low k interconnects. As the technology continues to advance, the implementation of porous low k dielectrics beyond the 65nm node will bring in new processing and reliability issues, such as pore sealing, etch damage and ultra-thin barriers. These problems will be discussed together with recent advances in material and process development and reliability improvement for Cu low k interconnects.

University of Texas, Austin, TX, USA

Chemical Mechanical Polishing
• Damascene Processing: CMP slurries , CMP pads • CMP Process Problems: Erosion, dishing, corrosion, scratches, residues • Alternative Planarization Processes: Electropolishing, ECMP • Effect of CMP on Low-k Dielectrics • Post-CMP Cleaning

Packaging Processes
• Dicing • Wirebond Process • Flip Chip Process

This course will provide an overview of the materials, processes, and reliability for Cu/low k interconnects. It will focus on basic issues relating to copper deposition, damascene structure and processing, and on low k dielectric materials, their processing and reliability issues. The effects of scaling and process integration on performance and reliability for advanced transistors will be examined. The impact of chippackage interaction on low k chips will be highlighted and discussed.

IBM Microelectronics Basic Device Physics • Scaling Theory Essex Junction, • Stress Effects Vermont, USA Processing • Isolation; STI, LOCOS • Gate Dielectric: SiO2, Si oxynitrid, high K • Gate conductors: Polysilicon, polycide, metal gates, FUSI • Junction formation: Ion implantation, clustered ion beam, plasma doping; furnace anneal, RTA, laser anneal; stress layers; SiGe, SiC • Contacts: Silicide; stress layers; SiN barrier layer; pre-metal dielectric – PECVD vs Spin-on; W contacts vs. low resistivity contacts • Device Yield and Reliability: Hot electron, NBTI, dielectric breakdown, charge damage



We now continue with an overview of interconnect scaling trends, problems, and potential solutions. We then provide a detailed discussion on current developments and processing integration of low k dielectrics. Key areas discussed include chemical bond and electron polarizability and how they are optimized to yield desired properties for low k dielectrics. Discussions on processing integration include deposition and etching of low k dielectrics and the formation of ultrathin liners in damascene structures.

Wednesday pm – JEFFREY GAMBINO
• Dielectric Selection • Spin on Processes • CVD Deposition • Post Deposition Processing: Solvent removal, porogen removal, curing • Characterization of Deposited Films: Porosity, thickness, composition, bonding

Dielectric Etching
• Via First vs. Line First Dual Damascene Schemes: Hardmask vs softmask processes • Resist Poisoning • Etch Control: Resist erosion, lineedge roughness, profile control • Impact of Etch Processes on Dielectric: Lateral etching, low-k oxidation • Hybrid Structures

Cu Interconnect Technology
• Cu Interconnect Technology • Interconnect Scaling Trends • Performance and Density Limitations • Wiring Design of Cu Interconnects • Need for Advanced Materials • Cu Damascene Interconnect Structures

Liner Deposition
• Liner Selection • Precleans and Damage Removal: Wet cleans, in-situ cleans • Metal Deposition Options: PVD processes, ALD processes • Resistance Impact and Liner Thickness Uniformity and Control • Pore Sealing

Development of Low k Materials
• Dielectric and BEOL Roadmap • Dielectric Constant and Chemical Bond • Molecular Design of Low k Dielectrics • Fully Dense and Porous Low k Dielectrics

We will now focus on implementation and reliability issues of Cu damascene structures. This will include Cu deposition by electroplating and chemical mechanical polishing of Cu damascene structures. Reliability issues will be examined including thermal stress, electromigration, and leakage current characteristics. Recent advances in improving Cu/low k reliability will be discussed, including the use of metal overlayers to improve adhesion and electromigration performance and packaging effect on reliability of Cu low k chips.

Friday –PAUL HO
Structural Integrity and Reliability of Low k Interconnects
• Thermomechanical Deformation • Thermal Stress Behavior of Low k Interconnects • Stress Induced Void Formation in Cu Low k Interconnects • Electromigration in Low k Interconnects • ChipPackage Interaction and Impact on Cu Low k Reliability

CEI-Europe • Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •


Course 16

June 8-12, 2009. Cambridge, UK
Low- and high-level injection conditions are discussed. Key NPN and PNP DC and AC parameters are defined and their characterization described. These include gain, early voltage, ideality, capacitances, breakdown voltages, parasitic resistances and capacitances, gain-bandwidth product (ft), maximum oscillation frequency (fmax), and noise. The relation of parameters to horizontal and PROFESSOR EMERITUS vertical geometries and their sensitivities to CARLTON M. OSBURN process variations are discussed. North Carolina The objectives and considerations in inteState University, grating MOS and bipolar devices in BiCMOS Raleigh, USA technology are reviewed in detail. Process and device architecture alternatives and scaling schemes are reviewed for various silicon-based technologies. CMOS and bipolar device performance tradeoffs inherent in creating a BiCMOS process from purely CMOS or bipolar flows are addressed. Emphasis is given to critical bipolar process modules such as buried layers, collector structures, vertical and horizontal isolation schemes, base formation, and polysilicon emitter design. SiGe and SiGe-C technologies and their advantages for analog/RF applications are reviewed. Integration of analog/RF passive components, their key parameters and characterization are discussed.

CMOS is the dominant integrated circuit technology offering low power consumption, ease of circuit design, and increasingly high performance with device scaling. BiCMOS adds the further advantages of noise immunity, linearity, device matching, and high drive capacity, thus permitting performance optimization and a higher degree of system integration. Hundreds of complex and mutually interdependent processing steps must be performed in a well-defined sequence in order to build the circuits successfully. These steps, as well as their sequence, must be carefully planned to assure high yield, adequate performance, and acceptable cost.

This course has a threefold emphasis: first on understanding MOS and bipolar device requirements for current and future generations; second, on how integrated process sequences can be constructed to meet those requirements; and finally, on the subsequent needs for unit processes, such as enhanced mobility channels, gate stack formation, SiGe bases, lithography, shallow junction formation and multilevel metallization techniques - all crucial to successful submicron device implementation.

Engineers and scientists working on the design, fabrication, and manufacturing of advanced silicon devices would benefit from this course. It provides an excellent way to obtain in-depth knowledge for those individuals who already have an engineering background but are relatively new to semiconductor process technology. Experienced participants, who are responsible for process development, will benefit from the years of problem-solving experience that are supplied by the instructor and his lectures. The course is also designed to provide management-level perspective on future trends and important issues in the semiconductor industry, as portrayed in the International Technology Roadmap for Semiconductors.

Front End Processes: Active Device Formation
• Buried Layers, Epi, Contacts to Buried Layers, and Well Formation Options • Shallow and Deep Trench Isolation and LOCOS Options • Formation of MOS and Bipolar Active Devices: Strained channels for enhanced mobility, base and channel doping • Ultra-Thin Gate Insulators: Progression from SiO2 to SiON to high k • Poly-Si and Metal Gate Electrodes and Base/Emitter Contacts • Patterning: Lithography and etching

Applications of Ion Implantation and Rapid Thermal Annealing in CMOS/BiCMOS
• Typical Ion Implants and Device Structures: From shallow source/ drain extensions to deep wells, and their functions • Series Resistance Requirements for Contacts and Junctions: Xj-Rs needs • The Drain Extension Structure • Implant Considerations in Devices: Edge effects, shadowing, knock on • Control of Short Channel Effects with Channel and Halo Implants • Ion Implantation for Non-classical CMOS Devices, i.e., SOI and FinFET • Process and Device Simulation

CMOS Device Design and Optimization
The challenges encountered in designing and fabricating semiconductor devices suitable for advanced ULSI are described. Basic semiconductor physics are reviewed starting from energy bands and doping in semiconductors and including pn junction and MOS operation. Short channel effects in state-of-the-art CMOS devices are described along with the tradeoffs between drive current, off-state leakage, and substrate current that are associated with alternative channel and drain doping strategies. CMOS device and circuit considerations to minimize device degradation are covered, including that caused by hot electrons and holes, and the electric field reduction options to minimize device degradation. The inherently bipolar nature of the CMOS structure and the latchup problem and its prevention are reviewed. Roadmaps are used to portray the advances of technology and to project future requirements. Strategies for future non-classical CMOS, including fully depleted and multi-gate FinFETs are shown.

Front End Processes: Junction and Contact Formation
• Ultra-Shallow Junction Formation • Junction Contacting Strategies, Self-Aligned Silicides • Parasitic Series Resistance

Back End Processes: Multilevel Interconnect
• Pre-Metal and Interlevel Dielectric Layers • Contacts and Vias • Planarization Strategies • Multilevel Interconnect Options

Bipolar Device Design and Optimization and BiCMOS Process Integration
An extensive tutorial is given on bipolar transistor physics, device design, trade-offs, and optimization in an integrated BiCMOS process.

BiCMOS Yield and Reliability Considerations
This lecture covers systematic and random defects, yield models, critical areas, monitors, and yield management. Basic reliability concepts and models, including reliability distributions, acceleration factors and burn-in, are described to compliment earlier discussions of the reliability physics involved with electro-migration, hot-carrier effects, NBTI, oxide degradation and integrity, and latch-up.


CEI-Europe • Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •

Course 62

June 10-11, 2009. Cambridge, UK

Growing complexity in semiconductor design and processing, especially in a fabless or foundry environment, often leads to functionality, yield, or reliability failures that directly affect timeto-market and serviceability. Rapid and definitive root cause determination is realized only through a proactive design, test, and packaging strategy that is optimized to diagnose and isolate faults for subsequent failure analysis and corrective action. Once the domain of a small handful of simple test and failure analysis laboratory techniques, this critical field now relies on strong synergy between three key areas of the business: test, packaging, and fault isolation – the latter of which includes a wide array of new sophisticated electrical and physical instruments and techniques. The ultimate success of this key element of the semiconductor development and manufacturing business hinges on a test and packaging strategy that leverages the capabilities of each of these methods while taking into account their dependencies and limitations.

The Business and Technical Environment for Debug and Fault Isolation
The role of debug and fault isolation in semiconductor development and manufacturing. Overview of basic debug strategies including technical issues and business impacts. The importance of communication and synergy between stakeholders.

IBM Systems & Technology Group, Burlington, VT, USA

Electrical Characterization and Stimulus for Debug and Fault Isolation

Common electrical failure modes and test methodologies for VLSI packages and logic, memory, ASIC, microprocessor, analog, and mixed signal chips are presented and categorized. Basic electrical test and characterization techniques are covered for understanding and diagnosing these failures and for providing the proper stimulus for debug and fault isolation.

This course will provide: • An overview of the debug and fault isolation business and technical environment • A brief summary of common semiconductor failure mechanisms and test methodologies • An understanding of leading-edge debug and fault isolation instruments and methods including photonic, thermal, magnetic, electron, ion beam, and x-ray microscopy • A review of common semiconductor package types and their compatibility with fault isolation techniques • Case histories and examples • And guidance on implementing a proactive process for successful debug.

Test Infrastructure and Package Sample Preparation
VLSI component packaging is rapidly increasing in density and what used to be a simple means of interconnect to the outside world has become a complex device of its own. Preparing a packaged chip for non-destructive debug and fault isolation requires numerous techniques that preserve original functionality and form-factor as much as possible while maintaining heat dissipation and allowing access to internal nodes and films. Laser ablation, milling, surface grinding and micromachining methods are examined along with test fixturing.

Package and System Level Fault Isolation
Time-domain reflectometry, thermal imaging, and X-ray tomography are critical methods covered for non-destructively debugging and isolating failures in single and multi-chip and multi-layer VLSI packages.

This course will be of strong interest to technicians, engineers and project managers working in semiconductor R&D, design, process engineering, manufacturing, test, quality and reliability, failure analysis, procurement, and sourcing. It will be relevant both for captive semiconductor fabricators and fabless/foundry partners.

Die Level Electrical Debug and Fault Isolation
Scan-chain design and test and memory bitmap analysis are presented as mainstream approaches to isolating problems with logic and memory cells, respectively. Internal node nano-probing is also covered as the only method of characterizing the electrical performance of individual circuit nodes and transistors.

Physical Characterization, Debug, and Fault Isolation
Electrical fault isolation techniques are by nature limited in spatial resolution to the area energized – a logic node or a memory cell for example. For many nanoscale defects and subtle non-visual defects this level of isolation is insufficient. Physical characterization, debug and fault isolation takes advantage of physical effects of semiconductor devices, materials, and interconnects. Properties such as photocarrier absorption, magnetic field density, and electroluminescence are used with electrical test and high resolution microscopy to image and characterize the operation of functioning devices and defective circuits. Methods include laser scanning microscopy, magnetic field imaging, photon emission microscopy (PEM), passive voltage contrast (PVC), and optical and electron beam induced current (OBIC/EBIC) imaging.

Proactive Approach to Successful Debug
Planning, communication, and interaction between all stakeholders are important in ensuring success when problems arise. Class material will be reviewed and synthesized into a process for ensuring the best possible plan for debug and fault isolation.

CEI-Europe • Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •


Course 61

June 8-12, 2009. Cambridge, UK

Yield and reliability are two of the cornerstones of a successful IC manufacturing technology along with product performance and cost. Many factors contribute to the achievement of high yield and reliability, and many of these also interact with product performance and cost. A fundamental understanding of failure mechanisms and yield limitations enables the up-front achievement of these technology goals through circuit and layout design, device design, materials choices, process optimization, and thermo-mechanical considerations. Failure isolation and analysis, defect analysis, low yield analysis, and materials analysis are critical methodologies for the improvement of yield and reliability. Coordination of people in many disciplines is needed in order to achieve high yield and reliability. Each needs to understand the impact of their choices and methods on the final product. Unfortunately, very little formal university training exists in these critical areas of IC reliability, yield, and failure analysis.

Tuesday – JOSÉ MAIZ
Transistor Reliability: Dielectric Breakdown, Hot Carriers and Parametric Stability
• Physics, Statistics, and Scaling Impact on Failure Mechanisms • Reliability Performance of Thin Conventional Oxides: Defects, wear-out failures • Hot Carrier Performance and Parametric Stability of P- and N-channel Devices under DC and AC • High k Gate Dielectrics and Novel Transistor Configurations • Key Failure Mechanisms for Bipolar Transistors • Transistor Reliability Strategies in Fabless Environments

Intel Corporation, Hillsboro, OR, USA

CMOS Latch-up and ESD
• Physics, Scaling Impact, and Technology Dependence of CMOS Latch-up and Electrostatic Damage (ESD) • Technology and Design Based Solutions, Device Performance, and Manufacturability Constraints • Latch-up and ESD Assessment in Fabless Environments

Soft Errors, and Other Failure Mechanisms
• Physics, Scaling Impact, and Technology Dependence of Alpha Particle and Cosmic Ray Induced Soft Errors • Technology Solutions, Performance, and Manufacturability

Applied Materials, Austin, TX, USA

This course will be of strong interest to engineers working in semiconductor R&D and manufacturing, equipment service, and also procurement of product from foundries. It will be relevant both for companies producing integrated circuits themselves and for those involved as partners in the “fabless/foundry” model.

Yield Elements
• The Importance of Yields to the Financial Success of a Semiconductor Manufacturer • Data of Typical Yields Obtained in the Industry for Different Product Generations • The Concept of Yield Modeling, Showing Defects and Other Mechanisms Affecting Yields • Process and Equipment Defect Details: Lithography, oxidation, thin film deposition, etching, and wafer cleaning • Other Defect Sources: Clean-room materials and environment • Yield Issues: Electrical parameter distributions and physical device structures • Practical Examples: How Yields are Impacted by Various Types of Phenomena

Monday – JOSÉ MAIZ
IBM Systems & Technology Group, Burlington, VT, USA

Reliability Fundamentals and Scaling Principles
• The Reliability Bathtub Curve, Its Origin and Implications • Key Reliability Functions and Their Use in Reliability Analysis • Defect Screening Techniques and Their Effectiveness • Accelerated Testing and Estimation of Useful Operating Life • Reliability Data Collection and Analysis in Integrated Circuits • Past Technology Scaling Trends • Forward Looking Projections with a Focus on Examining and Understanding of the Impact on VLSI Reliability • Power Density Trends: Operating temperature, activation energies for dominant vlsi failure mechanisms, and reliability impact • Reliability Strategies In Fabless Environments

Yield Management and Improvement
• Attributes Possessed by “High Yield” Wafer Fabrication Lines • In-line Measurement Techniques for Process Control and Improvement: Particle detection and loop structures • Examples: Successfully Applied Techniques to Improve Yields • The Use, Importance, Application, and Pitfalls of Statistical Process Control • Software Techniques for Detecting Significant Patterns in Yield Data • Yield Impacting Factors: How continuous improvements can be made • Special Topics of Interest

Reliability of the Interconnect System
• Physics and Statistics of Failure Mechanisms Associated with Interconnect Systems • Electro-migration of Al and Cu Interconnects • Mechanical Stress Driven Metal Voiding and Cracking • Low k Materials as Interlayer Dielectrics and Their Impact on Electro-migration • Thermo-mechanical Integrity of the Interconnect System • Key Technology Parameters: Materials choices, structural and geometric effects • Extreme Scaling Impact on Wear-out Time • Technology Solutions: Alloys, metal barriers, and engineering of interfaces • Improved Electro-migration Performance under Non-DC Currents and Short Lines • Interconnect Reliability Strategies in Fabless Environments


CEI-Europe • Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •

Process and Product Control
• Statistical Process Control • Process Certification and Qualification

The mission of CEI-Europe is to provide professional scientists and engineers with continuing education in state-of-the art technology.

Managing Quality in Manufacturing
• Technology Transfer • Copy Exactly

Design for Manufacturing
• DFM: What it is and methodology evolution • Datamining Techniques: Identify process/product yield interactions and fast troubleshooting • Leveraging Mini Shrinks: Improve overall die output • Yield Maximization Through Optimizing Product Designs

In 1980, Dr. Birgit E. Jacobson, at the time associate professor in materials science, had returned to Sweden after four years of research at Stanford University. She brought with her an awareness of the need of the academic researcher and the active engineer to share an educational arena where state-of-the-art discus- Dr. Birgit E. Jacobson, CEO, sions could take place, a forum that would facilitate Doctor honoris causa the fruitful interplay that results from discussion with compeers. That insight formed the underpinnings of Continuing Education Institute-Europe, a company committed to the transfer of high tech knowledge. Today, more than 30'000 engineers have attended CEI-Europe courses. Over the years, Dr. Jacobson has received recognition as scientist and educationalist. In 2001, the University of Cambridge in England honored her with a By-Fellowship for outstanding contributions to international learning in advanced technology. Since 2003, she is Honorary Doctor at Chalmers University of Technology, Sweden, awarded for outstanding achievements in the international field of scientific education.

Fabless/Foundry Model
• The Fabless/Foundry Business Model • Foundry Supplier Selection • IP and Design Services • Processes for Foundry Supplier Management: Negotiations, planning, inventory • Managing Foundry Quality: Supplier management scorecard

Failure Analysis
• Overview of Failure Analysis Instruments and Processes • Memory, Logic, Analog, and Mixed Signal Device Approaches • Package, Wafer, and Die Level Analytical Strategies • Methods for Technology Development, Yield, Reliability, and Customer Return Failures • Electrical Fault Isolation Principles: Time-domain reflectometry, memory and logic diagnosis • Physical Fault Isolation Techniques: Electron, ion, and laser scanning microscopy; photon emission, thermal and magnetic imaging; scanning probe microscopy • Electrical Characterization: Micro- and nano-probing • Chemical, Mechanical, and Ion Beam Deprocessing • Optical, Acoustic, Scanned Probe, Electron, and X-ray Microscopy/Tomography

CEI-Europe is not just another company active in the educational field. The personal commitment of Dr. Jacobson is reflected in the high standard of handpicked instructors from universities and high tech enterprises throughout the industrialized world. It is reflected too in the fact that so many very busy professionals continually return to instruct at CEI-Europe courses. Only the best is good enough for CEI-Europe. No traditional university has access to a faculty equal to that of the internationally renowned instructors at CEI-Europe. No traditional educational company offers interdisciplinary programs in spearhead technology where attendees meet their professional peers in a think tank environment. Not only are our more than 100 instructors internationally renowned in the particular field of each, but all have demonstrated a pedagogic ability to impart technological expertise to a professional audience. They also act as advisors for our forthcoming programs to ensure that the latest developments in the field will be included. For this reason, content of the courses change from year to year.

Materials Analysis
• Particle Beam Interactions in Solids • Bulk Composition Analysis: Energy and wavelength dispersive spectroscopy • Principles of Electron, Ion, and X-ray Techniques: TEM, AES, SIMS, XPS, and TXRF • Sensitivity and Resolution Comparisons

Practical Applications and Future Challenges
• Case-Histories and Examples: Time-resolved photon emission movies of operating devices; Nanoscale 3D X-ray tomography virtual sections; Defects; Fault isolation results, etc. • Planning for Analysis to Maximize Effectiveness • Scaling and Material Challenges in Analytical Science

The educational programs are run at international venues. Venues are specially selected for cultural and historic interest and easy access to activities that encourage professional camaraderie outside the classroom. New friends might choose to ski on Davos’ slopes, admire Gaudi’s architecture in Barcelona, visit the historical Cambridge University, or have a great evening in the amusement park Tivoli in Copenhagen. Learning is not confined to formal classroom situations. Attendees often mention that ad hoc discussions after the daily lectures give rise to a surge of new ideas and possibilities. Mind-networking has become a hallmark of CEI-Europe educational programs.

If your business future indicates a need for educational themes other than those currently available from CEI-Europe, do not hesitate to contact us with suggestions. We are continually renewing both content and knowledge themes for open programs as well as corporate exclusive courses.

CEI-Europe • Box 910 • S-612 38 Finspong • Sweden Phone +46 122 175 70 • Fax +46 122 143 47 • •


March 9-13, 2009
#14 Digital Camera Systems #12 Embedded Data Converters #10 RF and Microwave Filter Design with EM Simulation #57 Synchronization & Interconnect in Multi-Clock Domain #15 Design and Simulation of RF Systems #08 Advanced RF Power Amplifier Techniques #59 OFDM and MIMO Wireless Tech. (WiMax, UMTS LTE) #58 Modern Digital Modulation Techniques 6 13 14 20 21 22 28 32 #05 Advanced Lithography Technologies and Applications #37 Micro Fabrication Technology for MEMS and NEMS #36 Silicon Device Technology Overview #87 Plasma-Assisted Etching and RIE #88 Plasma Etching for CMOS and ULSI #75 Chip Interconnection and Process Integration #95 Copper Low-k Interconnect Technology #16 CMOS/BiCMOS Process Integration and Engineering #62 Diagnosis, Debug, and Fault Isolation #61 Yield and Reliability in VLSI Manufacturing 36 37 38 40 41 42 43 44 45 46

March 30 – April 3, 2009
#20 Advanced Image Sensor Technology #60 Grounding and Shielding: The Essence of EMC Design #85 Phase Locked Loops for Wireless Com. Systems #90 RF Transceiver Architecture, Design, Evaluation #41 3 GPP LTE: The Future UMTS Standard #81 Modulation, Coding, and Iterative Techniques 5 11 17 26 30 33


September 28 – October 2, 2009
#14 Digital Camera Systems #11 Digital Signal Analysis Techniques #12 Embedded Data Converters #57 Synchronization & Interconnect in Multi-Clock Domain #15 Design and Simulation of RF Systems #08 Advanced RF Power Amplifier Techniques #41 3 GPP LTE: The Future UMTS Standard #81 Modulation, Coding, and Iterative Techniques 6 8 13 20 21 22 30 33

April 20-24, 2009
#11 Digital Signal Analysis Techniques 8 #70 High-Speed PCB Design for EMC and Signal Integrity 10 #91 Applied Radio Design: Architecture, PCB Implementation 19 #06 Linearisation and Modelling Techniques for RF PAs 23 #26 Radio System Design – Theory and Practice 24 #64 Next Generation Networks 27 #21 Advanced Array Antennas: Conformal & Beamforming 34

October 12-16, 2009
#70 High-Speed PCB Design for EMC and Signal Integrity #10 RF and Microwave Filter Design with EM Simulation #86 RF Component and System Measurements #06 Linearisation and Modelling Techniques for RF PAs #26 Radio System Design – Theory and Practice #90 RF Transceiver Architecture, Design, Evaluation #21 Advanced Array Antennas: Conformal & Beamforming 10 14 18 23 24 26 34

May 25-29, 2009
#13 Digital Imaging: Image Capturing, Image Sensors #50 Digital Speech Transmission: Enhancement, Coding #55 Signal Integrity: Advanced High-Speed Design #19 RF/MW Circuit Design: Applications and Theory #86 RF Component and System Measurements #46 MIMO and Beamforming for 4G Wireless (LTE, WiMax) 4 7 9 15 18 29

October 26-30, 2009
#13 Digital Imaging: Image Capturing, Image Sensors #20 Advanced Image Sensor Technology #56 Power Integrity: Advanced Design and Characterization #19 RF/MW Circuit Design: Applications and Theory #85 Phase Locked Loops for Wireless Com. Systems #27 Design of Advanced Radio System Architectures #59 OFDM and MIMO Wireless Tech. (WiMax, UMTS LTE) #49 4G – Fourth Generation Wireless Networking #58 Modern Digital Modulation Techniques #23 Satellite Communication Systems 4 5 12 15 17 25 28 31 32 35

June 8-12, 2009
#07 Analog Signal Processing, Bipolar, CMOS Circuit Design #49 4G – Fourth Generation Wireless Networking 16 31

Box 910 • S-612 38 Finspong • Sweden • Ph. +46 122 175 70 • Fax +46 122 143 47 • E-mail

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