886 IEEE TRANSACTIONS ON ELECTRON
DEVICES, VOL. ED-30, NO. 8, AUGUST 1983
voltage-controlled semiconductors has been demonstral ed. ACKNOWLEDGMENT
A six cell monolithic PDA, when subjectedto a norm;llly Theauthors acknowledge
gratefully contributions by S.
incidentflux of 50 mW/cm2 at865-nm peak wavelenith, Knight, J. M. Borick, D. D. Roccasecca, H. J. Braun, and the
produces an open-circuit voltage of 5.3 V and a short-circuit late D. Ketchow.
current of 33 PA,These values are more than sufficient for
numerous voltage-controlled applications.
switching “l’he REFERENCES
ability to grow an area of approximately seven square ce::lti- [ 1] W. C. King, unpublished.
meters of uniform material reproducibly, combined with the  J. A. Hutchby and R. L. Fudurich, J. Appl. Phys., vol. 47, no. 7 ,
interconnecting of the PDA elements in a single metallization p. 3140, July 1976.
 H. C. Casey, B. I. Miller, and E. Pinkas, J. Appl. Phys., vol. 44, no.
evaporation, provides a viable approach for using 111-V arr rys 3, p. 1281, Mar. 1973.
forsuch applications. The technological approach described  T.S. Moss and T.D.F. Hawkins,lnfraredPhys.,vol. no. 2, p. 111,
here could easily beapplied to other 111-V systems, such as July 1961.
 M. Sturge, Phys. Rev.,vol. 127, no. 3, p. 768, Aug. 1962.
InP/InGaAs(P), where the wider bandgap binary could be u;;r,d  L. R. Dawson, J. Appl. Phys., vol. 48, no. 6, p. 2485, June 1977.
as the “window” layer and the ternary and quaternary absob-  V. G. Keramidas, GaAs and Related Compounds 1978, Inst. Phys.
ing layers could be adjusted to a specific composition to ma ;ch Conf. Ser., no. 45, p. 396.
 M. Ettenberg, H. Kressel, and S. L. Gilbert,J Appl. Phys., vol. 44,
the emitter’s wavelength and assure efficient absorption of its no. 2, p. 827, Feb. 1973.
spectra1 range.  W. C. King, U.S. patent 4 114 177.
A New Dynamic Random Access Memory Cell Using
a Bipolar MOS Composite Structure
Abstract-A new dynamic random access memory (RAM) cell which LIST OF SYMBOLS
incoperatesan n-p-n bipolar ,junction transistor with an n-channel
MOSFET in a compositestructure, is proposedand investigated. In Base-charging capacitance of base-emitter junction.
this novel cell called the BIMOS cell, the collector-base junction serves Reverse-biased junction capacitance of base-collector
as a buried storage capacitor whereas the n-MOSFET as.a transfer g te.
The fabrication technology is simple and compatible with that sinjde-
polysilicon CMOS IC’s and a minimum cell size of 14.875F2 wit11 a CBE Reverse-biased junction capacitance of base-emitter
minimum feature size F is realizable. The write,read, andstandby junction.
operations of the cell are analyzed andsimulated. An experimental (:ell CBEJ Depletion capacitanceof base-emitter junction.
is fabricated andcharacterized. Dynamic test is successfully perform :,d. Bit-line capacitance.
The investigation on the cell performance is also made. It has shown
that large storagecapacitance to bit-line capacitance ratio as well as
Gate-source overlap capacitance.
faitly good packing density, soft-error immunity andleakage character- Parasitic capacitance.
istics are expected. Furthermore,ascompared to theconvetltiolal Transconductance of a bipolar junction transistor.
1-transistor cell the new cell can be scaled down with less process,ng Reverse saturation current of a diode.
troublesandbetterperformance improvements.Simpleprocess and Collector-emitter current with openedbase.
good scaled-down properties offer great potential for the proposed : n :w
cell to be used in the design of larger dynamic MOS RAM’S.
Leakage current of thecell.
Number of cells per bit line.
Manuscript received May 17, 1982; revised January19,1983. Tiis Charge storage i r ~the storage capacitor of the cell
research was supported by the National Science Council, Republic of storing binary l(0).
China under Contract NSC71-0404-E009-05.
The author is with the Institute of Electronics, National Chiao Tung Storage time of thecell.
University, Hsin-Chu, Taiwan, Republic of China. Transient (final) base-emitter voltage.
0018-9383/83/0800 -0886$01.OO 0 1983 IEEE
WU: DRAM CELL USING BIPOLAR-MOS COMPOSITE STRUCTURE
Coupling voltage atthestoragenodeofthe
storing binary l(0).
CELL A ,j CELL B 1
Power supply voltage. AL BIT LINE 1 POLY-Si WORD LINE
Signal size of the cell,
Standby bit-line voltage.
Storage node voltage in the cell storing binary l(0).
Threshold voltage of a MOSFET.
- VSl - VSO.
Change of transient base-emittervoltage during A t .
Time period of the write binary 0 operation. VQD P N CAPACITANCE
F R CHARGESTORAGE
Current gain of a bipolar junction transistor. (a)
Forward base transit time bipolar junction
N the past decade, dynamic random access memories
L A M 's) have evolved continuously toward larger bit (b) ( c)
capacity, higher performance, cost
and lower per bit. To Fig. 1. (a) Cross-sectional views of two new dynamic RAM cells; equiv-
achieve these goals, many such
factors as the signal size, alentcircuit of (b) a new dynamic RAM cell; (c) aconventional
leakage rate, packing density, complexity of clocks, and fabri- 1 T cell.
cation complexity shoulld becarefullyconsidered [ l ] . Since
thesefactorsstronglydependupontheperformance of dy- 11. CELLOPERATIONS
namic RAM cell itself, considerable efforts have been concen- The basic integrated structure of the proposed new dynamic
trated on thecell design and improvement. RAM cell is shown in Fig. l(a). This cell mainly contains an
So :far the one-transistor-one-capacitor(1T) cell structure [ 2 ] n-MOSFET siting on a p-well. The polysilicon gate is extended
has been the most popular one used in current MOS dynamic to form the word line while the aluminum line, which contacts
RAM'S , Such a cell stores acharge packeton an MOS one of the two n++ regions in the n-MOSFET, is extended to
capacitor with a MOS transistor as a transfer gate for charging form the bit line. The other n++region is connected to the p+
and discharging. However the 1T cell suffers from low packing region of the p-well through an aluminum contact. Besides the
density and high leakage rate which will become more n-MOSFET M I , there is a merged BJT Q2 with the n-substrate
severe as the bit capacity reaches 64Kor higher. Therefore, as collector, p-well as base, and n+* bit line diffusion region as
mtny new concepts [ l ] have been explored to construct new emitter.Thusthe equivalentcircuit of the new cell may be
cells ,with higher performance. One o f these concepts is the drawn as in Fig. l(b). As compared with the 1T cell circuit
buried junction storage whichhas been used inthe VMOS shown in Fig. I(c), the M I transistor in the new cell serves as
dynarnic RAM cell [ 5 ] , the punchthrough isolated (PTI) cell a transfer gate to charge or discharge the storage capacitor,
, and the BO-MOS dynamic RAM cell , All these new similar to the M 3 transistor in the1T cell. However, the
cells need epitaxy process and/or V-groove etchingprocess storage capacitor here is base-collector p-n junction capacitor
which. are more critical and camplex than that in conventional which lies beneath the M I transistor, instead of an MOS capac-
MOS [C's. itor upon the semiconductorsurface as in the case of 1T cell.
This paper demonstrates a new cell design which incorporates To write 1, the word linepotential of the selected cell is
an n-p-n bipolar junction transistor (BJT) with an n-channel rised from 0 to 5 V and its bit line potential is also rised to
MOSFET in a composite: structure. In this new cell which is 5 V. At this time, the transistorMl is turned on and the p-well,
called the BIMOS cell according to its structure, the collector- Le., the base region of the transistor Q 2 ,is charged. Then the
base junction capacitor of the merged BJT serves as a buried bit line is left floating by a clock such as chip-enable clock.
storage element whereas the MOSFET as a transfer gate. The During this time, the word line potential is dropped to 0 V.
fabrication process of the new cell is compatible with that of At last the whole write 1 operation is finished by promoting
the CMOS IC's. Moreover, it shows a goodcompromise be- the bit line potential to standby level VREFwhich is equal to
tween cell performance amd process complexity. In Section I1 VDD(5 V). If the charging action is complete, just after the
of this paper, read, write, and standby operations of the new write operation,the voltage at the base terminal called the
cell are analyzed.The cell performance including chiparea, storage node is
signal size, leakage considerations, and process compatibility,
is investigated in Section 111. In Sections IV and V, experi- vSl = vDD - vth* (1)
mental results of the test cell, simulated transient waveforms, To write 0, the operation is similar to that of write 1 except
andtheperformance of the scaled-down cell aredescribed. to
that the bit line potential is lowered 0 V. During the opera-
Discussion and conclusion are madein the last section. tion, the storage node potential first is discharged to 0 V and
888 IEEE TRANSAI:'TIONS ON
ELECTRON DEVICES, VOL. ED-30, NO. 8, AUGUST 1983
finally is rised to some positive level by the capacitance cou. where the forwardbase-emitter junction capacitance is the
pling effect. Therefore, after
just the write operation, tht: sum of base-charging capacitance CB = TFgm which is the
voltage level Vso may be expressed by dominant component, and the forward depletion capacitance
vso = vco (21 Assume that the deselected cell storing binary 1 is continu-
ously subjected to the write or read binary 0 operation, the
where Vc0 is the coupling voltage on the junction capacitanc,: worst-case storage node voltage can be expressed as
CBC through CBE. Since CBC and CBE are all voltage depen"
b 1 , m i n = V B E ~VCI (4)
dent, Vco should be determined by the transientcalculations.
To determine the final voltage at the storage node, the c e % where VBEfis the final base-emitter voltage when the bit line
afterthe write l(0) operation is considered to be always voltage is 0 V, and Vc1 is the coupling voltage. Note that V C ~
deselected before the
next refresh cycle reaches. If this is greater than Vco since the initial condition for Vcl has a
deselected cell is subjected to the standby operation, the bit larger forward-biased emitter-base junction capacitance CBE.
line potential is kept at 5 V ( VREF)and two junctions of the From the above considerations, it is seen that if A VBE,is
bipolar transistor are reverse-biased. Thus the storage node I S negligibly small, both VBEF and V ~ l , willbe nearlythe
isolated from the bit line except that small reverse saturation same as those in the fist time the bit line voltage is 0 V, and
current and leakage current flow through both reverse-biaseS the stored voltage will be not severely distributed. However,
junctions. Although these currents tend to increase the poter.. if A V B ~is large, V B E will be equal to the steady-state open-
tial of storage node, such increase is so small that the potenti;ll base base-emitter voltage, and the binary 1 will be held with a
of storage node will be nearly undisturbed. In the read and the lower V S I , ~ ~ .
write binary 1 operations, bit line potential is either 5 or nelr In the case of very large CBc/CBE ratio, both VC, and VCO
5 V. Thus the deselected cell is not severely disturbed as i n are small. Thus VSo 0, Vsl,mh V B E ~ , the and stored in-
the standby case. formations will still be not destroyed. It should be emphasized
In the write orread binary 0 operation, the bitline potenti;ll that only when the storage node voltage of the deselected cell
is lowered to 0 V. At this moment, the storage node of the storing binary 0 has enough long time to be charged to V B E ~
deselected cell storing binary 0 is also lowered toa small the stored information could be destroyed.
positive residue voltage which is generated during the standby Intheproposed cell structure,boththeemitterand base
period by the charging of small currents in reverse biased jun ;- impurityconcentration difference andthe base width, i.e.,
tions. As the bit line remains a t 0 V, the increasing rate of this the and
difference of p-well depth source/drain depth, is
residue voltage willbe lower thanthat in thestandby c a x rather large. This leads to a large PTF. Furthermore, the time
because charging currents to the storage node from the two period At in the write or rewritebinary 0 operation can be
junctions are opposedratherthansuperposed.Afterthe bit small as will be seen in Section IV. ThusA VBETcan be strictly
line potential is rised back to 5 V, the storage node potentiil reduced. With very small A VBE,, each time the stored binary
is also rised to that of binary 0 and the original stored data is 1 level in the deselected cell storing binary 1 is recovered from
restored without destruction. one write or readbinary 0 operation, the loss of its storage
For the deselected cell storing binary 1, the voltage o n t l e node voltage is quite small.
storage node is high. As the bit line potential is decreased lo When the cell is scaled down, the base area is reduced and a
0 V in the write or read binary 0 operation, the storage notle smaller CBc is resulted.The base-emitter C B is, however, ~
voltage is decreased according to the capacitance coupling also reduced toobtainthe same or larger CBC/CBE ratio.
effect between base-collectorjunction capacitance and emitter- Moreover, in the scaled-down cell, both the depth and theim-
base junction capacitance. Finally, the emitter-base junction purity concentration of the sourcejdrain and the p-well can be
forward-biased while the base-collector junction is kept reverse- designed to obtain thesame large PTF and the smaller At. Thus
biased. At this moment,thetransient base-emitter volta1:e very small AV,, can also be obtained. Under this case, the
V B ~ which is determined by the base-collector and base- stored binary 1 in the deselected cell is still not distroyed.
emitterjunction capacitances during procels,
.the transient From ( 2 ) and (4), the stored charge quantity on the storage
tends to be decreased by the base-emitter discharging currer!i. capacitor of the cell is written as
This current is formed by the netflow of: 1) holes injected fro)m
base to emitter; 2 ) electrons injected from emitter and not col- Qil = C B C ( ~ D D - Vs/sl,min)=CBC(VDD - VBEf- Vc1)
lected by the collector and 3) holes injected from collector :o (5)
base. The first two components are just the base current under
VBET whereas the last component is approximately the reverse Qto = CBC( ~ D - VSO)D (6)
saturation current IC, of the base-collector junction. Thus tlre where Qil
change of VB,, during the time period t can be written as
(eio) is the charge quantity when the cell stores
l(0). Therefore the signal swing on the bit line withcapaci-
tance CBL is
A vBET = (IC0 - Ic/O)At/(cBEJf CB)
v T A t ( r C O / T ~ I ~- 1 / p T ~ ) 1)
WU: DRAM CELL IJSING BWPOLAR-MOS COMPOSITE STRUCTURE 889
The line per cell generally contains three
components: 1) CBE in series with CBC;2 ) gate-source overlap
capacitance C,, which is much smaller than that in l), and 3)
parasitic capacitance Cp which is also much smaller than that
in 1). For a bit line with n cells connected in it, CBL may be
Substituting (8)in (7), wehave
B. Storage Capacitance
In general the p-n junction reverse-bias capacitance per unit
area is lower than the MOS capacitance per unit area. This
disadvantage can be compensated partially by the fact that the,
entire cell area is available for the p-well which forms the cell
storage capacitor with the n-substrate, and the fact that the
depth of p-well is large to provide considerable sidewall
From (9), it is seen that the signal size is strongly dependent capacitance. Moreover the diffwion the
n+ on n-substrate
upon the capacitance ratio CBEICBC. As the bit capacity in- between p-wells is effective to increase the sidewall capacitance.
creases, n increases and CBE/CBCshould be decreased in order According to the cell layout in Fig. 2 , the bottom area of
to ob.tain a detectable VI" The decrease ofjunction capacitance p-well is 7 times that of n++ region whereas the typical depth
ratio CBE/CBC can be achieved increasing
by CBC and/or of p-well is nearly 4 times thatof nt+ region. Furthermore, the
decre;asing CBE which are all feasible through various process
difference between doping concentrations of two p-n junction
capacitance CBc and CBE is offset by the n" diffusion on the
111. PERFORMANCE substrate. Therefore the ratio CBC/C'E can be made large to
obtain a larger signal size.
A. Chip Area
Since every cell has its own p-well as shown in Fig. 1, the C. Leakage Considerations
spacing between two p-wells is the most important parameter The leakage current of a reverse-biased p-n junction generally
in determining the cell area. Fortunately, the spacing can be increases with the junction area and decreases with the impu-
strict:ly minimized due to thefollowing reasons: rity concentration. Therefore the storage capacitance CBc has
a) Only n-regions are connected to the power supply or the a larger current than the bit line capacitance CBE when the cell
bit line while all p-regions are left floating. There is n o way is in its standby mode. However,these two currents are ex-
for the hold current to flow. Thuslatchup cannot occur among pected to be low even at high bias because the p-well doping is
the cr:lls. quite low to effectively reduce tunneling  in both reverse-
b) The n+ region between two p-wells, which is formed be- biased junctions despite of the high doping concentration of
fore p-well implantation has a higher impurity concentration both n+ and n++ regions.
than the p-well region. Thus the lateraldiffusion of p-well and The n+ region between p-wells is effective to decrease the
the space charge width in n+ region are effectively reduced. numbers of hole-electron pairs generated in the depletion
c) The vertical scale down of p-well  alsoreduces the region by a-particles or cosmic rays [ l o ] andto repel the
spacing between p-wells. migratingholes fromthe bulk [ 7 ] . Thereforethesoft-error
Although an extra contact is needed, the of this contact immunity is not worse than the conventional 1 T cell.
plus 'other spacings is expected tobe smaller than that of capac-
itor .in conventional 1T cell. Thus the total chip area of the D. Process Compatibilities
new cell will be smaller. Based onthe single-poly process As maybe seen from the integrated structure of the new
technology with minimum feature F and the same design rule cell shown in Fig. l(a),thefabrication process is similar to
in the BO-MOS cell  , the minimum cell area is 14.875F2 as that of Si-gate p-well CMOS except an extra n+ implantation.
indicated in the layout shownin Fig. 2. For F = 3 Bm, the area Thus the cell can be easily fabricated by using the conventional
is 134 pm2 which is smaller than that of 1T cell and VMOS technologies without paying a lot of efforts to develope other
cell, comparable with that ofHi-C cell [ l ] and PTI cell, but complicate or difficult processes. Moreover, the peripheral
larger than that of a BO-MOS cell. circuits can be built with CMOS, the way leading to a simpler
IEEE TRANE/"rCTIONS ELECTRON DEVICES, VOL. ED-30, NO. 8, AUGUST 1983
TABLE I -.
TYPICAL PROCESSES NEWCELL
OF THE 1 --- BIT LINE
x x a STORAGE NODE
1. Thermal o x i d a t i o n
2. CVD Si3N4 and CVD S i 0 2
3. P - w e l l d e f i n i t i o n (Mask #1)
4. N+ r e g i o ni m p l a n t a t i o n (AS)
5. F i e l do x i d a t i o n (LOCOS)
6. S i 3N 4 remove
8. Drive-in and oxidation -1.01
0' 10 x) 30 40 V" 501 v
, =, ,
60 70 El 90 100 XTj
9. A c t i v er e g i o nd e f i n i t i o n (Mask # 2 ) TIME (NSEC)
10. Gate o x i d a t i o n Fig. 3. Simulated timing diagram of the write operation.
11. CVD p o l y s i l i c o n
12. G a t ed e f i n i t i o n (Mask # 3 ) TABLE I11
PROPOSED DEVICEM E N S I O N IN THE SCALED-DOWK
13. P+ r e g i o nd e f i n i t i o n (Mask # 4 )
14. P+ i m p l a n t a t i o n
P-well Depth (urn)
15. N++ r e g i o nd e f i n i t i o n (Mask 15)
Depth Source-Drain Ipm) 0.1
16. N++ implantation N+ Depth (Pm) 0.5
17. CVD S i 0 2 Surface
Concentrations A l l Unchanged
18. Ohmic c o n t a c to p e n i n g (Mask X6)
19. M e t a l l i z a t i o n (Mask #7) TABLE IV
20. P a s s i v a t i o n (Mask 1 8 )
CALCULATED JUNCTIONC I T A N C E S A N D T H E I R R A T I O S A T
DIFFERENTN I M U M FEATURE
SIMULATED SURFACE CONCENTRATION AND DEPTH
JUNCTION O F T H E DEVU:
N++ E m i t t e r ax1019 0.508
N+ Diffusion 5x10~' 1.540
P-Well 5x1oI6 2.690
Fig. 3. The capacitance of the bottom plate in B-E and B-C
N-Layer I 5 x 1 0 ~ ~ I -
junctions is calculated by the method proposed by Lin .
The sidewall capacitance of the p-well touching the n-region is
circuit design [ I 11 and a better balance of power and speed calculated by the conventional method [ 151 whereas the side-
[I21 wall capacitance of the p-well touching the n+ region and the
To be compatiblewiththe n-well CMOS technology,the sidewall capacitance of B-E junction, both being of double
proposed cell can also be made on p-substrate with an n-well ;is Gaussian distribution, are calculated by the numerical method
its storage node and an p+ region as its emitter. . Based on these methods, a simulation program for the
reversed junction capacitance has been constructed to simulate
IV. SIMULATED RESULTS the cell capacitances.
The proposed fabrication processes of the new cell with a According to the cell layout shown in Fig. 2 and the simu-
p-type well are listed in Table I whereonlymain steps are lated profiles, a scale-down onthe dimension of the cell is
concerned. Except the n+ region implantation which may als 2 proposed, as shown in Table 1 1 to investigate the performance
be viewed as a kind offield implantation, the processes are juzt of the scaled-down cell. Both the p-well and the source-drain
the same as those of a typical p-well Si-gate CMOS. Based 0.1 junction depths are not subjected to scale down until the mini-
the actual process parameters, the simulatedsurface concentrz - mum feature size is below 3 pm. The surface impurity concen-
tions and junction depths the cell, which are generated frorl trations ofall theimplantation regions remain the same as
the SUPREM program , are shown in Table 11. those in Table I for all values of F .
To calculate the reversed junctioncapacitance, all the im- ,
The total capacitanceratio CBc to C and,their sidewall
planted profilesare assumed to be of Gaussian distributio~r capacitance ratioforthe cells storingbinary 1 arelistedin
which is agoodapproximationtothe simulatedprofiles ill. Table IV. For the cell with the n+ diffusion outside the p-well
WU: DRAM CELL USING STRUCTURE 891
the ratioincreases from 3.8 at F = 5 pm to5.2 atF = 3 pm and TABLE V
CALCULATED VOLTAGELEVELS N U M B E R OF C E L L S PER BIT LINE
finally to 14.8 at F = 0.5 pm. This implies that when the cell 100-mV SIGSAL
SIZE THE CELLS
IN WITHDIFFERENT CBC/ CBE
area .is scaled down in order to be used in a larger RAM, the
ratio of storage capacitance t o bit line capacitance is favorably 8=250 T
F =0.7ns VTh'l. ov
increased without invohing critical processes such as thin c,,=0,016pf (-4V bias)
capacitor oxide growth as the conventional 1T cell should do.
This increase is due to th.e following reasons:
a) Due to the logarithmic dependence of the sidewall capac- VRFIT (v) I 0.4547 I 0 . 4 402.641208.7118 5 0
itance per unit area on the depletion width 151 ,the difference
[ 3.03 2.21 1.09
of the sidewall capacitance density between B-C and B-E junc- 'Sl,rnin ("
tions is smaller thanthat of thebottomplatecapacitance vso (VI 0.73 1
0.39 . 7 5 2.37
density. Therefore the total sidewall capacitance in the B-C
junction which has a larger sidewall area, is larger than in the
number of cells I 150 1 80.6 I 36 1 28
B-E junction and their ratio large as may be seen from Table
IV. When the horizontal dimension is scaled down by a factor
K and the vertical dimension remains unchanged, the sidewall
area anditscapacitance become more and more significant.
Theriefore, although the sidewall capacitance ratio is not
changed, thetotalcapacitanceratio is still increased from
F = 5 pm to F == 3 pm as listed in Table IV. The increase of
sidewall capacitance ratio when F is smaller then 3 p m is due
to th.e increase in the percentage of p-well sidewall area touch-
ing the n+ region.Thisincrease also contributes part of the
increase of the ratioCB~-/CBE.
b) The p-well depth is scaled down under the fixed surface ( W CELLSlBlT LINE)
A A A BIT LINE ( 1 )
impurity concentration. This leads to a lower p-well concentra- 0 0 0 BIT UNE (0)
tion at theB-E junction and a larger gradient at the B-C junc-
tion.Thereforewhen scaled down, CBE is decreased more
fast .than CBc is, as listed in Table IV. This leads to the result
that the ratio CBC/CBEis remarkably increased from F = 2 pm
to F = 0.5 pm as listed in Table IV.
For the purpose of comparison, the ratios and capacitances TIME (NSEC)
for the cell without the n+diffusion are also listed in Table IV. Fig, 4. Simulated timing diagram of the read operation.
The increase of CBC by the n+ diffusion can be easily seen.
For the cell storing binary 0, the characteristics are similar to
those of the cell storing binary 1 cited earlier.
To show the dynamic characteristics of the cell, the voltages
of V&,, VB,, Vel, and VCO are simulated by using the SPICE
program  and are listed in Table V for different CBCICBE.
In this table, the value of VBE, is determined at the first time
the bit line is lowered to 0 V just after 'the write 1 operation,
(VS,) is ~
that of V S ~ , ~ determined from the worst case that
the bitline voltage has been kept at 0 V ( 5 V) 2 ms long. Fig. 5. Surface photograph of a fabricated cell.
Based on these data, the number of cells n which can be con-
nected together on one bitlineandcanoffer 100-mV signal The corresponding read transient is shownin Fig. 4 where
size in the worst case, is estimated by (9) and is also listed in the bitline capacitance CBL is 1 PF which is equivalent to
Table V. It may be seen that at larger value of CBC/CBE, the that of bit line with 6 4 cells on it. The signal swing of 1 12 mV
signal swing V S ~- VSO~is smaller than the value of VDD -
, ~ can be obtained within 10 ns.
Vth. Therefore the value of n is smaller than the 1T cell for
the same line capacitanceto storage capacitance ratio. V. EXPERIMENTAL RESULTS
However, the CBC/CBEratio is large when the cell is scaled To observesome properties of the proposednew dynamic
down. Thisleads to a large enough n value to beused in a RAM cell, a test chip for the new cell is designed by using
large DRAM. 10-pm design rule. The fabrication processes are the same as
Typical write transient waveforms in the case of large (=10) listed in Table I except that the n+diffusion region outside the
CBC/CBE which is the practical condition for DRAM cells,
ratio p-well is simply defined by an extra mask rather than by the
are shown inFig. 3. It is evident that V S ~ V B~~and N , f~ LOCOS method. The surface photograph of the fabricated cell
YSO2: 0 as predicted in Section 11. is shown in Fig. 5 . The measured capacitance at various
CAPACITANCELEAKAGE CURRENT DENSITY
JUKCTION AND O F THE
EXPERIMEUTAL CELL -2v Reverse B ~ o s
-4V Reverse BIOS
8 - E Junctlon
-2V Rwerse Bias
IC 4 V Reverse 810s
B-C Junction wtth N' Diffusion
-2V Reverse Bias
-4V Reverse Bias
B - E Junctton
--M- .25um x 25um
C2 . 4 0 u m x 4 0 ~ l m
-. + (C,-C2 I 2 . % ) I C ,
8-C Junctlon wth N' Dlffusim
CJ : 50umx30urn
Temperature ( T )
Fig. 7. Leakage current as a function of ambient temperature in various
Since the leakage current in the sidewall junction which has
higher impurity concentrationis smaller than thatin the bottom
junction and the contribution of sidewall become more signifi-
cant than that of bottom wall when scaled down. Thus the
Reverse - Bfased Voltage (Volt) total leakage current density of the whole junction is smaller
Fig. 6 . Characteristics of capacitance increment in the scaled-dow a in the smaller junction than in the larger one as listed in Table
B-C and B-E junctions. VI. Similar result is also obtained in the case of B-E junction.
When the reverse-biased junction voltage exceeds 1 V, the
reverse-biased voltages for the base-collector junction wit.l variation of capacitance with temperature in both junctions
andwithoutn+ diffusion andthe base-emitter junction are are observed to be negligibly small. However the leakage cur-
listed in Table VI. As may be seen from Table VI, the capac . rent is increased with the increase of ambient temperature as
itance is increased bythen+ diffusion.However, since th.s shown in Fig. 7 where the B-E junction, the B-C junction with
fabricated cell is not optimized in its dimension, the capac .I n+ diffusion, and the B-C junction without n+ diffusion are
tance CBE appears larger than CBC. Theoretical calculatiorrs measured. It may be seen that the n+ diffusion in the sidewall
are also compared to the experimental results and a satisfactor:/ is also effective in reducing leakage current. From Fig. 7, the
agreement between them is obtained. total leakage current I, of the cell storing binary 0 is about
To investigate the scale-down properties of the cell capaci. 1.25 pA at 25°C. For the averaged storage capacitance C ~ = C
tances, the capacitances of two B-C junctions with anare,] 0.44 pF and voltage swing between 0 and 1 A V = 1 V, the
ratio 4 and two B-E junctions with an area ratio 2.56 are mea- storage time t, of the fabricated cell may be estimated by 
sured and the results are shown in Fig. 6. Due to the contri-
ts = C, A V/IL = 350 ms.
bution of the sidewall capacitance as mentioned in Section IV,
the capacitance of the scaled-down B-Cjunction is larger tharl When the cell is operated at 120"C, the storage time reduces to
one-fourth of the capacitance of the larger B-C junction b:!r 6 ms due to a larger I, = 73 PA.
24 percent. It is larger than that of B-E junction, 1 2 percent. Dynamic test of the fabricated cell is also performed. The
Therefore the scale-down is effective to increase the ratio waveforms in the write 1 and standby operations are shown in
CBClcBE * Fig. 8(a) with test circuit shown in Fig. 8(b). The cell is first
Typical leakage current density of two B-C junctions a : selected to write 1 andthen is deselected.During the dese-
various reverse voltages is listed in Table VI where the increasc lected or standby period, the bit line voltage is subjected to
of currentwith respect to the increase of voltage is rathe. several timesofdropingto 0 V. However, the storage node
small. Therefore the tunneling current component 191 in thes(: voltage can followthe bit line voltage changes and recover
junctions is negligible. itself without destroying the stored binary 1. Note that short
WU: DRAM CELL USING BIPOLAR-MOS COMPOSITE STRUCTURE 893
the effect of the externalcircuit the charging of write 1 is slow
down in this test.
VI.DISCUSSION AND CONCLUSION
We have proposed a new dynamic RAM cell which consists
of an n-channel MOSFET as atransfer gate and a base-collector
junction of a merged BJT as a storage capacitor. The write and
read operations of the new cell have been analyzed, described,
and simulated. It has been shown that the signal size depends
upon the capacitance ratio of the base-collector junction and
the base-emitter junction. In the standby operation, the cell
leakage current is small enough to obtain a good data retention
capability.Thestoreddata in the deselected cell is not de-
stroyed by thebit line potentialvariations.
Due to the facts that latchup cannot occur and lateral dif-
fusion width is reduced by the n+ diffusion, the spacing
between p-wells can be strictly minimized. Thus a minimum
area 14.875F2 with a minimumfeature size F is realizable.
Furthermore,then+ region between p-wells is effective to
error immunity of the cell is not worse than the conventional
Fig. 8. (a) Dynamic waveforms of the write 1 and standby operations; 1T cell.
(b) its test circuit.
Unlike other cells using the buried junction storage, no epi-
taxy or I/-groove cutting is required. The fabrication technol-
ogy of the cell is fully compatible with that of p-well or n-well
Si-gate CMOS.Using the p-well silicon-gate CMOS processes
and relaxed design rule, the experimental cell is fabricated and
tested. The fabricated cell has a leakage current of 1.25 pA at
25°C and an averaged storage capacitance of 0.44 pF, which
lead to a storage time of 350 ms. Dynamic test of the fabri-
cated cell is also successfully performed to verify the cell
operation descriptions.However, because optimal dimension
is not performed in the fabricated cell, the capacitance ratio is
small. Furtherimprovementsonthe cell will be doneand a
whole test RAM IC will be fabricated in the near future.
When the cell is scaled down, the capacitance ratio is simu-
lated to be increased from 3.8 at F = 5 pm to 5.2 at F = 3 pm
and finally to 14.8 at F = 0.5 pm, This is due to the contribu-
tions of both thesidewall junction and the p-well doping profile.
The number of cell per bit line for 100-mV signal size is also
increased as the cell is scaled down. Furthermore the leakage
current density is reduced when scaled down.
In summary, the proposed new cell has simple fabrication
process and good performance of large storage capacitance to
bit-line capacitance ratio, as well as fairly goodpacking density,
(b) soft-error immunity and leakage characteris.tics. Moreover, as
Fig. 9. (a) Dynamic waveforms of the write 0 and standby operations; compared with the conventional 1T cell, the scaling down of
(b) its test circuit.
the cell can be performedwith less processing troublesand
better performance can be obtained. Thus it is felt that the
clocksareused to prevent the cell from discharging through new cell has great potential for furtherdevelopments.
the input resistance of the probe. Thus the storage node volt-
age can be directly observed. ACKNOWLEDGMENT
The waveforrns in the write 0 and standby operations are The author wishes to thank D. J. Neiu, M. Z. Lin, and the
shownin Fig. 9(a) with the testcircuitshownin Fig. 9(b). Technical Staff of Semiconductor Research Center, National
The cell is first selected to write 1 and then write 0, finally is the
Chiao Tung University for fabrication of the devices.
deselected andstandbyat binary 0. The voltage difference Valuable suggestions by the reviewers are greatfully acknowl-
of the storage node between 0 and 1 is clearly seen. Due to edged.
a94 IEEE TRANSti.::TIONS ON ELECTRON DEVICES, VOL. ED-30, NO. 8 , AUGUST 1983
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Silicon-Rich Si02 and Thermal Si02 Dual Dielectric
for Yield Improvemenmt and High Capacitance
STEFAN K.-C. LAI, D. J. DIMARIA, AN3 FRANK F. FANG, SENIOR MEMBER, IEEE
Abstract-The use of silicon-rich Si02 and thermalSiO2 dual dielectric device dynamic memory cells [ 1] thus increasing signal levels
in memory capacitors and FET’s is investigated. It is shown that thc and reducing the impact of alpha particles [ 2 ] , increasing
silicon-rich layer was conductive and introduced only a small decreasc:
in the series capacitance of the dual dielectric. Consequently, the capac
transconductance of FET’s, and reducing short-channel effects
itance of the dual dielectric is close to that of the thermal oxide only, [ 3 ] . Insulators like silicon nitride  and tantalum pentoxide
The response time of the silicon-rich layer is measured by using FE’I [ 5 ] have been proposedand used to give higher dielectric
response time and is shown to be in the nanosecond range. With thi;! constantcomparedtothatofthermaloxide. However, the
fast response time, it is possible to use the dual dielectric in memoq, use of such insulators is still experimental, and their compati-
and logic circuits. Another advantage of the dual dielectric is the ver!,
high yield due to the field screening of the silicon-rich layer to an) bility with standard polysilicon gate processing and long-term
nonuniformities in the thermal oxide or at the SiOz-contact interface reliability are questionable.
This dual dielectric has the promise of high yield and high capacitancc Recently, it was demonstrated thatsilicon-rich silicon dioxide
for future VLSI circuits. (deposited by CVD with approximately 13-percent excess
silicon)  could be used on top of thermal silicon dioxide for
I. INTRODUCTION . enhanced electron injection into the oxide  - [ 9 ] . Further-
more, silicon-rich oxide has a high dielectric constant (approxi-
I N VLSI circuits, a high-dielectric-constantgate-material is
desirable.can increase storagecapacitancein 1- mately 7.5 in the above composition) and such a composite
structure has been demonstrated to have well controlled high
Manuscript received December 24,1982; revised March 14,1983 field conduction properties  . In the low field region (less
Thiswork was sponsored by the DefenseAdvanceResearch Project! than 5 MV/cm) where there was no significantinjection of
Agency (DoD) ARPA order number 4012 under Contract MDA903-81’ electrons, such a dual dielectric gave higher capacitance com-
C-0100 issued by the Department of Army,Defense Supply Service
Washington, DC. pared to pure oxide of the same thickness and had very few
S. K.-C. Lai was with IBM Thomas J. Watson Research Center, York low field breakdowns, giving high yields [ 9 ] . It will be shown
townHekhts. NY 10598.He is now withIntelCorporation, Sant;i in this paper that under suitable conditions, the response time
Clara, CA% OS 1.
D. J. DiMaria and F. F. Fang are with IBM Thomas J.Watson Researct of stored charge in the silicon-rich layer can be in the nanosec-
Center, Yorktown Heights, NY 10598. ond range,fastenough to be used in mostcircuits. Froma