Switched Current Memory Cell Using Floating Gate MOSFET by lq3233

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									J. of Active and Passive Electronic Devices, Vol. 2, pp. 261–269                       c 2007 Old City Publishing, Inc.
Reprints available directly from the publisher                     Published by license under the OCP Science imprint,
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            Switched Current Memory Cell Using
                  Floating Gate MOSFET

                          M ANEESHA G UPTA∗ AND R AHUL S URI

                       Electronics and Communication Engineering Department,
                       Netaji Subhas Institute of Technology, New Delhi-110045



        An implementation of switched-current memory cell in floating gate
        MOSFETs (FGMOS) technology is presented. The sampled and hold
        circuit built using FGMOS based memory cell has better performance
        due to the increased gate to source capacitance inherent to the FGMOS
        technology. Noise analysis shows improved performance of the proposed
        memory cell over conventional memory cell. Pspice simulations have
        been used to validate the theoretical predictions.

        Key words: Analog current mode circuits, switched current, floating gate
        MOSFET.



1 INTRODUCTION

Switched current technique is being extensively used in the design of
differentiator and integrator circuits, Switched current filters, Analog/Digital
converters, Sigma-Delta converters [1, 2]. The switched current circuits
can be build through MOSFETs without the need of any special design
process which makes it ideally suitable for mixed ICs for implementation
in standard CMOS technology.
   The non-ideal behavior of switched current memory cell results mainly
from clockfeedthrough [3] switch charge injection [4], non zero output
conductance [5] and settling time. Several design techniques have been used
to remove these imperfections [6, 11]. Many researchers have analyzed the
cause and effects of noise in current memory cells [3, 4] and proposed the
measures to reduce it but there haven’t been many practicable solutions


   ∗ Corresponding      author: E-mail: maneesha.gupta 60@gmail.com



                                                         261
262                               G UPTA AND S URI




FIGURE 1
Floating Gate MOSFET (a) Layout (b) Equivalent Model (c) Symbol.


that have been implemented. The FGMOS‘s have been used in switched
current memory cell [12] for the low voltage applications.
   This paper aims at introducing a new implementation for switched current
memory cell using multiple input floating gate MOSFETs (FGMOS) for
improved noise performance. FGMOS can be used instead of MOSFETs
in other switched current circuits so that a new class of switched current
circuits can be evolved. The enhancement proposed for the memory cell is
superior as it retains the same number of transistors with improved noise
performance.


2 FGMOS AS CMC

A multiple input FGMOS is shown in Figure 1. It consists of an n-MOS
having a electrically floating gate electrode. The floating gate, which is
built on the conventional Poly1, is capacitively coupled to the input control
gates built on Poly2.
   If the total initial charge on the floating gate is removed by ultraviolet
light [8, 9], then the voltage at the floating gate of a FGMOS can be
expressed as:
                                             n
                                       1
                              Vfg =               Ci Vi                   (1)
                                      CT    i=0
                                       n
                              CT =          Ci                            (2)
                                      i=0

where C0 is the capacitor formed between the floating gate and the substrate,
and C1, C2 , C3 . . . Cn are the capacitors between the control gates and the
floating gate. V0 is the substrate potential and Vi represents the voltages
     S WITCHED C URRENT M EMORY C ELL U SING F LOATING G ATE MOSFET           263




FIGURE 2
Floating Gate MOSFET as used in the memory cell. (a) Equivalent Model (b) Symbol.


of the input control gates. Figure 1b shows the symbol used for FGMOS
and Figure 1c show the equivalent model for FGMOS.
   The FGMOS memory cell employs 4-input floating gate transistors
(Figure 2). While one of the input control gate is used for analog signal
processing as in the case of a MOSFET in a conventional memory cell, the
other three control gates are grounded. Since in this structure, the source of
the FGMOS is grounded the net gate to source capacitance (Cgs) increases
as compared to Cgs, in a conventional memory cell. The substrate of the
FGMOS is at ground, therefore all the capacitances are in parallel. Thus,
in FGMOS the effective gate to source capacitance Cnet increases. Cnet
can however be further increased by using more number of input control
gates for FGMOS. The increase in Cnet can be exploited to reduce noise
level in the memory cell.


3 FGMOS MEMORY CELL

The CMC designed with FGMOS in place of MOSFET is presented
(Figure 3). During the phase φ1 , the input current Iin adds to the bias
current J and the sum of the two currents flows into the initially discharged
gate to source capacitance, Cnet of the floating gate transistor. As a result
the capacitance Cnet begins to charge and as the voltage across it exceeds
the threshold voltage, the floating gate transistor T1 conducts. When Cnet
becomes fully charged, the entire current J + Iin flows into the drain of
the FGMOS.
   When phase φ2 occurs, the current J + Iin is sustained in the drain
because the gate-source voltage is maintained constant by virtue of the
charge stored in the capacitor. Thus during φ2 the output current i 01 is the
264                             G UPTA AND S URI




FIGURE 3
FGMOS Memory Cell.


difference of the bias current and the drain current written as:
                       I01 = J − ( J + Iin ) = −Iin                   (3)
   In order to obtain a memory of the input current throughout the entire
clock period φ1 and φ2 , the circuit can be modified by adding another
FGMOS as shown in Figure 4. The output current I02 flows during the
sampling phase φ1 and the holding phase φ2 by current mirror action.
   If the two FGMOS transistors are matched then,
                                I02 = −Iin                            (4)




FIGURE 4
FGMOS Memory Cell Modified.
    S WITCHED C URRENT M EMORY C ELL U SING F LOATING G ATE MOSFET       265

4 NOISE REDUCTION

Noise in switched CMC results from the transistor switch and the copying
transistor. For a MOS, noise has two components, thermal noise and 1/ f
noise. For a transistor in saturation with transcondutance, gm the thermal
noise current power spectral density is given as follows [7]

                        i t2           2gm
                             = 2kT              −∞ f ∞                   (5)
                         f              3
   The 1/ f noise component has a power spectral density that decreases
as frequency increases and is expressed as:

                                i t2           2
                                        K f n gm
                                     =                                   (6)
                                 f     Cox W L| f |
   Where K f n is a process dependent constant, Cox is the gate capacitance
per unit area and W and L are the transistor’s width and length respectively.
   Now we can write [7],
                                   K fn                    2
                   SM ( f ) =                + 2kT                       (7)
                                Cox W L| f |              3gm
   While current is being sampled by copier cell, noise from both
the switch and the transconductor changes the voltage across capacitor.
When the switch is turned off, a sample of this noise is stored on the
capacitor. It can be shown that the power spectral density of noise on the
sampling capacitor due to switch transistor and copy transistor is given
respectively as
                                     (g0 /gm )2
                       SC R ( f ) =                  SR ( f )            (8)
                                    1 + ( f / f 0 )2
                                          1
                       SC M ( f ) =                  SM ( f )            (9)
                                    1 + ( f / f 0 )2
   It is to be noted that the transconductor noise alters the voltage on the
capacitor much more than the switch noise. Since go /gm       1, (go and gm
are trans-conductances of the switch and the copy transistor respectively)
switch noise can be completely neglected and total PSD is expressed as
                        SC ( f ) = SC R ( f ) + SC M ( f )              (10)
                                          1
                        SC ( f ) =                  SM ( f )            (11)
                                   1 + ( f / f 0 )2
  An expected value of mean square output noise current can be obtained
by integrating the current noise spectral density over the cell’s own
266                                           G UPTA AND S URI

bandwidth [10]
                     ∞                              ∞                     ∞

           i TOT =
             2
                             ST OT ( f )d f =           SISD ( f )d f +       SIH ( f )d f
                                                                                 D
                     0                             0                      0
                         ∞

                 =2           SISD ( f )d f                                                  (12)
                         0

   Here SiSDrepresents the current noise spectral density at the output and
is given as
                                        SISD = gm SC ( f )
                                                2
                                                                                             (13)
  If nT s < t < (n + 1)Ts is considered then only the baseband noise holds.
                                         ∞
                           2                            1           4kT
                         i T OT   =2           2
                                              gm                         df                  (14)
                                                   1 + ( f / f0 ) 2 3g
                                                                       m
                                        0
                                              4kT π
                                  = 2gm
                                      2
                                                    f0                                       (15)
                                              3gm 2
  The loop bandwidth f o = gm /(2πC) is substituted to get,
                                         2 kT
                                       i T OT = 2gm
                                                  2
                                                                        (16)
                                           3C
   With a current copier the low frequency 1/ f noise is removed and has
been neglected in evaluating the integral. The expected current noise at the
cell’s output can be written as
                                                          2kT
                                       σni = gm                                              (17)
                                                          3C
   Thus, one of the ways of reducing the output noise current is to increase
the gate to source capacitance. Another superiority of the proposed memory
cell is that the increase in the capacitance can be adjusted as per the
bandwidth requirements by varying the number of input control gates for
the floating gate transistor. Greater the number of grounded input control
gates, greater is the effective gate to source capacitance. Thus, reduction
in output noise is achieved with the proposed memory cell without any
additional MOSFET or external capacitance.


5 SIMULATION RESULTS

The proposed CMC has been simulated on PSPICE with the assistance of
the FGMOS macro model shown in appendix. The parameters used for
     S WITCHED C URRENT M EMORY C ELL U SING F LOATING G ATE MOSFET        267




FIGURE 5
Time Domain Simulation results a) FGMOS Memory Cell b) Conventional Memory Cell
c) FGMOS Cell modified.
268                                   G UPTA AND S URI




FIGURE 6
Macro Model for FGMOS.


the floating gate MOSFETS are: W = 16µm, L = 1.5µm, Cgso = 1 pF,
Cgbo = 1pF, and the coupling capacitors are each 357fF. The current source
has a value J = 100µA. For a sinusoidal input current, the current at the
output of the FGMOS memory cell of Figure 3 is shown in Figure 5(a). It
can be seen that the current I01 is a memorized version of the input current.
It can be compared with the current I01 at the output of the conventional
single MOSFET memory cell [6–10] shown in Figure 5(b) to confirm
identical operation of the two memory cells. Further, the current I02 at the
output of the modified memory cell (Figure 4) is shown in Figure 5(c),
for a sinusoidal input current, Iin . This current is memorized version of
the input current and is available during both phases φ1 and φ2 .


6 CONCLUSIONS

In this paper, a new FGMOS based implementation for switched CMC has
been presented. It was shown that the CMC would work in the same manner
as in case of a CMC. FGMOSs have been connected in such a way so that
the total gate to source capacitance of the copy transistor increases. Noise
analysis shows that the proposed CMC has better noise performance. The
proposed CMC is completely implementable in CMOS technology and the
designer has the control over the amount of increase in the capacitance.


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     Proc. IEE Part G.
      S WITCHED C URRENT M EMORY C ELL U SING F LOATING G ATE MOSFET                   269

 [3] Helfenstein, M., and Moschytz, G. S. (1998). “Improved two-step clock-feedthrough
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APPENDIX

The macro model of the FGMOS used in the simulations is shown below.
Large resistances are included in parallel with the capacitances to avoid
DC convergence problems in simulations.
  The expressions pertaining to the model are
 1)
          G 0 (V0 − V f g ) + G 1 (V1 − V f g ) + · · · + G n (Vn − V f g ) = 0       (1.1)
                                               n
      where G i = 1/Ri and G T OT =                 Gi
                                              i=1
 2) Given G i = kCi then
                                        (C0 V0 + C1 V1 + · · · + Cn Vn
                                Vfg =                                                 (1.2)
                                                   C T OT
                      Ri = 1/kCi
      where k is a constant chosen to provide a large value of Ri of the
      order of 1000G. Thus, their effect can be neglected.

								
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