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							EDACAS UDSM SOC Hierarchical Design Flow
EDACAS OFFICE

This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Contents
Introduction Highlights Details of reference flow

This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Introduction
Address multimillion gate design with high timing complexity Integrated solution from RTL to GDSII Unified data transfer methodology Tools and Tasks:
Synopsys Tools Design Compiler Physical Compiler Jupiter XT/Floorplan Compiler Module Compiler Prime Time Astro STAR RC XT Hercules Version 2002.05 2003.03 2002.12-1 2002.05 2002.03-SP1 2003.03 2003.03 2003.03 Tasks Synthesis Placement and Optimization Floorplan, Power Network Analysis Datapath compiler STA, SI Analysis Detail Route, Optimization Extraction LVS, DRC

This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Highlights
Design Planning
RTL Performance Prototyping

Power Network Analysis (PNA) and design

Design Implementation
Block and Top-level detail route in Astro

Post Route optimization in Astro PC-Astro interface using pdef2scheme and scheme2pdef CTS and CTO Extraction in STAR RCXT

Design Refinement
DRC and LVS using Hercules Chip Finishing in Hercules ,Primetime and Astro

This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Details of Reference Flow
RTL,chip RTL,chip constraints constraints

Flow Macro Graph Design implementation
Block Optimization, CTS,Routing, Extraction & Timing closure Top-level Optimization, CTS,Routing, Extraction & Timing closure

Design planning
Initial Synthesis, Sim, DFT, Power

Chip Finishing
Chip level STA & Timing Closure

RTL Performance Prototype, Floorplanning, Design &analysis of power grid

Chip level SI analysis & fixing

Chip finishing

Timing &Physical Constraints Generation

Physical Verification

Tape Tape Out Out
This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Design Planning
Objectives
A realizable floorplan for the chip Realistic design budgets for blocks

Processes
Convert the design from RTL to Gates Floorplanning Obtain top-level routability information Obtain as realistic budget as possible for the blocks

This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Design Planning Flow
RTL,chip RTL,chip constraints constraints

A

VCS Vera

RTL verification Coverage, toggle report

JXT / FPC

Clustering & Movebounds Macro placement Initial Power Routing Floorplan Creation Timing and Congestion Analysis

DC PC PrimePower/ Power Compiler JXT / FPC

Synthesis, scan, JTAG,power

RTL Performance Prototyping

Floorplan ok

No

yes
Power Analysis

JXT / FPC

Insert Repeaters(optional) Top Level Global Route Budgeting

Die Initialization IO, JTAG Placement Power Network Analysis and design

To Design Implementation
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This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

Design Implementation
Objectives
Placement,optimization and detail routing for blocks and top-level Achieve timing closure on blocks

Processes
-Block level implementation Physical optimization, Clock tree synthesis, Detail Route Extraction, STA, Post Route Optimization -Top level implementation Physical optimization CTS and Detail route

This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Design Implementation flow
Astro

A
PC

Design Planning Star RCXT
Block Level Physical synthesis Low power, scan, CTS

Block-level Routing

RC Extraction

PT
Block-level STA SI analysis

PC

B
No

ILM ILM Generation Generation Block timing ok?

PC

Top Level Physical synthesis Low power, scan, CTS

ILM
Astro

yes
FRAM, TIM View creation

No

Chip-level timing ok?

Yes

Astro
Top-level routing

Chip Finishing
This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Chip Finishing
Objectives
-Refine the chip implementation to achieve the final timing closure and make the chip tapeout ready

Processes
-Perform re-budgeting and Post Route optimization if required for timing closure - Final chip-level static timing analysis - Final Crosstalk Analysis and Repair - Final power analysis - Perform Chip finishing, DRC LVS

This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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Chip Finishing Flow
Design Implementation Star RCXT
Top Level Extraction
FRAM,TIM

PT

PT

Capture Block Level Constraints

Top Level STA

ILM No PC
Block PR Opt Top PR Opt

timing ok?

Astro
ECO Route
FRAM,TIM

PT Astro

Yes
SI Analysis SI Repair

Star RCXT PT

RC Extraction Full Chip STA

ILM

PrimePower / Astro Rail Astro Hercules

Power signoff Chip Finishing DRC/LVS/Ant timing ok?

No

B,A

Yes

Final GDS
This document is proprietary of EDACAS. It must not be copied or used for any purpose other than for reference only.

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