Card Reader – Group T by fjzhxb


									Card Reader – Group T
T.J. McPhail Pranav Chitkara Joaquín M. Martínez

Functional Description
• Administrator sets building code and initializes the external memory, if necessary • The users with access to this building are cached into the internal memory • User ID and PIN entered and checked with internal memory • Administrator has option to add/remove users or enter building

Block Diagram
• Initialization Diagram
– Administrator ID, PIN, and BC – Initialize External DB

• Normal Diagram
– ID & PIN entered – Check in Internal DB – Administrator / Access

Normal Mode

Administrator Mode

PLA – State Diagram
• • • • • • • • • Normal Mode Check Mode Add User Remove User InitMemory Check User Write User Read User Delete User

PLA-Initialize Memory
Initializes the Card Reader
- Sets the Building Code for the Reader

- Initializes the External Memory (if necessary)
- Initializes the Internal Memory

PLA-Check User
Checks if a given user is in memory (external or internal)

PLA-Write User
Writes a user’s information to memory
ID, PIN Number, (and Building Code if writing to external memory)

PLA-Read User

Reads a user’s information in to the chip’s input registers.

PLA-Add User

Adds a user to memory (internal or external)

PLA-Delete User

Deletes a user from memory (internal or external)

PLA Layout

Chip Floor Plan

Sub-Cell – BC_Access
Checks if users from external memory have access to this building for caching into the internal memory.

Sub-Cell – End_Memory

Checks to see if chip has reached end of internal or external memory.

Sub-Cell – 2 to 4 Bit Mux

An example of one of the three different multiplexors present in our chip

Sub-Cell – Good User

In Normal Mode, determines if the user ID and PIN are in the internal memory, allowing/denying the user access to the room

Sub-Cell – Address Counter

Tells the internal/external memory which address to search for; can increment / decrement the current address by 1, 3, or 6

Sub-Cell – Internal Memory

Houses our cached users for the card reader’s building

Sub-Cell – 6 Bit Register

One of 2 different registers used throughout our chip

Pad Frame

Progress Report
• Finishing routing of our chip tonight
• System simulation begins tomorrow

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