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					26 ¡¡ 5 ˘ 2005 ˜Œ 5 ´ ¡¡ ¡¡

º ¡¡ … ¡¡ ¡¡ § ¡¡ –¤ C H IN ESE J OU RNAL O F SEMICONDUC TORS

Vol. 26 ¡¡ No . 5 ¡¡ ¡¡ May ,2005

( 1 Dep art ment of Elect ronic En gi neeri n g , Tsi n g hua Uni versit y , B ei j i ng ¡¡ 100084 , Chi na) ( 2 I nstit ute of M icroelect ronics , Tsi ng hua Uni versit y , B ei j i n g ¡¡ 100084 , Chi na)

1 ¡¡ Introduction

plicatio ns. The mo st co mmo nly used CMOS mixer

plicatio ns . Recently ,a lot of effort s have been spent

f ro m a lower co nver sio n gain for a given power . In device ,RF and L O signal s are applied to t he gate Ref . [ 4 ] ,MOS t ransistor is used as a fo ur2terminal
Research of China ( No . G2000036508) t ronic systems and SOC.

o n t he develop ment of low2voltage CMOS RF mix2 er s. In Ref s. [ 2 ,3 ] ,t he p resented mixer avoids t he stacking of t ransistors ; t radeoff is t hat it suffer s and t he back gate while t he mixing p roduct is ex2 t racted f ro m t he drain ; t his kind of mixer can be working o n a low supply voltage ,but it is difficult to p redict t he mixer performance due to t he lack of

t ure ,which limit s it s use in low supply voltage ap 2

get in mo st digital and analog integrated circuit ap 2 topology is Gilbert mixer [ 1 ] . It has stacked st ruc2

3 Project supported by National Nat ural Science Foundation of China ( No s. 60475018 ,60372021) and State Key Develop ment Program for Basic
¡¡ Liu L u ¡¡female ,PhD candidate. Her work focuses on t he analog circuit design and RF f ront2end circuit design. ¡¡ Received 11 October 2004 ,revised manuscript received 6 December 2004

¡¡ Wang Zhihua ¡¡ male ,p rofessor . His research areas include analog/ mixed2signal/ RF CMOS integrated circuit technology ,ASIC design for com2 munication systems ,algorit hm exploration and ASIC design of digital audio/ video signal p rocessing systems ,design of integrated elec2

and 11 45 GHz RF inp ut ,simulation result s show t hat t he co nversion gain is 15dB ,IIP3 is - 41 5dBm ,N F is 17dB ,t he ty analyses are also p resented. Key words : downconversion mixer ; CMOS p rocess ; noise and linearity analysis EEACC : 1250 CLC number : TN432 ¡¡ ¡¡ ¡¡ Document code : A ¡¡ ¡¡ ¡¡ Article ID : 025324177 (2005) 0520877204

maximum t ransient power dissipatio n is 91 3mW ,and DC power dissipatio n is 91 2mW. The mixer¡fl noise and lineari2 s

Abstract : A new architect ure of CMOS low voltage downconversion mixer is p resented. Wit h 11 452 GHz LO inp ut

In recent year s ,low voltage has beco me a tar2

A Ne w Low Voltage RF CMOS Mixer Design 3
Liu L u1 and Wang Zhihua2
space.

adequate model for t he t ransistor in such working mode. In Ref . [ 5 ] ,L C tanks are used in t he mixer to achieve low voltage operatio n , but in CMOS technology , Q2value of t he spiral inductor is rela2 In t his paper , a high gain downco nver sio n CMOS mixer wit h low supply voltage is p resented ; t he topology of t he mixer has never been reported Figure 1 show s t he basic operating p rinciple of t he mixer . In t his mixer core , t ransisto r M1 is working in t he t riode regio n , t ransistor M2 is working in t he sat uratio n regio n ,t he current flow t hro ugh M1 and M2 is equal ,so t hat
ν 2005 Chinese Instit ute of Elect ronics

tively low ,and t he inductor occupies a lot of chip s

p revio usly. This new mixer does not need induc2 tor s ,so it is relatively easy to fabricate.

2 ¡¡ Architecture of proposed mixer

878

26

W W 1ƒ ( V B2 + v RF - V Tn ) 2 = ƒ p Cxo n Con L 2 L 2 ( 1) can be changed into Equatio n

( VDD - V B1 - vLO - | V Tp | ) ( VDD - v)
1

( 1)

v = VDD -

1ƒ W n L 2
ƒ p

( V B2 + vRF - V Tn ) 2
2

W L

¡`

1 1 vLO VDD - | V Tp | - V B1

( 2)

( VDD - V B1 - | V Tp | )
1

t he p ropo sed mixer ,it has fo ur sectio ns : sectio n 1 is co mpo sed of M1 ,M2 ,MM1 ,and MM2 ; sectio n 2 is co mpo sed of M3 ,M4 ,MM3 ,and MM4 ; sectio n 3 is co mpo sed of M5 ,M6 ,MM5 ,and MM6 ;and sectio n 4 is co mpo sed of M7 , M8 , MM7 , and MM8. The f unctio ns of t he fo ur sectio ns are equal ; each sec2 tio n co nsist s of a mixer core (for example M1 and ample MM1 and MM2 , which are used to co nvert t he o utp ut voltage of t he mixer co re into current ) . feed t hro ugh of L O and RF signal s. plex and usually has stacked t ransistor s. In t his pa2 per ,first t he RF inp ut voltage is co nverted into current who se value is p roportio nal to RF inp ut t rolled load ,t he resistance of t his load has a term p ut voltage has t he mixing term. This kind of mix2 ing p rocedure is rat her simple ; t he mixer core o nly has t wo t ransistor s , t hus can be wo rking in low supply voltage. The supply voltage can be adjusted lower depending o n t he system requirement s. which is p roportio nal to t he L O voltage ,so t he o ut 2 voltage ,t hen t his current flow s t hro ugh L O co n2 into voltage. V out is t he o utp ut voltage of t he mix2 er. The balanced st ruct ure is cho sen to reduce t he bert mixer , is to achieve mixing t hro ugh current , t he RF inp ut voltage into current , t he L O signal and it has a t ransco nductance stage ,which co nvert s rent s co ntains t he mixing terms and are co nverted into voltage by using t ransisto rs or resistances as ting voltage into current and t hen co nverting t he load. This kind of mixer has a p rocedure of co nver2 current back into voltage ,so t he st ruct ure are co m2 switches t he current s o n and off , t he o utp ut cur2 The co mmo nly used active mixer ,such as Gil2 are used to add t he o utp ut t ransco nductance sta2 ges¡flo utp ut current and co nvert t he added current M2 ) and an o utp ut t ransco nductance stage (for ex2 Transistors ML1 and ML2 have equal sizes. They

Fig. 1 ¡¡Basic operating p rinciple of t he p ropo sed mixer

V Tn and V Tp are t he t hreshold voltage of M2 and

M1 ,ƒ n and ƒ p are t he mo bilities of charge carrier s p resent t he t ransistor¡fl widt h ,lengt h ,and gate ca2 s pacitance per unit area ,respectively ,V B1 and V B2 are DC bias voltages. The bias voltage and t he aspect ratio of t ransisto rs are selected to guarantee
vLO

of NMOS and PMOS t ransistor s , W , L ,and Cox re2 VDD - | V Tp | - V B1 Thus
1 1 vLO VDD - | V Tp | - V B1
¡

vLO 1 + VDD - | V Tp | - V B1

Then equatio n ( 2) can be app ro ximated to VDD 1ƒ W n L 2
W L
1 2

( V B2 + vRF - V Tn ) 2

v¡

ƒ p

( VDD - V B1 - | V Tp | )

1ƒ W n L 2
W L
n 1

( V B2 - V Tn ) 2 vLO

2

ƒ p

( VDD - V B1 - | V Tp | ) ( V B2 - V Tn ) vRF vLO

ƒ

W L
1

2

ƒ p

W L

( VDD - V B1 - | V Tp | ) 2

The last term in Eq. ( 4 ) is p roportio nal to v RF vLO ; Figure 2 is t he co mplete schematic diagram of

t his term can be used to achieve mixing.

ν 1

( 3)

-

-

( 4)

5˘

Liu L u et al . : ¡¡ A New Low Voltage RF CMOS Mixer Design

879

Fig. 2 ¡¡ Complete schematic diagram of t he mixer

3 ¡¡ Mixer noise and l inearity analysis
The design of t he mixer requires a co mp ro 2 The noise co nt ributio n of each t ransistor of
Id ( f ) rep resent s t he t hermal noise current in
2

tio n regio n ,t he t ransco nductance of t hem sho uld be large eno ugh to minimize t heir equivalent noise

mise ,and t he perfo rmance parameter s of t he mixer

rameter value of t he mixer , simulatio n show s t hat it has a N F of 17dB.

tio ns. In t his paper ,t he mixer is designed wit h high

intercept point ) .

t he p ropo sed mixer can be simulated and calculated by Cadence Spect reRF. This mixer is a low IF downco nversio n mixer ,and t he t hermal noise is t he p rimary noise so urce.

in t he t rio de regio n ; t heir noise can be reduced by increasing t heir lengt hs. Simulatio n result s show t hat t ransistor s M2 ,M4 ,M6 ,and M8 co nt ribute to

lo ng2channel t ransistor s and may be needed to be F E Ts.

t he drain due to t he channel resistance. If t he t ran2 sisto r operates in t he t riode regio n ,
Id ( f ) =
2

gain and low operating voltage , mo derate N F ( noise figure) ,and IIP3 (inp ut referred t hird2order 4kT
r ds ( 5)

replaced by a larger value for submicro n MOS2 Transistor s M1 ,M3 ,M5 ,and M7 are wo rking

sho uld be caref ully specified for different applica2 Where rds is t he channel resistance
[6 ]

p ut t ransco nductance stage. The linearit y of t he sisto r in t he mixer core , which is t he RF inp ut

crease power co nsump tio n. To increase t he linearit y tio of t he t wo t ransistor s of t he t ransco nductance stage is caref ully cho sen to cancel t he no nlinear terms.

.

sat uratio n regio n [ 6 ] ,
2

The coefficient ƒˆ is derived to be equal to 2/ 3 fo r

For t he lo ng2channel t ransistor wo rking in t he
ƒˆ Id ( f ) = 4 k T g m ( 6)

of t he o utp ut t ransco nductance stage ,t he aspect ra2

Linearit y is an important co nsideratio n in mix2 er design ,f ro m Eqs. ( 1¡« 4 ) ,it can be seen t hat to achieve high linearit y , t he co nditio n of Eq. ( 4) must be satisfied. The linearit y of t he mixer is also t ransco nductance stage. Transco nductance linearit y can be imp roved by increasing t he gate overdrive

4 ¡¡ Simulation results

p rocess . The simulatio n result of t his mixer is sum2 marized in Table 1. It is a low supply voltage high quency of RF signal is 11 452 GHz ; L O signal f re2 quency is 11 45 GHz ;t his is because t he mixer is de2 gain mixer , wit h moderate IIP3 and N F. The f re2

voltage at t he circuit inp ut . Af ter adjusting t he pa2 voltage , but increasing t he gate overdrive will in2 The mixer circuit is simulated using Cadence ƒ Spect reRF based o n Do ngbu 01 25 m CMOS determined by t he linearit y of mixer core and o ut 2 mixer core is determined by t he lower MOS t ran2

mo st of t he noise. A s t hey are working in sat ura2

880

26

5 ¡¡ Conclusion

t he RF inp ut voltage signal into current ,t hen t his current flows t hro ugh a t ransistor working in t he t riode regio n who se resistance is modulated by t he tively low supply voltage.

L O signal . This kind of mixer can wo rk in a rela2 This mixer achieved a simulated co nver sio n
» —´ ˜ ˘ (1 ˙ »“ · § (2 ˙ »“· § ˛¢ “ “ : Æ ‡ `¸ »

signed for L2band DAB applicatio ns.
Supply voltage DC power dissipation Conversion gain IIP3 NF Maximum t ransient power dissipation LO f requency RF f requency Technology LO amplit ude

Table 1 ¡¡ Mixer performance
2V 91 2mW 91 3mW 15dB 17dB 0dBm

sio n mixer is p resented. The mixer fir st co nvert s

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15dB ,IIP3 ˛“ - 41 5dBm ,N F ˛“ 17dB , —¶¨ ‰ł — • ˛ . — `¸ „ …·˚ : ˇ´ – ˘ » ˘ ˘ ; CMOS „⁄ EEACC : 1250 —˝… •
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11 452 GHz

11 45 GHz

- 41 5dBm

· ¸† ‹ „ƒ ”˜ ˛“ 91 3mW ,– ` „ƒ ”˜ ˛“ 91 2mW. †¢¶ ‚ˆ » ˘ ˘ ˜ º ø
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wit h a DC power co nsumptio n of 91 2mW f ro m a single 2V supply. References
t ransceivers. Chinese Journal of Semiconductors ,2003 ,24 (5) : 472 Gilbert mixers for bluetoot h t ransceiver . Chinese Journal of Semiconductors ,2004 ,25 (9) :1066 um on Circuit s and Systems ,2000 ,1 :327

[ 1 ] ¡¡ Chi Baoyong ,Shi Bingxue. CMOS mixers for 21 4 GHz WL AN [ 3 ] ¡¡ Kan T K K ,Mak K C ,Ma Dongsheng ,et al . A 22V 9002M Hz [ 6 ] ¡¡Johns D , Martin K. Analog integrated circuit design. New York :Jo hn Wiley & Sons ,Inc ,1997 :199

[ 2 ] ¡¡ Cui Fuliang ,Ma Dequn , Huang Lin ,et al . Low voltage CMOS

[ 4 ] ¡¡ Wang Hongmo . A 12V multigigahertz RF mixer core in 01 52 [ 5 ] ¡¡ Tang C C ,L u W S ,Van L D ,et al . A 21 42 GHz CMOS down2 conversion doubly balanced mixer wit h low supply voltage. IEEE International Symposium on Circuit s and Systems , 2001 ,4 :794 ¡¡ 100084) ¡¡ 100084)

gain of 15dB , IIP3 of - 41 5dBm ,and N F of 17dB ,
ƒ m CMOS. IEEE J Solid2State circuit s ,1998 ,33 (12) :2265

CMOS mixer for GSM receivers. IEEE International Symposi2

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