Operand Addressing

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					Instruction Set Design

Operand Addressing
Rob Dempster
dempster@ukzn.ac.za

School of Computer Science University of KwaZulu-Natal Pietermaritzburg Campus

Instruction Set Design – p.1/15

Abstract
This is not a paper. It is the lecture presentation slides I used to introduce instruction formats, the use of registers and addressing modes before studying the architecture of the A Intel 8088. The slides were prepared using SuSE Linux, Emacs, LTEXand Prosper. c 2007, Robert Dempster. These are free slides. There are no restrictions on using or redistributing or posting on the web a complete, unmodified copy of this material. There are some restrictions on modified copies. To be precise: Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with no invariant sections, front cover text, or back cover text. The most recent version of these slides are always available, at no charge, for downloading and for on-line use at the Web address http://sun-java.cs.ukzn.ac.za/ robd/scoslides/. There A you will find the LTEXsource code together with the slides in formats suitable for slide presentations (.sp.) and 4-up hand-outs (.ho.4up).

Instruction Set Design – p.2/15

Introduction

Generally one would tend to classify instructions in terms of their functionality. Data movement, arithmetic, logical, flow of control, input/output and miscellaneous provide a reasonably starting point. We will deal with these when we study the Intel 8088 instruction set. It is however also useful to classify instructions in terms of their addressing capabilities. Please note that: While it is customary for unlabeled assembly language instructions to start beyond column one, here we will start them in column one in order to better use the space available on the slides. During the discussion we will often want to note the extent to which the introduction of a new instruction format affects a program that uses it, use of space and time - more of my CS maxim!! To this end we will assume that the time required to load a word contained in memory into a CPU register is 2TM AT time units. (M AT represents Memory Access Time) We will also assume that W represents the space required in memory to store a computer word - of what we can load into a CPU register.

Instruction Set Design – p.3/15

Direct addressing

The address of the operand is contained within the instruction format directly, usually appended to the opcode. This is the (only) addressing mode employed by the ASC system.
LDA 1024 ;load the ACC from location 1024 LDA VALUE1 ;ditto, but from location labeled VALUE1

Please note the direct relationship between the size of the addressable memory (RAM) and the width of the address field in the instruction format. Instructions using this form of addressing require at least 2TM AT time units to execute. It is “at least” because an ADD instruction using this form of operand addressing would require extra time to complete compared with a LDA instruction. Instructions using this form of addressing require W space units to store.
Instruction Set Design – p.4/15

Immediate addressing

The value of the operand is contained within the instruction format.
LDI 3 ;The value 3 is used as the operand ;it is the value that will be loaded into the ACC register LDI THREE ;also loads 3 into ACC - see comment below

The second example assumes that the assumes that the assembler has a pseudo instruction that allows constants to be defined i.e., THREE with 3. We could extend AAL with a DCV (Define Constant Value) pseudo instruction to achieve this for work with our ASC system. This instruction requires at least 1TM AT time units to execute. The also requires W space units to store. However unlike the previous format it does not require another W space units to store the value addressed by the operand. The operand is the value that will be used!!

Instruction Set Design – p.5/15

Memory indirect addressing

This technique uses the direct address as a pointer to the memory location that contains the actual operand value. Here we effectively employ a function to map the direct address to the actual or target address. Some instruction sets allow multiple levels of indirection per operand reference.
LDA [PTR] ;Uses PTR as direct address to obtain target address LDA (PTR) ;Another notation for indirection

The second example assumes that the assumes that the assembler has a pseudo instruction that allows constants to be defined i.e., THREE with 3. We could extend our AAL with a DCV (Define Constant Value) pseudo instruction to achieve this for work with our ASC system. This addressing mode requires at least 2TM AT time units to execute. The addressing mode also requires 2W space units to store, one word for the instruction and another for the indirect operand address. This is very powerful as it allows a running program to alter the operand address used when it is executed (and appear to be intelligent). Instruction Set Design – p.6/15

Register indirect addressing

This technique uses a CPU register to hold the address of the operand value. This implies that there is a CPU register that can be used in this manner. We will assume that the INX register is such a register. It also implies that instructions exist to set this register up etc.
;assuming INX has been set up appropriately LDA [INX] ;use value in INX register as the target address. LDA (INX) ;as above, but another notation.

This addressing mode requires at least TM AT + 1TRAT time units to execute. TRAT represents the time taken to reference a CPU register. It is an order of magnitude less than than 1TM AT The addressing mode also requires W space units to store. It does of course require a CPU register (a precious resource). Because of the fast access time registers are precious computing resources and programming language translators often devote considerable resources to register optimization during the translation process to produce good code. By good do we mean it has a small footprint, is fast or both?
Exercise:

Instruction Set Design – p.7/15

Base register relative addressing

This addressing technique uses a special base register, the contents of which are added to the direct address to generate the target address. The direct address can be considered to be a displacement into a block of memory pointed to by the base register. Some systems allow the direct address to take the form of either a positive or a negative displacement. As the base register contains a complete/full pointer to memory, the displacement need not be capable of addressing the whole of the address space. This results in a reduction of the number of address bits that have to be contained within the instruction. This addressing mode also allows us to easily relocate code and data segments if all intra-segment references are relative to an address originating at zero. This form of addressing is not always available to the user as it may be reserved for the implementation of the operating system.

Instruction Set Design – p.8/15

Base register relative addressing

The more recent Intel microprocessor in the 80 series used a number of 16-bit base/segment registers for addressing purposes. The 8086 segment register values are first shifted left four places before a 16-bit displacement is added to it to produce a 20-bit target address. The following figure shows how the 8088 processor addresses the next instruction in terms of the Code Segment (CS) (base) register and the Instruction Pointer (IP) (displacement) register.
15 0

CS
15 0

IP

The 20−bit effective (target)address

Instruction Set Design – p.9/15

Base register relative addressing (cont’d.)

The 8088 CS register thus in effect addresses 16 byte paragraphs at which a 64K byte segment may start. All addressing is thus base register relative and no specific indication thereof is required. Other systems allow base relative addressing as an optional mode and thus the mode must be specifically indicated. The other 8088 segment registers are:
DS ES

The Data Segment that serves to address a segment containing data. The Extra Segment that serves to address a second segment containing data. Being able to use two (data) segment registers supports the movement (copying) of blocks of data from one memory location to another.

SS

The Stack Segment that is used for the run-time stack - mostly used with the Stack Pointer (SP) register that provides the displacement into the stack segment.

Segment registers are also useful in the sense that we could use them (with descriptors) to control the manner in which the segment is used e.g., make it read only, only addressable by the operating system etc.

Instruction Set Design – p.10/15

Indexed addressing

Indexed addressing supports the manipulation of regularly structured data such as arrays. It is an addressing mode that generally augments another addressing mode e.g., such as direct addressing. It is typically added to that address to produce the target address. For example, if the direct address is that of the zeroth element of an array (A) and then index register contains three (3) then the target address will be that of the fourth element in the array i.e. A[3]. The use of index registers is often enhanced by the inclusion of additional instructions that can be used with the index register to implement the higher level iterative/looping constructs found in programming languages.
LXI 0 ;Load the index register X with immediate value 0 LAX VECTOR ;Load the A-Reg using index register X

Instruction Set Design – p.11/15

Program counter relative addressing:

Much the same as base relative addressing as it also allows for a reduction in the number of bits required for the direct address. It also enables program relocation to take place without affecting the addressing capabilities of instructions contained within the segment. It is usually the responsibility of the translation program (assembler or compiler) to determine whether PC relative addressing is feasible under the circumstances. Generally in order to generate optimal code the translator would: first try to generate a PC relative operand address if it is supported and is feasible, otherwise generate a base-relative operand address if it is supported, finally resorting to a full address if it is the only remaining option.

Instruction Set Design – p.12/15

Some other addressing modes

Page relative addressing: This mode requires memory to consist of a number of sequential pages. The direct address can be considerable shortened if we only allow the current page or the zeroth page to be addressed. Access to a memory location beyond the current page and zeroth page is usually achieved indirectly. Stack addressing: This is really a particular case of implied addressing in which the operands are implicitly on the top of a push down stack. Heavily used by a stack oriented architecture. Also generally used to access the local variables and parameters in the stack frame of the run-time stack of the most recently evoked method of function.

Instruction Set Design – p.13/15

Instruction Types

The requirements to be satisfied by an instruction set can be stated in the following general but rather imprecise terms: They should be complete in the sense that one should be able to write a machine code program to evaluate any function that is computable using the available memory space. They should be efficient in the sense that commonly used functions can be implemented using a minimal number of instructions. The instruction types should be similar to those commonly adopted by other manufacturers to facilitate the production and programming processes. While this may seem like a rather strange requirement it has a powerful influence on what actually takes place in the industry.

Instruction Set Design – p.14/15

Instruction Set Completeness

The completeness of an instruction set can be demonstrated informally by showing that certain basic operations in each of these three groups can be programmed. It must be possible to transfer a word between the processor and any memory location. It must be possible to add two, two’s complement numbers. If the logical connectives AND and NOT are included then we can program the more complex arithmetic operations. At least one conditional branch instruction must be included. The size of instruction sets and the complexity of the individual instructions has been a major issue from the outset and the debate is continuing with the emergence of RISC processors.

Instruction Set Design – p.15/15


				
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