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Wild Circuits
Investigating the Limits of
MIN/MAX/AVG Circuits
Brendan Juba

Definitions: MIN/MAX/AVG Circuits
unsatisfied
satisfied
 We are given a circuit, C, with
feedback, operating on real numbers                         1 0
from the closed interval [0,1].
 C contains                                         0           MIN

MIN, MAX, or AVG gates with two inputs
“Inputs” to the circuit that are hard-wired to             AVG

either 0 or 1.                                                     0
 |C| denotes the number of gates of C                        MAX

Here, |C| = 3
 When the output of a gate is the                   0
appropriate function of its inputs, we
say that the gate is satisfied                  satisfied
Definitions: MIN/MAX/AVG Circuits
 Settings of the gate outputs from the interval
[0,1] are value vectors                                         1 0
 A value vector for C, v  [0,1]|C|
 The ith entry, vi, is the output of the ith gate.
 We may also consider an update function,
MIN

F: [0,1]|C|  [0,1]|C|
 We are interested in two varieties: single-gate               AVG

update functions and circuit-wide update
functions:
MAX
 A single gate update function replaces the output
of a single designated gate with the correct output
value.
• We will call iterating over the single gate update
functions “gate-by-gate update”
 The circuit-wide update function simultaneously
replaces the output of every gate with a value that
is correct with respect to the old values
Definition: Stable Circuit Problem
 A vector v is stable iff every gate is satisfied. (F(v) = v)
 We wish to find these stable vectors.
 Gate-by-gate update from 0 clearly obtains a stable vector
in the limit. This is the minimum stable solution
1 0                                   1 0
stable                            unstable

MIN                                  MIN
0                                     0

AVG                                   AVG
1/2                                   1/2

MAX                                   MAX

1/2                                  0
Stable Circuit Decision Problem
 We designate some ith gate of C in the minimum stable
solution, s, and ask, “is si ≥ 1/2?”
 We can reduce the function problem to this decision
problem. We can find 2|C| bits of any si, which may be
shown to be sufficient.
 Suppose there is a gate xk: sxk ≥ 1/2 iff the kth bit of si is a 1
 If sxk ≥ 1/2, we assume its binary decimal representation is
.100…0 with 0s in positions 2 through 2k-1
 Otherwise, it is .011…1 with 1s in positions 2 through 2k-1
 Depending on whether sxk ≥ 1/2, we add a new gate, xk+1:
AVG(xk,1/2-1/22k), if sxk = .100…0
AVG(xk,1/2+1/22k), if sxk = .011…1
 In the former case, sxk+1=(.1)(.100…0 + .011…11)
 In the latter, sxk+1=(.1)(.011…1 + .100…01)
 In the solution for the modified circuit, xk+1 clearly has the
desired properties. The largest construction is O(|C|2) gates.
Unique Solution Circuits
x       0
 Replace any wire from x to y in the
circuit with the construction on the
right using m AVG gates
AVG
 This circuit has a unique solution
(Shapley, 1953)
Suppose the original circuit-wide update              AVG

function is F, stable solutions are u and v
If ||u-v||∞= c, then it is easy to see
c = ||u-v|| = (1-1/2m)||F(u)-F(v)|| ≤ (1-1/2m)c
Clearly, c = 0.                                       AVG

 These solutions turn out to be
arbitrarily close to the minimum                       y

stable solutions (for appropriate m).
Stable Circuit is in NPco-NP
(Condon, 1992)
 A nondeterministic machine M can, in
polynomial time, on input circuit C, for gate i
Build a suitably close unique solution circuit C’
Guess the solution to C’
Verify the guessed vector is a solution
Accept or reject, respectively, precisely when the value
of gate i is above 1/2 (since C’ was close to C, either i is
above 1/2 in neither, or it is above 1/2 in both)
Stable Circuit is P-hard
 If we use no AVG gates, the wires of the circuit
will only carry 0 or 1
 It is immediate that we may use MIN as AND,
MAX as OR
 For any circuit with fixed inputs, we can
construct a “complement” circuit
Switch 0 inputs with 1 inputs
Switch MIN gates with MAX gates
 We can now negate by crossing a wire between
the original and complement circuits
(In this AVG-free case, deciding the output is in P, too)
Observation and Motivation
 If we apply gate-by-gate or circuit-wide update
on arbitrary starting value vectors, we can obtain
“interesting” circuits
One such “interesting” circuit is a binary counter
We do not necessarily obtain the stable configurations
of our circuits this way -- this is not Stable Circuit
 Can we obtain such circuits under gate-by-gate
update from 0?
If so, the minimum stable solution is the configuration of
the device after an unbounded amount of time!
“Leapfrog” circuits
 We assign each wire a “threshold” wire and
interpret its value relative to that threshold
Above threshold: T
Below threshold: F
 It is already clear that we still have AND and OR
 There is also a construction for NOT (next slide)
If there are W wires which we wish to interpret relative to
the same threshold, this gadget takes Θ(W) gates
 NB: The circuits are still monotone!
As we update, a value may seem to rise or fall, as we
follow it across different wires through the circuit
The value on any particular wire only rises as the gates
of the circuit are updated
th         x0      x1         x2

AVG

MAX

MIN        MIN        MIN

AVG                 MAX        MAX

~x0    x1         x2         th   x0   x1   x2
th
Caveats
 Assumptions:
1. All values above [below] threshold are equal
2. The values th, T, and F are all different
3. We may specify the update order for the gates of the
circuit
 Take each in turn:
1. Everything starts from zero, the property is preserved
by all three gates
2. We can push th above zero by means of an AVG gate
 With feedback, we must pass the other wires to be
interpreted relative to that threshold through similar
constructions so as to maintain relative values
3. Update order doesn’t change the solution we approach
Two-bit Counter Circuit
1      AVG
1
x0                     x1     th
NOT
NOT

MIN          MIN

MAX
1                 1
AVG          AVG

0
x0   x1   th
Two-bit Counter Circuit
1      AVG
17/32

x0                     x1     th
NOT
NOT

MIN          MIN

MAX
1                 1
AVG          AVG

1/2
x0   x1   th
Two-bit Counter Circuit
1      AVG
781/
1024
x0                     x1     th
NOT
NOT

MIN          MIN

MAX
1                 1
AVG          AVG

195/
256    x0   x1   th
Two-bit Counter Circuit
1            7217/
AVG   8192
x0                     x1     th
NOT
NOT

MIN          MIN

MAX
1                 1
AVG          AVG

28867/
32768
x0   x1   th
Serving Suggestions
carry-in
 The counter generalizes to                                    xi

n bits easily                                    NOT
The n-bit counter takes Θ(n2)                  NOT
gates, due to the size of the
carry-
 We may also build a                              MAX
out
xi
input is ever above
threshold, a wire in the                        MAX     1
input

threshold forever:                (the internal wire must also pass
NP-hardness

x1               x2 x3 th, etc.
Let any boolean formula be given…
Ex: (x1~x2x3)  (~x1~x2x3)                         NOT

Since we have AND, OR, and NOT                         NOT
gates, we can easily translate any
formula into a circuit which has an         MAX               MAX
output above its threshold iff the
formula is satisfied by the                      MAX         MAX
assignment from the input wires, as
we have on the right.                                  MIN

(x1~x2x3)(~x1~x2x3)

By attaching xi to the ith bit of the counter, we try all possible
assignments, allowing us to encode answers to SAT on a wire. The
number of gates in this circuit is quadratic in the length of the formula.
Entering PSPACE
 We can still do better: using the counter, we will
decide whether quantified boolean formulas are            x1
valid
 Assume WLOG that the quantifiers alternate: odd
variables are universal, even existential
 Observe that the counter “walks” along the              x0    x0
leaves of a tree of assignments, left to right.     
 Suppose that at the bottom we evaluate the
quantifier-free part of the formula on the specified 00 01 10    11
assignment.
 Now suppose at every  level of the tree, we have one bit of memory
for the left branch
 Set it to T when the branch is T, reset it to F when leaving that subtree.
 Pass T up the tree when
 We see T at either branch at an  level
 We see T at the right branch of a  level with the left branch bit already
set to T.
 T is passed up from the top of the tree iff we have a TQBF.
Quantifier Circuit: xi xi-1 A
xi Carry-out: xi     v i0       A   • IH: the wire labeled A will carry T iff the
shorter boolean formula with alternating
NOT                         quantifiers, A, is satisfied by the current
assignment to xi-1,…,xn from the counter
MIN
• vi0 is a register that holds the evaluation of
NOT                         xi-1A when xi is F, while xi+1,…,xn remain
fixed
• When there is a carry out of xi, xi+1 has
altered, (new branch) so we reset vi0 to F
MIN
MIN             • If vi0 holds T, and when xi is T, for some xi-1 A
carries T, then the wire labeled xixi-1A
MAX
carries T. Otherwise, the wire remains F.
MIN                      • Observe that the wire xixi-1A will carry T iff
xi                       v i0
xixi-1A is satisfied by the current
xixi-1A                     assignment to xi+1,…,xn, so the IH is satisfied
End of the Line: Thwarted by
PSPACE
 In the limit, the separation between T and F
shrinks as the internal wires approach 1.
It is not immediately clear how to recover the values of
any wire from the minimum stable solution
 Recall: finding values in the limit (the minimum
stable solution) is known to be in NPco-NP
 Answers to PSPACE-hard problems (QSAT)
may be encoded on the wires as we update
Since the “space” in Leapfrog circuits is bounded by the
number of gates, it is doubtful that such circuits can
solve anything harder
 In the limit, it is impossible to distinguish the
values in Leapfrog circuits unless NP =
th          x0        check         x1             x2          This gadget behaves
AVG
identically to the regular
NOT, unless check is set
MAX                                            high, in which case, all
outputs are set high.
MIN       MIN           MIN         MIN