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Simultaneous Placement and Routing

VIEWS: 4 PAGES: 17

									On Sub-optimality and Scalability of Logic Synthesis Tools
Igor L. Markov and Jarrod A. Roy Dept. of EECS, University of Michigan at Ann Arbor

Outline
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Motivation and Previous Work Results on Common Problems Primality Testing as a Benchmark
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Theoretical Bounds Empirical Results Polynomial Fitting

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Conclusions and Further Work

Quantifyng Scalability
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Previous work has been in physical design
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L. Hagen, J.H.Huang, and A.B.Kahng, “Quantified Suboptimality of VLSI Layout Heuristics”, DAC 1995, pp. 216-221
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Test cases with optimal cost grow linearly with problem size

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C.C.Chang, J.Cong, and M.Xie, “Optimality and Scalability Study of Existing Placement Algorithms,” ASP DAC 2003, pp. 621-627
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Placement Examples with Known Optima (PEKO) - rather artificial circuits (no long wires) Show a 2x sub-optimality in placement tools

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Our interest: logic synthesis

Our Work
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Evaluate scalability of ESPRESSO, SIS, BDS Introduce primality testing as a scalable benchmark for synthesis tools
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 poly-sized circuits; we derive an upper bound No such poly-sized circuits actually known

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Show exponential sub-optimality (pessimistic)
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Multipliers not a problem – can be instantiated

Results on Common Tasks
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Parity
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ESPRESSO & SIS: circuits as big as input truth tables BDS: circuits grow linearly ESPRESSO & SIS: work on up to 7(8)-bit adders ~polynomial circuit growth BDS crashes on all inputs (but not immediately) ESPRESSO & SIS: work on up to 4(8)-bit multipliers super-polynomial circuits growth BDS crashed on all but the 2-bit multiplier

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Addition
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Multiplication
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Log-Log Plot for Adders
Poly  Straight Line

Log-Log Plot of Multipliers

Primality Testing
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AKS algorithm (Agrawal, Kayal & Saxena) “PRIMES is in P”, preprint, August 2002 http://www.cse.iitk.ac.in/news/primality.html
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1st deterministic poly-time algorithm for primality testing Runs in O*(n12) time for n-bit integers on a RAM machine Well-known result in Complexity Theory implies that combinational circuits of size O(n52) exist

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For 1-tape Turing machine: our bound is O(n26)
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The Sophie Germain conjecture, if true, reduces the circuit size bound to O(n24)
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“True for practical purposes” (verified up to astronomic n)

Results
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ESPRESSO-exact: runs out of steam at 19 bits SIS (best of full_simplify & script rugged )
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Runs out of steam at 20 bits, but otherwise results no better than those for ESPRESSO No better than SIS or ESPRESSO

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BDS: runs out of steam at 7 bits
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Super-linear trends in log-log plots suggest exponential growth in circuit size

Log-Log Plot of Espresso Results

Known Exponential

Log-Log Plot of SIS Results

Log-Log Plot of BDS Results

Fitting Polynomials to the data
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Too few data points to see if the trend fits a 24th degree polynomial We fit the Espresso and SIS data to smaller degree polynomials (up to 18th)
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13th-15th degree were most reasonable for Espresso 13th-16th degree were most reasonable for SIS

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Several characteristics of the fits suggest circuit size growth is exponential

Properties of Good Poly-Fits
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Monotonically increasing Most coefficients should be positive  Leading coefficient must be positive Increased degree should improve fit Behavior outside data region should be reasonable

Polynomial Fitting Espresso Data

Polynomial Fitting SIS Data

Conclusions and Further Work
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Primality testing appears to expose an exponential sub-optimality in synthesis tools Continued work with primality testing
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Try new tools: M31, etc. Derive better bounds on circuit size
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Use more sophisticated algorithms like Fast Fourier multiplication Factor in improvements to AKS

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Build primality testing circuits in a VHDL, synthesize, see how well they scale Scalability studies based on doubling constructions in the spirit of Hagen et. Al.

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Work beyond primality testing
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