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Gate Delay Calculation Considering the Crosstalk Capacitances Soroush Abbaspour and Massoud Pedram University of Southern California Los Angeles CA Asia and South Pacific Design Automation Conference 2004 Outline Motivation Background Effective Capacitance Calculation RC Loads Coupled Capacitive Loads Coupled RC Loads Conclusions Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Motivation The stage delay in a VLSI circuit consists of the gate propagation delay and wire propagation delay. This paper focuses on the problem of calculating the gate propagation delay. For highest accuracy, we most carefully consider the effect of the resistive shielding and the capacitive coupling. ASP-DAC 2004 Massoud Pedram Soroush Abbaspour Motivation (Cont’d) Because of the complexity of the problem, the simplest way is to ignore: coupling capacitance between interconnects, and resistive shielding of the interconnects We only consider the capacitive loading on cell/gate propagation delay. ASP-DAC 2004 Massoud Pedram Soroush Abbaspour Gate Propagation Delay for Capacitive Loads In the case of a purely capacitive load, the gate propagation delay is a function of: Tin Gate/Cell input transition time, and output load. V(v) 90% 50% 10% CL In commercial ASIC cell libraries, it is possible to characterize various output transition times as a function of the input transition time and output capacitance, i.e., a% denotes the percentage of the output transition. ta is the output delay with respect to the 50% point of the input signal. fa is the corresponding delay function. ta fa (Tin , CL ) t10% t50% t90% t(s) Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Gate Propagation Delay Algorithm: Capacitive Load Draw_Output_Waveform (, Tin, CL) 1. For a=10%, 50%, and 90% do ta=Calc_Delay (, Tin, CL, Table(Tin, CL, a)) 2. Draw the output waveform according to above data. Calc_Delay (, Tin, CL, Table(Tin,CL,a)) 1. From Table(Tin,CL,a) according to Tin and CL, find the 50% input to a% output propagation delay, add to this and call it ta 2. Return ta value, Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Resistance Shielding and Effective Capacitance Approach In VDSM technologies, we cannot neglect the effect of interconnect resistances of the load. Using the sum of all load capacitances as the capacitive load provides an overly pessimistic approximation. Sum of all capacitive load Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Resistance Shielding A more accurate approximation for an nth order load seen by the gate/cell (i.e., a load with n distributed capacitances to ground) is to use a second order RC- model. RC- load for effective capacitance algorithms For efficient and accurate gate delay calculation, we then convert the second order RC- model into an effective capacitance value and use that value as the output load of the gate. T in Gate /Cell C1 C2 R Tin Gate /Cell Ceff Ceff C1 kC2 Soroush Abbaspour where ASP-DAC 2004 0 k 1 Massoud Pedram Crosstalk Capacitance As technology scales, the effect of coupling capacitances becomes more noticeable. Given a complex load with two types of capacitive couplings (loadto-load and input-to-load couplings), one can use moment matching techniques to model the load and the parasitic elements as an RC network (see below). Notice that the gate propagation delay calculation becomes challenging, potentially requiring large multi-dimensional lookup tables. tin,a C(a,b) C(b,a) tout,a Ra C2,a C1,c tout,b C1,b Rb C2,b C2,c C1,a tin,b Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Outline Motivation Background Effective Capacitance Calculation RC Loads Coupled Capacitive Loads Coupled RC Loads Conclusions Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Prior Work C. Ratzlaff, S. Pullela, and L. Pillage, “Modeling the RC Interconnect effects in a Hierarchical Timing Analyzer,” CICC 1992. M. Sriram and S. M. Kang, “Fast Approximation of the Transient Response of Lossy Transmission Line Trees,” DAC 1993. R. Macys, S. McCormick, “A New Algorithm for Computing the “Effective Capacitance” in Deep Sub-micron Circuits,” CICC 1998,. C.V. Kashyap, C.J. Alpert, A. Devgan, “An effective capacitance based delay metric for RC interconnect” ICCAD 2000. S. Abbaspour, M. Pedram, “Calculating the effective capacitance for the RC interconnect in VDSM technologies,” ASP-DAC 2003. Soroush Abbaspour ASP-DAC 2004 Massoud Pedram A New Effective Capacitance Calculation Algorithm Consider a unit step voltage source that drives an RC circuit. The current flowing into the RC circuit in Laplace domain is calculated as: C I ( s ) V ( s )Y ( s ) sRC 1 i(t) R C t T b) Current waveform i(t) 1/R Ceff a) RC element c) Effective capacitiance By calculating the total charge induced into the capacitance up to time T and equating with the total charge induced into the corresponding effective capacitance, we can write: Ceff Soroush Abbaspour T RC ) C (1 e ASP-DAC 2004 Massoud Pedram Effective Capacitance Calculation (Cont’d) Similarly, the effective capacitance for an RC- model load can be written as: k tout R C2 Ceff C1 (1 e )C2 k is a dimensionless constant tout is the gate output transition time. As in Macys’ work, we define: a C1 C1 C2 tout R C 2 Ceff C1 C2 Based on Macy’s output-transition-time and gate-configuration independent table that relates these three parameters, we can rewrite the effective capacitance equation as: Ceff C1 C2 a 1 ek 1 a ASP-DAC 2004 Massoud Pedram Soroush Abbaspour Effective Capacitance Calculation (Cont’d) If we replace the output transition time (tout) by 50% propagation delay we can rewrite the equation as: Ceff C1 C2 a 1 e kt ' 1 a where ’ is the ratio between the 50% propagation delay and the RC2 product. kt is a fixed value which can be obtained from a lookup table (compiled from circuit simulation results), and which is constant for the calculated a and ’. Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Effective Capacitance Calculation (Cont’d) This plot shows kt values for 50% propagation delays for different a and ’ values in a 0.1m CMOS technology. 0. 8 0. 6 kt 0. 4 0. 2 0. 9 0 1 4 7 0. 1 10 13 16 a ' Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Advantage of The Proposed Equation to Macys’ Equation An analytical expression for effective capacitance Our approach results in a more stable effective capacitance estimation. tout Ceff tout t t out out Ceff Ceff tout Ceff C1 C2 Ceff t Hout tout tout t out Ceff C1 C2 H tout kt tout Ceff Ceff t t k t k out out t out t kt kt tout Ceff kt Ceff tout kt Ceff Ceff Ceff t k k t out t Hout t Ceff tout kt Ceff kt Ceff coeff Ceff kt kt 2 '(1 a )ekt ' kt Ceff a (1 ekt ' )(1 a ) Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Advantage (Cont’d) This coefficient is always less than 1. Therefore our output transition time equation is less sensitive to parameter error 0. 2 0. 15 coeff 0. 1 0. 05 0 1 0. 7 4 0. 1 10 13 16 a ' 7 Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Gate Propagation Delay Algorithm: RC Load Draw_for_RC_Load (Tin, Load Parameters) 1. For a=10, 50, and 90 do Find_Transition_Point (Tin, C1, R, C2, Table (50%-a%),Table(kt)) 2. Draw output waveform according to the results Find_Transition_Point (Tin ,C1,C2,R,Table(50%-a%), Table(kt)) 1. Guess an initial value for Ceff 2. Compute a value (Macys’ notation) from the load values 3. Obtain ta from Table(50%-a%) based on values of Ceff and Tin 4. Compute ' from ta and load elements 5. Find kt from Table(kt) according to a and ' 6. Calculate Ceff 7. Find the new value of ta for the obtained Ceff from Table(50%-a%) 8. Compare the new ta with the old ta 9. If not within acceptable tolerance, then return to step 4 until ta converges 10. Return ta Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Proof of Convergence Theorem 1: The iterative algorithm, always converges independently of the initial guess. Furthermore, its solution is unique. Proof: Because d kt ' k ' d kt ' dC2 k ' t e C2 e t C2 dCeff dC2 dCeff kt ' dC2 kt ' k ' e kt ' e t 1 dCeff for (kt ') 0 Therefore, d kt ' )C d kt ' ekt ' C 1 C1 (1 e 2 2 dCeff dCeff Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Experimental Results Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Outline Motivation Background Effective Capacitance Calculation RC Loads Coupled Capacitive Loads Coupled RC Loads Conclusions Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Problem Statement tin(a) tout(a) Ca Ia Cc Va tin(a) tin(b) tin(b) I tout(b)b Cb Vb Two CMOS drivers, a and b, are given where their corresponding input transition times are tin(a) and tin(b) a and b denote the 50% transition points of the input waveforms of driver a and b. There is a =b-a delay between their input waveforms Furthermore, the output waveform of drivers a and b are tout(a) and tout(b), respectively. The objective is to find the output waveforms of the two drivers. ASP-DAC 2004 Soroush Abbaspour Massoud Pedram Problem Statement (Cont’d) In fact, we must solve a nonlinear equation: where t Tin in(a) t in(b) S(Tin , CL , CC ,Tout ) 0 t Tout out (a) t out (b) C CL a Cb CC Cc which is a daunting task. So we must look for a different approach. Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Miller Capacitance Based Solution tin(a) tout(a) Ca Ia Cc Ca Vb tin(b) tout(b) Cb Va tin(a) tout(a) Ia Ceff(a) Ib Ceff(b) tin(a) tin(b) tin(b) I tout(b)b Cb Equating the current sources in grounded capacitance and the coupling capacitance, we end up: Ceff ,a Ca Cc (1 Ceff ,b Cb Cc (1 DVb ) Vth,a 1 where DVb Vb Vb0 1 where DVa Va Va0 DVa ) Vth,b where Vth,a identifies the transition point of interest, say Vth,a=0.5Vdd and DVb is the output voltage transition of driver b from when the output waveform of driver a transits from 0 to its transition point. Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Gate Propagation Delay Algorithm: Coupled Capacitive Load Find_Waveforms_Capacitive_Cross_Coupled((a),(b),tin(a), tin(b), Ca, Cb, Cc) 1. Guess an initial value for output capacitive load as CL(a) and CL(b) 2. tout,a=Draw_Output_Waveform((a),tin(a),CL(a)) 3. tout,b=Draw_Output_Waveform((b),tin(b),CL(b)) 4. Repeat until the output waveform converges For (Vth,a,Vth,b)={(50%,50%),(50%,90%), (90%,50%), (50%,10%), (10%,50%)} do Find_Output(tout,a,tout,b,Vth,a,Vth,b,CL(a), CL(b),Cc) Find_Output(tout,a,tout,b,Vth,a, Vth,b, CL(a), CL(b), Cc) 1. CL ( a ) CL( a ) Cc (1 DVb ) Vth, a and CL(b) CL(b) Cc (1 DVa ) Vth,b 2. Update tout,a and tout,b 3. If tout,a and tout,b tolerance are within acceptable range, then return tout,a and tout,b 4. Find_Output (tout,a,tout,b,Vth,a,Vth,b,CL(a),CL(b),Cc) Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Proof of Convergence Theorem 2: The “Find_Waveforms_Capacitive_Cross_Coupled” algorithm converges to its unique solution independently of the initial guess for the value of the effective capacitance to ground. Proof: the algorithm can be written as : Tout F (Tin , CL CEFF ) Tout F (Tin , CL G(CC ,Tout )) CEFF G(CC ,Tout ) which is equivalent to prove: F (Tin , CL G(CC ,Tout )) 1 Tout where: 1 k g1 tout ( a ) G(CC , Tout ) Cc 1 k g 2 tout (b) k C C 1 k t c g1 out ( a ) f1 a F (Tin , CL Ceff ) k f 2 Cb Cc 1 k g 2tout (b) Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Proof of Convergence (Cont’d) Therefore, it can be inferred : Tout Fa t out ( a ) F (Tin , CL G(CC ,Tout )) F b tout ( a ) Fa tout (b) Fb tout (b) Fa Fb Fa Fb k f 1k f 2Cc 2k g1k g 2 tout ( a ) tout (b) tout (b) tout ( a ) The worst case values confirms above inequality, which turns out the correctness of the theorem. Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Experimental Results Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Outline Motivation Background Effective Capacitance Calculation RC Loads Coupled Capacitive Loads Coupled RC Loads Conclusions Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Problem Statement Problem Statement: The problem statement is the same as the one in for coupled capacitive loads, except that the load is now the one that is depicted in following figure. We are interested in determining the output waveforms at the near ends. tin,a C(a,b) C(b,a) tout,n(a) Ra C2,a C1,c tout,n(b) C1,b Rb C2,b C2,c tout,f(b) tout,f(a) C1,a tin,b Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Gate Propagation Delay Algorithm: Coupled RC Loads Find_Output_Waveforms (tin,a,tin,b, Load Parameters) 1. Model each coupling capacitance as a capacitance to ground 2. (tout,n(a),tout,f(a))=Draw_for_RC_Load(tin,a, Load Parameters) 3. (tout,n(b),tout,f(b))=Draw_for_RC_Load(tin,b, Load Parameters) 4. Repeat For (Vth,a,Vth,b)={(50%,50%),(50%,90%), (90%,50%), (50%,10%), (10%,50%)} do Update_Voltage_Waveforms (Voltage Waveforms, Vth,a, Vth,b, Load Parameters) 5. Until the output waveforms converges Update_Voltage_Waveforms (Voltage Waveforms, Vth,a, Vth,b, Load Parameters) 1. Update equivalent Miller capacitance values 2. Draw_for_RC_Load (tin,a, Load Parameters) 3. Draw_for_RC_Load (tin,b, Load Parameters) 4. If voltage waveforms are within acceptable tolerance, then return values 5. Update_Voltage_Waveforms (Voltage Waveforms, Vth,a, Vth,b, Load Parameters) Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Experimental Results Soroush Abbaspour ASP-DAC 2004 Massoud Pedram Conclusion Gate delays can vary widely as a function of input slews, driver sizes, input transition time skews, and output loads. We presented three efficient iterative algorithms with provable convergence property for calculating the effective capacitance. The error for calculating the gate propagation delay is quite small 1-6% depending on the complexity of the load and coupling configuration. Soroush Abbaspour ASP-DAC 2004 Massoud Pedram

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gate delay, delay calculation, timing analysis, delay variation, Massoud Pedram, interconnect delay, output signal, statistical timing, critical paths, Xu Xu

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