IJAIEM-2014-05-31-134.pdf by editorijettcs


More Info
									 International Journal of Application or Innovation in Engineering & Management (IJAIEM)
                     Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 5, May 2014                                                                                ISSN 2319 - 4847

     Efficient Implementation of Address Generator for
           WiMAX Deinterleaver on Xilinx FPGA
                                             Mr. Murali Krishna1, Dr. Ramesh2
                              M.Tech [VLSI], CMR Institute of Technology, Bangalore, Karnataka, India
                     Associate Professor, Dept. of ECE, CMR Institute of Technology, Bangalore , Karnataka, India

Wireless technology is emerged as the Path Breaking research areas in the modern communication domain. The key
difficulties used in the modulation schemes for WiMAX deinterleaver design, as mentioned by IEEE 802.16 standard,
needs ample hardware if all the modulation schemes and code rates have to be designed on FPGA. Floor function is
the one which makes the design extremely hardware impotence. This paper is an attempt towards removing the
hardware impotence in the implementation of the permutations by making use of simple mathematical algorithms.
Interconnection delay is reduced by making use of FPGA embedded multiplier. 16-QAM and 64-QAM are the
modulation schemes used in this paper.

Keywords: Deinterleaver, Wireless Technology, WiMAX, FPGA.

Broadband Wireless Access (BWA) is continuously becoming a more challenging competitor to the conventional wired
last mile access technologies. IEEE has developed standards for mobile BWA (IEEE 802.16e) popularly referred to as
mobile WiMAX. The channel interleaver employed in the WiMAX transceiver plays a crucial part in minimizing the effect
of burst error. Memory utilization and frequent memory accesses time are a crucial part of interleaver design.
In this paper, a path breaking, less-complexity, high-speed, and efficient resource address generator for the channel
deinterleaver used in the WiMAX transreceiver eliminating the requirement of floor function is proposed. Very few works
related to hardware implementation of the project is used the interleaver/deinterleaver used in a WiMAX system is
available in the literature. The work demonstrates the grouping of incoming data streams into the block to reduce the
frequency of memory access in a deinterleaver using a conventional lookup table (LUT)- based CMOS address generator for
WiMAX. A low cost and re-configurable architecture for address computation is always profitable. IEEE 802.16e called
WiMAX is being used in the communication industry with many variants in channel coding, like different block sizes and
different modulation schemes (e.g. BPSK, QPSK, 16 QAM and 64-QAM).
Basically, the interleaving technique is to reorder the encoded bits such that the adjacent bits can now become nonadjacent
which can help handling the burst error occurring in those channels with memory which makes the error correction very
difficult if burst error is present. Although the basic concept of interleaving is straight-forward, the way of data reorder can
be quite complex. In addition, to reorder a sequence of data requires a large memory buffer and frequent memory access
such that the deinterleaver may become a crucial part of the overall decoder circuit in both area and power. Therefore, how
to design an efficient deinterleaving circuit is very important .

The blocks of a WiMAX transreceiver are shown in fig.1. The output of source is randomized before being encoded by two
Forward Error Correction (FEC) coding techniques, namely, Reed–Solomon (RS) and Convolutional Coding (CC). The
channel interleaver permutes the encoded bit stream to reduce the effect of burst error. When Convolutional Turbo Code
(CTC) is used for FEC, being used as optional in WiMAX, hence the channel interleaver is not required; CTC itself
includes an interleaver within it . Modulation and construction of the orthogonal multiplexing symbols are performed by the
subsequent block, namely, mapper. In the receiver end, the blocks are organized in the reverse order to obtain the restoration
of the original bit sequence at the output .

Volume 3, Issue 5, May 2014                                                                                         Page 451
 International Journal of Application or Innovation in Engineering & Management (IJAIEM)
                     Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 5, May 2014                                                                          ISSN 2319 - 4847

                                    Figure 2.1: Block Diagram of WiMAX Transceiver

The randomizer eliminates a long sequence of zeros and ones so that synchronization is not lost. It works on bit by bit
fashion. Encoding is used for forward error correction where additional redundancy bits are added to the output of the
randomizer. Interleaver is used for protection against burst errors which can make a sequence of consecutive bits erroneous,
thus making it difficult for the error correcting codes to correct this long sequence of consecutive errors in the sequence
bits. WiMAX uses Reed-Solomon Codes and its error correcting capacity is 8 bits. If there are more than 8 consecutive bits
in error than RS code will not be able to correct them. It is the role of the interleaver to break this sequence of consecutive
erroneous bits and make it possible to correct errors by RS codes below 8 bits. The mapper maps the incoming bits onto a
constellation. The governing equation for WiMAX interleaver/deinterleaver is a two step permutation and is defined by
IEEE 802.16 standard is given by,


                                                                       %s   (2)

The deinterleaver is one which performs the inverse operation of interleaver. It is also defined by two permutation


Equations (3) and (4) define a two level permutation and j is the index of the received bit within a block of bits. The
first equation is for mapping the adjacent coded bits onto non adjacent subcarriers of the OFDM modulation scheme and
second equation and the second permutation maps them alternately onto less or more significant bits of the constellation
thus avoiding long runs of less reliable bits. The letter ‘d’ represents the number of rows of the block deinterleaver and
may be chosen as 12 or 16.

In previous papers not much has been done regarding the hardware efficiency and resource utilization. Out of all the
references Asghar and Liu [1] and Bijoy and sanyal [2], reference paper [1] has mathematical limitations. Whereas paper
[2] incorporate random code rates with hardware efficient. In upcoming section we have results and discussion with final
conclusion on this paper.

Eliminating the floor function and modulo function with a simple mathematical algorithm. In this paper modulations
schemes like 16-QAM and 64-QAM are used with different code rates are generated by using the permutation formulae.
Here the value of ‘d’ has been chosen as 16 and other possible value is 12. In Xilinx we cannot divide a number other
then the power of two. In Figure 4.1 and 4.2 proposed two algorithms which will sidestep the floor function and
permutation formulae which are defined in the IEEE 802.16 standard. With the modified circuit with a algorithm which
is more optimal and hardware efficient. The designing of this paper is done using two modulation techniques 16-QAM
and 64-QAM address generators and the final module deals with the combination of these two modulation techniques
using resource sharing and FPGA embedded multiplier. The validity of (5) and (6) is to represent the correlation between
addresses which is formally done using algebraic analysis.

Volume 3, Issue 5, May 2014                                                                                     Page 452
 International Journal of Application or Innovation in Engineering & Management (IJAIEM)
                     Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 5, May 2014                                                      ISSN 2319 - 4847

              TABLE I :                                                  TABLE II :
       16-QAM Addresses (First 5 rows)                           64-QAM Addresses (First 5 rows)

Modulation    Deinterleaver addresses from first 5
/             rows
                                                      Modulation    Deinterleaver addresses from
                                                      /             first 5 rows
              0       16     32          48    64
bits                                                                0     16    32     48     64
              17      1      49          33    81     64-QAM/
                                                      596 bits      17    33    1      65     81
              2       18     34          50    66
                                                                    34    2     18     82     50
              19      3      51          35    83
                                                                    3     19    35     51     67
              4       20     36          52    68                   20    36           68     84

 Kn,16qam = d * j+i for j%2=0 and

             d * (i+1)+j for j%2=1 and
                              i%2= 0           (5)
             d * (i-1)+j for j%2=1 and
                             i%2= 1

 kn,64qam = d*i+j for j%3=0 and

           d * (i-2)+j for j%3=1 and
                            i%3= 2              (6)
         d * (i+1)+j for j%3=1 and
                          i%3≠ 2
           d * (i+2)+j for j%3=2 and
                           i%3= 0

             d * (i-1)+j for j%3=2 and
                            i%3≠ 0

        Figure 4.1: Block diagram of16-QAM            Figure 4.2: Block Diagram of 64-QAM

Volume 3, Issue 5, May 2014                                                                 Page 453
 International Journal of Application or Innovation in Engineering & Management (IJAIEM)
                     Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 5, May 2014                                                                ISSN 2319 - 4847

               Figure 4.3: Complete block diagram with 16-QAM and 64-QAM modulation Techniques

The Simulation results of the proposed hardware of the address generator is implemented using Verilog Hardware
Development Language on Xilinx ISE. Simulation results are obtained for 16-QAM and 64-QAM modulation types
and for different code rates using ModelSim are shown below in figure 5.1 and 5.2 respectively.

                                Figure.5.1: Simulation results for 16- QAM Address

                                Figure.5.2: Simulation results for 64- QAM Address

Volume 3, Issue 5, May 2014                                                                          Page 454
 International Journal of Application or Innovation in Engineering & Management (IJAIEM)
                     Web Site: www.ijaiem.org Email: editor@ijaiem.org
Volume 3, Issue 5, May 2014                                                                      ISSN 2319 - 4847

       FPGA parameters   Performance of     Performance of
                         proposed technique LUT based      Remarks
       slices             1%                17.66%         Significant reduction
       Flip flops            0%                     0.78%                    Significant reduction
       4 input LUTs          1%                     17.15%                   Significant reduction
       Operating             146.176MHz             62.51MHz                 Significant Improvement

There is a significant reduction in the FPGA Parameters like slices, flip flop and 4 input LUT’s. Even there is a
significant improvement in the operating frequency of this design when compared with LUT based technique is shown in
table 3.

This paper proposes a novel algorithm which replaces the use of floor function in WiMAX deinterleaver supporting 16-
QAM and 64-QAM modulation techniques and all possible code rates as per IEEE 802.16e. The proposed algorithm is
converted into an optimized digital hardware circuit. The hardware is implemented on the Xilinx FPGA using Verilog
which gives more satisfying results compared with LUT based technique.

[1] R. Asghar and D. Liu, “2D realization of WiMAX channel interleaver for efficient hardware implementation,” in
     Proc. World Acad. Sci. Engg. Technol., Hong Kong, 2009, vol. 51, pp. 25–29.
[2] B. K. Upadhyaya, I. S. Misra, and S. K. Sanyal, “Novel design of address generator for WiMAX multimode interleaver
     using FPGA based finite state machine,” in Proc. 13th Int. Conf. Comput. Inf. Technol., Dhaka, Bangladesh, 2010, pp.
[3] B. Li, Y. Qin, C. P. Low, and C. L. Gwee, “A survey on mobile WiMAX,” IEEE Commun. Mag., vol. 45, no. 12, pp.
     70–75, Dec. 2007.
[4] Y. N. Chang and Y. C. Ding, “A low-cost dual mode de-interleaver design,” in Proc Int. Conf. Consum. Electron.,
     2007, pp. 1–2.
[5] IEEE Standard for Local and Metropolitan Area Networks—Part 16: AirInterface for Fixed Broadband Wireless
     Access Systems—Amendment 2, IEEE Std. 802.16e-2005, 2005.
[6] IEEE Standard for Local and Metropolitan Area Networks—Part 16: Air Interface for Fixed Broadband Wireless
     Access Systems—Amendment 2, IEEE Std. 802.16e-2005, 2005.
[7] M. N. Khan and S. Ghauri, “The WiMAX 802.16e physical layer model,” in Proc. IET Int. Conf. Wireless, Mobile
     Multimedia Netw., Mumbai, India, 2008, pp. 117–120.
[8] J. G. Andrews, A. Ghosh, and R. Muhamed, Fundamentals of WiMAX: Understanding Broadband Wireless
     Networking. Upper Saddle River, NJ, USA: Prentice-Hall, 2007, ch. 8.
[9] Local and Metropolitan Networks—Part 16: Air Interface for Fixed Broadband Wireless Access Systems, IEEE Std.
     802.16-2004, 2004.
[10] Xilinx Spartan-3 FPGA Family: Complete Data Sheet, Xilinx, Inc., San Jose, CA, USA, 2012.
[11] B. K. Upadhyaya and S. K. Sanyal, “An improved LUT based reconfigurable multimode interleaver for WLAN
     application,” Int. J. Recent Trends Eng. Tech., ACEEE, vol. 6, no. 2, pp. 183–188, 2011.
[12] I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” in Proc. Int. Symp. Field Programm. Gate
     Arrays, Monterey, CA, USA, 2006, pp. 21–30.

Volume 3, Issue 5, May 2014                                                                                Page 455

To top