Docstoc

Advanced VLSI Design - Washington State University_2_

Document Sample
Advanced VLSI Design - Washington State University_2_ Powered By Docstoc
					     EE 587
SoC Design & Test

Partha Pande
School of EECS
Washington State University
pande@eecs.wsu.edu




                              1
Midterm Review




                 2
                      Wire Characteristics


•   Wire modeling in details
•   Wire delay and buffer insertion
•   Uniform and non uniform buffer insertion
•   How scaling changes characteristics of a chip




                                                    3
      Interconnect Capacitance Profiles

•   Total capacitance can be
    decomposed into three                                    V erti cal
                                                             spaci ng
                                                             between
    components:                                          H   conductors

     – Area capacitance
     – Lateral capacitance                                   T
                                                    S
                                                                   H ei gh t above
     – Fringe capacitance      Horizontal
                                spacing
                                                                   Substrate

                                between                  W
                               conductors                          H




                   Ctotal = Carea + Clateral + Cfringe

                                                                    4
                     Wire Dimensions

•   T=wire thickness, H=vertical wire separation, S=horizontal wire
    separation, W=wire width, L=wire length




•   T and H are fixed parameters based on the fabrication process
•   W, S and L are under the designer’s control
                                                                      5
          Computation of Area Capacitances


Metal 2

                                H        Ca
                                     W
Metal 1

                                       Ca


•   Area capacitance per unit length can be simply calculated using:

                   Ca= eox W = 0.035fF/um (W/H)
                         H

                                                                   6
      Computation of Lateral Capacitances


Metal 2

          Closely spaced wires               S

Metal 1                                 T
                                 CL         CL


•   Lateral capacitance per unit length for closely spaced wires can
    be calculated using:
                            CL= eox T = 0.035fF/um (T/S)
                                  s
•   For widely spaced wires, CL drops off as 1/S
                                                                       7
      Computation of Fringe Capacitances


Metal 2

          Widely separated wires        H   Ca

Metal 1                            Cf   T        Cf

                                            Ca



    For widely spaced conductors




                                                      8
                      Wire Inductance



•   Wide wires in clock distribution & upper level metal layers
•   These wires have low resistance
•   Exhibit significant inductive effects
•   New materials with low-resistance interconnect




                                                                  9
                         Inductance
•   Complete interconnect model should include inductance
                                +   V   -
                                                     V=Ldi
                     R      i       L          C        dt
•   With increasing frequency and a decrease in resistance due to wide
    wires and the use of copper, inductance will begin to influence
    clocks/busses:
                               Z = R + jwL

•   Inductance, by definition, is for a loop not a wire
     – inductance of a wire in an IC requires knowledge of return
       path(s)
     – inductance extraction for a whole chip is virtually
       impossible...
                                                                    10
Effect of inductance on Signal Delay




                                       11
            Repeater Insertion revisited




•Lower repeater size and less number of repeaters
•The amount of inductance effects present in an RLC line depends on the ratio
between the RC and the LC time constants of the line
•As Inductance effect increases the LC time constant dominates the RC time
constant and the delay of the line changes from a quadratic to a linear
dependence on the line length.
•Optimum number of repeaters for the minimum propagation delay decreases

                                                                      12
                       Signal Integrity

•   Avoiding worst case switching
•   CAC codes and their characteristics
•   How to design CAC codes
•   Avoid the patterns at the boundary
•   Joint CAC and Error Correction




                                          13
                       Power & Clock

•   IR drop
•   Electromigration
•   Ldi/dt
•   Clock Cycle requirements
•   Shielding vs. Spacing
•   Power Dissipation in clocks
•   Clock distribution network




                                       14
                             Testing

•   Controllability and Observability measures
•   Advantages and disadvantages of SCAN
•   Scan Flip-Flop
•   Given a flip-flop circuit, how can you make it scannable
•   JTAG
•   Different modes of JTAG
•   Role of update and capture signals
•   Role of TAM and Wrapper in SoC testing
•   Basic concepts of P1500
•   BIST
•   Implementation of LFSR and MISR
•   BILBO
•   IDDQ test

                                                               15

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:0
posted:4/27/2014
language:English
pages:15