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MIPS Overview _with comparisons to x86_ - Texas State University.ppt

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					      MIPS Overview
(with comparisons to x86)


            CS 3339
           Lecture 3.1
          Apan Qasem
      Texas State University


           Spring 2013
              Announcements

• Quiz 0 and 1 graded

• Rand ID

• HW 1 out
                                History
•   First specification in the early 80s
     • lead by John Hennessy
     • Developed by MIPS Technologies
•   One of the first examples of RISC
    architecture
     • Load/store architecture
     • Successful pipeline implementation
     • Spawned other RISC ISAs
        • SPARC
        • Alpha
•   In the 80s and 90s SGI’s servers
    implemented MIPS ISA
•   Today, MIPS mostly used in embedded
    processors
     • Routers
     • PS2
MIPS Processor
Processor With Other Components
Multicore Processors
Parallel Multicore Processor Architecture
                           Resources

• Green insert in Text front cover
   • Overview of ISA
• Appendix B
   • Comprehensive syntax and semantics
• Virtual MIPS machine
   • hecate.cs.txstate.edu


     Write a simulator for a MIPS-like
               architecture

 Add a feature of your choice and evaluate
                                             demo
                       Review

What features of MIPS should we be interested in?
  •   Types of instructions
  •   Addressing modes
  •   Registers
  •   Instruction length
  •   Instruction encoding
  •   Number of operands
  •   Supported Data Types
                       A Bus-based Datapath for MIPS
          Opcode                                      zero?                                          busy
         ldIR                OpSel      ldA       ldB                          32(PC)          ldMA
                                                                               31(Link)
                                                                               rd
                               2                                               rt
                                                                               rs

                                                                                    RegSel    MA
                              rd                                                3
                IR            rt        A         B                addr                       addr
                              rs
                                                                   32 GPRs
ExtSel                                                              + PC ...                  Memory
                Imm           ALU                                                                           MemWrt
                                                                                     RegWrt
    2            Ext         control        ALU                    32-bit Reg        enReg
enImm                           enALU                                data                       data        enMem


                                                  Bus         32
     Microinstruction: register to register transfer (17 control signals)
         MA¬ PC means RegSel = PC; enReg=yes;     ldMA= yes
           B   ¬ Reg[rt] means       RegSel = rt; enReg=yes; ldB = yes
 Slide courtesy : Asanovic
Microprogramming

       add $1, $2, $3



ALU:      A ¬ Reg[rs]
          B ¬ Reg[rt]
          Reg[rd] ¬ func(A,B)
          do instruction fetch

                                 Microcode is another layer of
                             abstraction used to implement higher
          register          level machine code in actual hardware
            File



           adder
         Arithmetic Instruction Variants
• Four types of integer arithmetic instructions
   •   Signed                       add
   •   Immediate                    addi
   •   Unsigned                     addu ￿
   •   Unsigned Immediate           addiu


• Two types of floating-point instructions
   • Single precision       add.s
   • Double precision       add.d
       Multiply and Divide Instructions
• Signed and unsigned multiply, divide
   • mult, multu, div, divu

                                         Register
• Move result from multiply, divide        File
   • mfhi, mflo


• Move to HI or LO
   • mthi, mtlo                          HI    LO




                                          More on this
                                           next class
                         Logical Instructions
•   Usual set of logical operations available
     • OR, AND, XOR etc.


•   Also support many variants of shift
     •   shift left logical       sll     shift left by constant
     •   shift right logical      srl     shift right by constant
     •   shift right arithmetic   sra     shift right and sign extend
     •   shift left logical       sllv    shift left by variable
     •   shift right logical      srlv    shift right by variable
     •   shift right arithmetic   srav    shift right by variable and sign extend
          Data Transfer Instructions

• Loads and Stores
  • byte, word and half word variants available
  • word is most commonly used
  • sb, sw, sh


• Unsigned and signed variants of load
  • lbu, lb


• Can do immediate loads (moves really)
  • lui $3, 64
                  Branch Instructions

• Conditional and Unconditional branches supported

• Comparison and branch are fused into one instruction
           beq $1, $2, offset // jump to PC + offset, if $1 = $2


• Many different variants available
   • PC-relative and immediate
   • Comparison with zero
      • bgtz, bgez
      • Used for normalized loops, boolean flags


• Non-fused branches available too
                     Registers in MIPS

•   32 GP Integer registers ($0 - $31)
     •   32 bits for MIPS32, 64 bits for MIPS64
     •   $0 always holds 0
     •   $sp = $29 = stack pointer
     •   $gp = $28 = global pointer                x86 has 8 GP registers
                                                       + SP, PC, GP etc
     •   $ra = $31 = return address



•   32 FP registers ($f0 - $f31)
     • 16 double-precision, uses adjacent 32-bit registers

•   PC separate from register file
            MIPS Register Usage

    Name    Register                 Usage      Preserve on
            Number                                 call?
$zero          0       constant 0                  n.a.
$at            1       reserved for assembler      n.a.
$v0 - $v1     2-3      returned values             no
$a0 - $a3     4-7      arguments                   yes
$t0 - $t7    8-15      temporaries                 no
$s0 - $s7   16-23      saved values                yes
$t8 - $t9   24-25      temporaries                 no
$gp           28       global pointer              yes
$sp           29       stack pointer               yes
$fp           30       frame pointer               yes
$ra           31       return address              yes
         Instruction Length and Encoding
•   Simple fixed instruction format
                                            R: rd ¬ rs1 op rs2
•   90 instructions                           6          5    5      5       11
•   3 types of encoding                      Op         RS1   RS2   RD      func
     • R, I and J
                                            I: ld/st: rd ¬ rs1 op imm, branch
•   ISA has pseudo instructions                 6     5 5            16
    that are synthesized into                 Op RS1 RD             const
    simple sequences
     •   rotate left (rol) is implemented
                                            J: j, jal
         using a combination of shift and     6                      26
         mask
                                             Op                     const

                                                        Fixed-Format (MIPS)
•   Designed for fast hardware
    (pipelining) + optimizing
    compilers
                                            x86 supports variable length
                                              1 to 15 byte instructions
                  Number of Operands
• Arithmetic and logical instructions
                                           Most x86 implementations
  use three operands                        allow only two operands

                                         One of the sources has to serve
               add $1, $2, $3
                                                 as destination

•   Destination register separate from
    source




                                          x86 allows one operand to
                                                 be in memory
• All operands must be in registers
      Memory Addressing and Access
• Addressing modes
   • Immediate : address stored in instruction
   • Register : address stored in register
   • Relative : address = register + offset

• Addressable Unit and Alignment
   • byte, half-word, word, double word [instruction dependent]

• Endianness
   • Big endian (can operate as little endian as well)

				
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