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					   Chapter 8 Combinational
Circuit Design and Simulation
         using Gates
   ECG 100-001 Logic Design 1


           Mei Yang



                                1
     Review of Combinational Circuit
                 Design
l   Steps for designing combinational circuits
    – Set up a truth table which specifies the output(s)
      as a functions of the input variables
    – Derive simplified algebraic expressions for the
      output functions using Kmaps, or other methods
    – Design the circuit to satisfy the objective subject
      to constraints
l   In some cases, particularly if the number of
    variables is large and the number of terms is
    small, it may be desirable to go from the
    problem to algebraic equations.
                                                            2
                 Design Facts
l   The minimum SOPs (POSs) leads directly to a minimum
    two-level gate circuit.
l   Minimum two-level AND-OR, NAND-NAND, OR-NAND,
    and NOR-OR circuits can be realized from the minimum
    SOPs.
l   Minimum two-level OR-AND, NOR-NOR, AND-NOR, and
    NAND-AND circuits can be realized from the minimum
    POSs.
l   Design of multi-level, multiple-output NAND-gate (NOR-
    gate) circuits is mostly accomplished by first designing a
    circuits of AND and OR (OR and AND) gates.
l   If the AND-OR circuit has an AND gate (or OR gate)
    output connected to the same type of gate, the extra
    inverters must be added in the conversion process using
    alternative gate symbols.
                                                             3
        Gate Delays and Timing
              Diagrams
l   When the input to a logic gate is changed,
    the output will not change instantaneously.
l   Propagation delays are usually in a few
    nanoseconds.
l   Timing diagram of the inverter




                                                  4
        Gate Delays and Timing
              Diagrams
l   Timing diagram for AND-NOR circuit




                                         5
    Hazards in Combinational Logic
l   Types of hazards




l   Detection of 1-hazard




                                     6
    Hazards in Combinational Logic
l   To eliminate the hazard, add the
    corresponding term.




                                       7
    Design of Circuits with Limited
            Gate Fan-in
l   In practical logic design problems, the maximum number
    of inputs on each gate is limited.
l   Example
    – Implement f(a,b,c,d)=Σm(0,3,4,5,8,9,10,14,15) using 3-input
      NOR gates
     From the Kmap, we get
      f’=b’d(a’c’ + ac) + a’c(b + d’) + abc’
     f=[b + d’ + (a + c)(a’ + c’)][a +c’ + b’d][a + b’ +c]
                            The resulting NOR-gate circuit




                                                                    8
Two-Level Multiple-Output Circuits
l   Implement f1, f2, f3 using only 2-input NAND
    gates and inverters




l   Minimize each function separately, the result
    f1 = b’c’ + ab’ + a’b
    f2 = b’c’ + bc + a’b
    f3 = a’b’c + ab + bc’
                                                    9
Two-Level Multiple-Output Circuits
l   To reduce the input the number of inputs to
    gate, convert the functions to
    f1 = b’(a + c’) + a’b
    f2 = b(a’ + c) + b’c’ or f2 = (b’ + c)(b + c’) + a’b
    f3 = a’b’c + b(a + c’)




                                                           10

				
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posted:11/19/2013
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