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					International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
         INTERNATIONAL JOURNAL OF ELECTRONICS AND
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 5, September – October (2013), © IAEME
 COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)

ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
                                                                              IJECET
Volume 4, Issue 5, September – October, 2013, pp. 132-142
© IAEME: www.iaeme.com/ijecet.asp                                            ©IAEME
Journal Impact Factor (2013): 5.8896 (Calculated by GISI)
www.jifactor.com




             STUDY ON COMPARISON OF VARIOUS MULTIPLIERS

                  V.Priyanka Brahmaiah1, L.Dharma Teja2, Dr.Y.Padma Sai3
     1
      ECE Department, VNR Vignana Jyothi Institute of Engg. & Technology, Hyderabad, A.P)
    2
     (ECE Department, VNR Vignana Jyothi Institute of Engg. & Technology, Hyderabad, A.P)
    3
      (ECE Department, VNR Vignana Jyothi Institute of Engg. & Technology, Hyderabad, A.P)



ABSTRACT

        Low power consumption and smaller area are some of the most important criteria for the
fabrication of DSP systems and high performance systems. Optimizing the speed and area of the
multiplier is a major design issue. This paper aims at an efficient implementation of high speed
multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm.
        The low power consumption quality of booth multiplier makes it a preferred choice in
designing different circuits. The result of this paper helps to choose a better option between serial
and parallel multiplier in fabricating different systems.
        The proposed architecture is implemented in mentor graphics tools and targeted to Spartan –
III FPGA kit. Finally it has been proved that booth multiplier is more efficient than other multipliers
in terms of speed and power consumption.

Keywords: Multipliers, Radix-2, Radix-4 Booth Multiplier.

INTRODUCTION

        Sizes of devices and the number of transistors are scaling as per Moore’s Law. The sources of
power consumption on a CMOS chip can be classified as static and dynamic. The actual effort of the
circuit to switch is being the dominant component dynamic. A first order approximation of the
dynamic power consumption of CMOS circuitry is given by the formula:

                                              P = C*V2*f
  Where
 P is the power,
 C is the effective switch capacitance,
 V is the supply voltage, and
 f is the frequency of switching operation.
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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 5, September – October (2013), © IAEME

         The power dissipation arises from the charging and discharging of the circuit node
capacitances found on the output of every logic gate. Power management is the careful planning of
power budget for every subsystem of a VLSI chip. This is especially important issue for today’s
complex systems. The most important and successful use of power management is to deactivate a
portion of circuit when its computation is not required. Every low-to-high logic transition in a digital
circuit incurs a change of voltage, drawing energy from the power supply.
         A designer at the technological and architectural level can try to minimize the variables in
these equations to minimize the overall energy consumption. However, power minimization is often
a complex process of trade-offs between speed, area, and power consumption. The current work
proposes reduction of dynamic switching power, to reduce switching activity and reduction of gate
counts in 16*16 complex multiplier by using higher order compressors. Multipliers require high
amount of power and delay during the partial products formation and addition of the numbers.
         Time to market, rapid technology advancement, increase in chip size, and complexity of
digital systems are some of the factors that led to the development of hardware description languages
(VHDL and Verilog) along with the automated logic synthesis tools. The VHDL program describing
the digital system is technology independent, but the synthesis tool that generates the circuit requires
a technology file attached to it. The absence of such file causes the problem of non-possibility of
time delay extraction. In this work, the coding of different multipliers is written in VHDL. After the
coding they are targeted on the FPGA and by using Xilinx Synthesis Report, the performance of
these multipliers has been observed and power consumption is observed using power analyzer in
Xilinx 10.1 package.

SIMULATION IN TERMS OF TIME AND POWER CONSTRAINTS

       Multiplication is an important fundamental function in arithmetic operations. In fact,
multiplication based operations such as Multiply and Accumulate (MAC) and inner product are
among some of the frequently used computations-intensive arithmetic functions currently
implemented in many Digital Signal Processors (DSP) applications such as convolution, Fast Fourier
Transform (FFT), filtering and others.
       There are two ways to speed up either by reducing number of partial products and/or by
accelerating accumulation. The three types of high-speed multipliers are Array multiplier, Booth
multiplier Radix-2 and Radix-4. In this work, analysis is done on these multipliers and they are
compared in terms of number of gates, LUT’s used and power consumption. Among these
multipliers, Booth Multiplier is optimized in terms of power consumption.

MULTIPLIER

        Multipliers are key components of many high performance systems such as FIR filters,
microprocessors, digital signal processors, etc. A system’s performance is generally determined by
the performance of the multiplier because the multiplier is generally the slowest clement in the
system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area
of the multiplier is a major design issue. However, area and speed are usually conflicting constraints
so that improving speed results mostly in larger areas.
        As a result, a whole spectrum of multipliers with different area-speed constraints has been
designed with fully parallel. Multipliers at one end of the spectrum and fully serial multipliers at the
other end. In between are digit serial multipliers where single digits consisting of several bits are
operated on. These multipliers have moderate performance in both speed and area. Multiplication is
achieved by adding a list of shifted multiplicands according to the digits of the multiplier.


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ARRAY MULTIPLIER

         A Binary multiplier is an electronic hardware device used in digital electronics or a computer
or other electronic device to perform rapid multiplication of two numbers in binary representation. It
is built using binary adders.

The rules for binary multiplication can be stated as follows

1. If the multiplier digit is a 1, the multiplicand is simply copied down and represents the product.
2. If the multiplier digit is a 0 the product is also 0.

For designing a multiplier circuit we should have circuitry to provide or do the following three
things:

1. It should be capable identifying whether a bit is 0 or 1.
2. It should be capable of shifting left partial products.
3. It should be able to add all the partial products to give the products as sum of partial products.
4. It should examine the sign bits. If they are alike, the sign of the product will be a positive, if the
sign bits are opposite product will be negative. The sign bit of the product stored with above criteria
should be displayed along with the product.

        From the above discussion the observation has been done that it is not necessary to wait until
all the partial products have been formed before summing them. In fact the addition of partial
product can be carried out as soon as the partial product is formed.

Notations:

 a – multiplicand
 b – multiplier
 p – Product
Binary multiplication (eg n=4)
p=a×b

an−1 an−2_a1a0
bn−1bn−2_b1b0
p2 n−1 p2 n−2_p1 p0

xxxx a
xxxx b
---------
x x x x b0a20
xxxx      b1a21
xxxx      b2a22
xxxx       b3a23
 _______________
 xxxxxxxx p



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                                Figure 1: Array Multiplier Architecture

BOOTH MULTIPLICATION ALGORITHM

       Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement
representation. The booth algorithm is illustrated with the following example:
Example, 2 ten x (- 4) ten
0010 two * 1100 two

MAKING THE BOOTH TABLE

I. From the two numbers, pick the number with the smallest difference between a series of
consecutive numbers, and make it a multiplier.

i. i.e., 0010 -- From 0 to 0 no change, 0 to 1 one change, 1 to 0 another change, so there are two
changes on this one.
ii. 1100 -- From 1 to 1 no change, 1 to 0 one change, 0 to 0 no change, so there is only one change on
this one.
iii. Therefore, multiplication of 2 x (– 4), where 2 ten (0010 two) is the multiplicand and (– 4) ten
(1100two) is the multiplier.

II. Let X = 1100 (multiplier)

Let Y = 0010 (multiplicand)
Take the 2’s complement of Y and call it –Y
–Y = 1110

III. Load the X value in the table.

IV. Load 0 for X-1 value it should be the previous first least significant bit of X.

V. Load 0 in U and V rows which will have the product of X and Y at the end of operation.

VI .Make four rows for each cycle; this is because we are multiplying four bits numbers.



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6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 5, September – October (2013), © IAEME


                             U         V         X        X-1
                            0000      0000      1100       0      Load the
                                                                   value
                                                                  1st cycle
                                                                  2nd cycle
                                                                  3rd cycle
                                                                  4th cycle

                          Table 1: Step1 in Radix-2 Booth Multiplication


BOOTH ALGORITHM
         Booth algorithm requires examination of the multiplier bits, and shifting of the partial
product. Prior to the shifting, the multiplicand may be added to partial product, subtracted from the
partial product, or left unchanged according to the following rules:
Look at the first least significant bits of the multiplier “X”, and the previous least significant bits of
the multiplier “X - 1”.
I. 0 0 Shift only
II. 1 1 Shift only.
III. 0 1 Add Y to U, and shift
IV. 1 0 Subtract Y from U, and shift or add (-Y) to U and shift
V. Take U & V together and shift arithmetic right shift which preserves the sign bit of 2’s
complement number. Thus a positive number remains positive, and a negative number remains
negative.
VI. Shift X circular right shift because this will prevent from using two registers for the X value.
VII. Repeat the steps until four cycles are completed.

                   U          V         X         X-1
                  0000       0000      1100        0
                  0000       0000      0110        0
                  0000       0000      0011        0
                  1110       0000      0011        0       Add –Y(0000 + 1110)=1110
                  1111       0000      1001        1        Shift

                      Table 2: Step3 in Radix-2 Booth Multiplication Process


                             U         V          X       X-1
                            0000      0000       1100      0
                            0000      0000       0110      0
                            0000      0000       0011      0
                            1110      0000       0011      0
                            1111      0000       1001      1
                            1111      1000       1100      1       Shift only

  Table 3: Step4 in Radix-2 Booth Multiplication Process and Final Result in the Final Cycle


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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 5, September – October (2013), © IAEME

        After finishing four cycles, so the answer is shown, in the last rows of U and V which
is: 11111000 two

NOTE: By the fourth cycle, the two algorithms have the same values in the product register.
Group of consecutive 0’s in multiplier - no new partial product - only shift partial product right one
bit position for every 0 Group of m consecutive 1's in multiplier - less than m partial products
generated

...01…110... = ...10...000... - ...00...010...
Using SD (signed-digit) notation =...100...010...

                  Xi      Xi-1          Operation             Comments           Yi

                   0        0            Shift only         String of zeros      0


                   1        1            Shift only         String of ones       0


                   1        0         Subtract & shift      Beginning of         1
                                                            String of ones


                   0        1          Add & Shift          End of a String      1
                                                               of ones
                                Table 4: Radix-2 Booth Multiplier Logic

Recoding multiplier xn-1 xn- 2...x1 x0 in SD code.
Recoded multiplier yn-1 yn-2 ... y1 y0. xi, xi-1 of multiplier examined to generate yi.
Simple recoding is yi = xi-1 – xi.

DRAWBACKS OF RADIX-2 BOOTH MULTIPLIER

         There is a problem of isolated one’s. To overcome this drawback, instead of comparing two
bits at a time, the comparison of three bits at a time should be done.

MODIFIED BOOTH ENCODER

        Modified Booth encoding is most often used to avoid variable size partial product arrays.
Before designing a MBE, the multiplier B has to be converted into a Radix-4 number by dividing
them into three digits respectively according to Booth Encoder Table given afterwards. Prior to
convert the multiplier, a zero is appended into the Least Significant Bit (LSB) of the multiplier. In
this approach instead of eight partial products being generated using conventional multiplier only 4
partial products are generated. Table 4.2. shows the truth table for a Booth encoder. The encoder
takes inputs YN+1, YN and YN-1 from the multiplier bus and produces a 1 or a 0 for each operation:
single, double, negative(X, 2X and Neg).




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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
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                         Table 5: Truth table for Modified Booth Encoder

        This Booth multiplier technique is to increase speed by reducing the number of partial
products by half. The operand that is booth encoded is called multiplier, and the other operand is
called multiplicand.
        In most of the cases MBE scheme is used for generating PP, because of its ability to reduce
the number of PP by half [7]. The truth table shows the function of booth encoder. If a 3-bit binary
input sequence is given at the input, and perform the operation as mentioned in front of it, the partial
products will be generated.




                                      Figure 2: Booth Encoder

PARTIAL PRODUCT GENERATOR (PPG)

       Partial product generator is the combination circuit of the product generator. Product
generator is designed to produce the product by multiplying the multiplicand X by 0, 1, -1, 2 or -2.
For product generator, multiply by zero means the multiplicand is multiplied by “0”. Multiply by “1”
means the product still remains the same as the multiplicand value. Multiply by “-1” means that the
product is the two’s complement form of the number. Multiply by “-2” is to shift left one bit the
two’s complement of the multiplicand value and multiply by “2” means just shift left the
multiplicand by one place.

SIGN EXTENSION CORRECTOR

        Sign Extension Corrector is designed to enhance the ability of the booth multiplier to
multiply not only the unsigned number but as well as the signed number. As shown in Table 3.2
when bit 7 of the multiplicand X(X7) is zero(unsigned number) and Yn+1 is equal to one, then sign
E will have one value (become signed number for resulted partial product). It is the same when the
bit 7 of the multiplicand X(X7) is one (signed number) and Yn+1 is equal to zero, the sign E will
have a new value.


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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 5, September – October (2013), © IAEME




                    Table 6: Truth Table for Sign Extension when X7 is zero




                     Table 7: Truth Table for Sign Extension when X7 is one

       However when both the value of A7 and Yn+1 are equal either to zero or one, the sign E will
have a value zero(unsigned number). For the case when all three bits of the multiplier value Yn+1,
Yn and Yn-1 are equal to zero or one, the sign E will direct have a zero value independent to the X7
value[8].

SIMULATION RESULTS

The different multipliers are simulated using Xilinx 10.1 ISE simulator after writing the code.




                             Figure 3: Simulation of Array Multiplier

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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 5, September – October (2013), © IAEME




                        Figure 4: Simulation Of Radix-2 Booth Multiplier




                        Figure 5: Simulation Of Radix-4 Booth Multiplier

TIMING REPORT & DESIGN SUMMARY OF MULTIPLIERS

        The timing report of the multiplier is generated by doing synthesis of code and is targeted on
to the Field Programmable Gate logic Array (FPGA).Initially, the package pins are assigned to each
port and after that the device have to be configured in Slave/Serial mode and finally the code is
dumped into the FPGA and verify the outputs.




                             Figure 6: Design Summary of Array Multiplier

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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 5, September – October (2013), © IAEME




                     Figure 7: Design Summary of Radix-2 Booth Multiplier




                     Figure 8: Design Summary of Radix-4 Booth Multiplier

COMPARISON TABLES OF DIFFERENT MULTIPLIERS

              S.No                         Multiplier                     Time Delay
                1                       Array Multiplier                   15.529 ns
                2                   Radix-2 Booth Multiplier               14.338 ns
                3                   Radix-4 Booth Multiplier               30.078 ns
                       Table 8: Time Delay Analysis of Various Multipliers


  SPECIFICATIONS                 ARRAY         RADIX-2 BOOTH           RADIX-4 BOOTH
                              MULTIPLER           MULTIPLIER             MULTIPLIER
      No. of slices                4%                   8%                  6%
      No. of LUTs                  4%                   8%                  6%
   No. of bonded IOBs              22%                 22%                  23%
                    Table 9: Performance Comparison of Various Multipliers



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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
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CONCLUSION

        This paper gives a clear concept of different multipliers and their comparision. It can be
concluded that the parallel multipliers are better than the serial multiplier, the result of power
consumption and the total area. In case of parallel multipliers, the total area is much less than that of
serial multipliers. Hence the power consumption is also less. This speeds up the calculation and
makes the system faster. While comparing the radix 2 and the radix 4 booth multipliers it has been
found that radix 4 consumes less power than that of radix 2. This is because it uses almost half
number of iterations and adders when compared to radix 2.When all the three multipliers were
compared it has been found that array multipliers are most power consuming. This is because it uses
a large number of adders. As a result it slows down the system because the system has to perform
more number of calculations in case of array multiplier. Multipliers are one the most important
component of many systems and it is necessary to find a better solution in case of multipliers.
Preferably multipliers should always consume less power and cover less area.

REFERENCES

 [1]  “Modeling of Time Delay in VHDL-based Design of a Multiplier” Z. A bid Electrical
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 [2] “A Two’s Complement Parallel Array multiplication Algorithm” By Charles.R.Baugh and
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 [3] M. Miyamotoetal, “High -Speed and Low-Power Interconnect Technology for Sub-Quarter-
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 [4] A. Bellaouar and M. I. Elmasry, “Low-Power Digital VLSI Design”, Kluwer Academic
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 [5] “Low voltage, low power VLSI subsystems” By Kiat Seng Yeo, Kaushik Roy.
 [6] “Digital Design” By John.F.Wakerly.
 [7] “VHDL Premier and VHDL Synthesis” By V.J.Prasad.
 [8] Computer System Architecture by “Marris Mano”.
 [9] B.K.V.Prasad, P.Satishkumar, B.Stephencharles and T.Prasad, “Low Power Design of
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 [10] Kavita and Umesh Goyal, “FPGA Implementation of Vedic Multiplier”, International Journal
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