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Chapter 1 Computer System Overview


 Internals          Chapter 1
and Design
 Principles   Computer System
                          Seventh Edition
                      By William Stallings
               Operating Systems:
         Internals and Design Principles

“No artifact designed by man is so convenient for this kind of
  functional description as a digital computer. Almost the only ones
  of its properties that are detectable in its behavior are the
  organizational properties. Almost no interesting statement that
  one can make about an operating computer bears any particular
  relation to the specific nature of the hardware. A computer is an
  organization of elementary functional components in which, to a
  high approximation, only the function performed by those
  components is relevant to the behavior of the whole system.”

                              THE SCIENCES OF THE ARTIFICIAL ,

                                                     Herbert Simon
          Operating System
nExploits the hardware resources of one or more
 processors to provide a set of services to system
nManages the processor, secondary memory and
 I/O devices
                Basic Elements
                                  n The memory
                                   n Is volatile – contents are lost
                                     when powered off
                                   n Random access

n n The processor (CPU)
  I/O modules                               n The system bus
   Move data the actions of the
 n n Controlsbetween
   memory and external                         n Provides
   devices (storage,                             communication among
   n Executes data-processing &                  processors, main
     logic operations
   hardware, terminals, …)                       memory, and I/O
nInvention that brought about desktop
 and handheld computing
nThe entire CPU could be placed on a
 single chip (or possibly a few chips)
nMuch faster than older CPUs built from
 several circuit boards
nMicroprocessors today have multiprocessor
 nEach chip may contains multiple processors
 nEach core may execute multiple threads
nMultiple cores mean faster processing – single
 core chips were approaching speed limitations.
      Graphical Processing
         Units (GPUs)
nProvide efficient computation on arrays of
 data using Single-Instruction Multiple Data
 (SIMD) techniques
nOriginally designed for graphics rendering but
 today used for general numerical processing
nPhysics simulations for games
nComputations on large spreadsheets
      Digital Signal Processors

nDeal with streaming signals such as audio or
nUsed to be embedded in devices like modems
nEncoding/decoding speech and video (codecs)
nSupport for encryption and security
        System on a Chip
nTo satisfy the requirements of handheld
 devices & embedded systems, the
 microprocessor is giving way to the SoC
nComponents such as DSPs, GPUs,
 codecs and main memory, in
 addition to the CPUs and
 caches, are on the same chip
    Instruction Execution

nA program consists of a set of instructions
 stored in memory

    Two steps:

    • processor reads (fetches)
      instructions from memory
    • processor executes each
Basic Instruction Cycle
          Instruction Fetch
            and Execute

nThe processor fetches the instruction from
nProgram counter (PC) holds address of the
 instruction to be fetched next
    § PC is incremented after each fetch
   Instruction Register (IR)

Fetched instruction is     nProcessor interprets the
 loaded into Instruction    instruction and performs
 Register (IR)              required action:
                                 n Processor-memory
                                 n Processor-I/O
                                 n Data processing
                                 n Control
 Characteristics of a
Hypothetical Machine
Example of
nInterrupt the normal sequencing of the
nProvided to improve processor utilization
   n most I/O devices are slower than the processor
   n processor must pause to wait for device
   n wasteful use of the processor
Common Classes

of Interrupts
Flow of Control
Instruction Cycle With Interrupts
Transfer of Control via Interrupts
        Multiple Interrupts

 An interrupt occurs
while another interrupt        Two approaches:
  is being processed
• e.g. receiving data       • disable interrupts
  from a                      while an interrupt is
  communications line         being processed
  and printing results at   • use a priority scheme
  the same time
          Memory Hierarchy

nMajor constraints in memory
   ◆ amount
   ◆ speed
   ◆ expense

nMemory must be able to keep up with the processor
nCost of memory must be reasonable in relationship to
 the other components
  Memory Relationships

               Greater capacity
               = smaller cost per
  Faster                               Greater
access time                           capacity =
 = greater                          slower access
cost per bit                            speed
    The Memory Hierarchy
§ Going down the

 Ø decreasing cost per bit
 Ø increasing capacity
 Ø increasing access time
 Ø decreasing frequency of
   access to the memory by
   the processor
Performance of a Simple
  Two-Level Memory

         Figure 1.15 Performance of a Simple Two-Level Memory
nSpeed of fast memory (T1): 0.1
nSpeed of slow memory (T2): 1.0
nHit ratio for fast memory: .95
nAverage access time = .15
 (.95 * .1) +(.05 * (1.0 + 0.1))
       Principle of Locality

nMemory references by the processor tend to
 nSpatial locality: a reference to one memory
  location usually means nearby locations will be
  referenced too
 nTemporal locality: if a location is referenced
  once, it will probably be referenced again soon.
       Principle of Locality

nIn a hierarchical memory, data can be
 organized so that the percentage of accesses to
 each successively lower level is substantially
 less than that of the level above
 ni.e., locations in current locality should be in the
  faster levels of memory.
nCan be applied across more than two levels of
       Memory Hierarchy
• Cache Memory: fastest; volatile; contains a
  subset of main memory
   • Most processors have more than one
• Main Memory: slower; also volatile
• Disk: slowest, non-volatile, used to store
  programs and data permanently
  Cache Memory

nInvisible to the OS
nProcessor must access memory at least once
 per instruction cycle
nProcessor execution time is limited by
 memory cycle time
nExploit the principle of locality with a small,
 fast memory
 Cache Principles
nOn a memory reference, the processor first
 checks cache
nIf not found, a block of memory is read into
nLocality makes it likely that many future
 memory references will be to other bytes in the
Cache and
Cache/Main-Memory Structure
            I/O Techniques
∗ When the processor encounters an instruction relating to
I/O, it executes that instruction by issuing a command to
the appropriate I/O module

  Three techniques are possible for I/O

   Programmed         Interrupt-      Direct Memory
       I/O           Driven I/O       Access (DMA)
          Programmed I/O
nThe I/O module performs the requested action
 then sets the appropriate bits in the I/O status
nThe processor periodically checks the status of the
 I/O module until it determines the instruction is
nWith programmed I/O the performance level of the
 entire system is severely degraded
                 Interrupt-Driven I/O
issues an I/O                           The processor
command to a                             executes the
 module and                             data transfer
 then goes on                              and then
  to do some                              resumes its
  other useful                              former
     work                                 processing

                 The I/O module will                     More efficient than
                  then interrupt the                    Programmed I/O but
                 processor to request                     still requires active
                   service when it is                     intervention of the
                  ready to exchange                      processor to transfer
                     data with the                      data between memory
                       processor                         and an I/O module
        Direct Memory Access
∗ Performed by a separate module on the system bus or
incorporated into an I/O module

     When the processor wishes to read or write data it
    issues a command to the DMA module containing:
•   whether a read or write is requested
•   the address of the I/O device involved
•   the starting location in memory to read/write
•   the number of words to be read/written
     Direct Memory Access
nTransfers the entire block of data directly to
 and from memory without going through the
   n processor is involved only at the beginning and end of the
   n processor executes more slowly during a transfer when
     processor access to the bus is required

nMore efficient than interrupt-driven or
 programmed I/O
     Symmetric Multiprocessors
n A stand-alone computer system with the
 following characteristics:
 n two or more similar processors of comparable capability
 n processors share the same main memory and are
   interconnected by a bus or other internal connection scheme
 n processors share access to I/O devices
 n all processors can perform the same functions
 n the system is controlled by an integrated operating system
   that provides interaction between processors and their
   programs at the job, task, file, and data element levels
       SMP Advantages
Performance                       Scaling
• a system with multiple          • vendors can offer a range of
  processors will yield greater     products with different price
  performance if work can be        and performance
  done in parallel                  characteristics

Availability                      Incremental Growth
• the failure of a single         • an additional processor can
  processor does not halt the       be added to enhance
  machine                           performance
     SMP Organization

                                                    Cache coherence
                                                    issues are
                                                    introduced when
                                                    several processors
                                                    cache the same
                                                    memory locations

Figure 1.19 Symmetric Multiprocessor Organization
             Multicore Computer
nAlso known as a chip multiprocessor
nCombines two or more processors (cores) on a
 single piece of silicon (die)
   neach core consists of all of the components of an
    independent processor
nIn addition, multicore chips also include L2
 cache and in some cases L3 cache
                        Intel Core i7

Supports two forms of external communications to other chips:

   DDR3 Memory Controller
   • brings the memory controller for the DDR (double data rate) main memory onto the
   • with the memory controller on the chip the Front Side Bus is eliminated

          QuickPath Interconnect (QPI)
          • enables high-speed communications among connected processor chips
Core i7

          Figure 1.20 Intel Corei7 Block Diagram
nBasic Elements
  nprocessor, main memory, I/O modules, system
  nGPUs, SIMD, DSPs, SoC
  nInstruction execution
     n processor-memory, processor-I/O, data processing,
  nInterrupt/Interrupt Processing
  nMemory Hierarchy
  nCache/cache principles and designs

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