# National Automated Highway Demonstration_ Platoon System by hcj

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```									CAD Software_ Logic Aid

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Logic Aid 的主要功能

h Simplifying Boolean functions
– Equations
– Terms
– Truth table
– PLA table
– Karnaugh maps
h Provides routines to do state reduction
– specify state assignments
– To generate flip-flop input equations
– Compare with another state table for functional equivalence
h Accepts state graphs and SM charts as inputs

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Equation_ Input Fromat

h Choose Input àEquation (Ctrl +E)

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Equation_ Variable Name Assign

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Equation_ Example

h 以Output Function name 為開頭
h 符號及字母間需空格
h 結尾需加 period ”.”
h Ctrl + Y 可檢查句法是否正確

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Equation_Save the Design as *.aid

If Syntax has no Error ->
Save the Design

Than *.aid will produced

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Equation_ Simplifying Logic Equations

h Routineà Simplification (or Ctrl+ I)
h Output Format:
--Alphanumeric:字母或符號
--Binary:1,0,-
-- PLA: input 為PLA時
h Simplification Routine
--PI Chart :一個主要相關的解,速度比Petrick快,適用於較多
term的時候
--Petrick (Maximum of 5): 最小閘數的解(最強的五個解)
--Espresso II : 可選Multiple or single output,適用於PLA 或是
很多輸入變數的
h 如無特殊狀況常用,選擇Petrick– Maximum of 5 Minimal
Solutions

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Equation_ Simplifying Logic Equations

h Options: 視需要勾選
--Complemented Functions : 反向輸出的解
--Display All Prime Implicants: 顯示prime implicants
--Identify Essential Prime Implicants:顯示EPI
--Display Input and Gate Costs:顯示輸出閘數
h 複雜的邏輯需要較多時間,Ctrl+ Period(.) 可以中斷簡化
h 設定後按okà output 視窗à可選擇存檔(*.out)

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Truth Table

h Input à Truth Table (or Ctrl + T)
h Input default: x1, x2, x3…….
h Output default: z1, z2, z3……..

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PLA

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Term: Minterm or Maxterm

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Other type Minterm and Maxterm

h Given a maxterm expansion with no ”don’t cares”
– Enter , 1 6 7 8 14.
h Given a minterm expansion with “don’t cares”
– Enter 1 3 5 7,,2 4 12.
h Given a maxterm expansion with “don’t cares”
– Enter ,0 3 9 13, 1 5 7.

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Karnaugh Maps

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State table

h State Reduction
h State Assignment
h Flip-Flop Equation
h Input à State Table (or Ctrl+
B)

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State Table_ State Reduction

h Inputà Check syntax (or Ctrl+ Y)
h Routine àState Reduction à可選擇新開一個視窗

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State Table_ State Assignment

h Routine à State Assignment

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State Table_ Flip Flop Equation

h Routine à Flip Flop Equation

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State Graph

h Convert to State Table and then you can reduce the number of
State Table
h Inputà State Graph

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State Graph

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State Graph_ Label

h 在要輸入的Arc旁按下右鍵,即可輸入Label
h 輸入和輸出值要以”/”分開
h 完成後進行 Check Syntax
h Input à Convert to State Table

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