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INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME TECHNOLOGY (IJEET) ISSN 0976 – 6545(Print) ISSN 0976 – 6553(Online) IJEET Volume 4, Issue 4, July-August (2013), pp. 144-158 © IAEME: www.iaeme.com/ijeet.asp ©IAEME Journal Impact Factor (2013): 5.5028 (Calculated by GISI) www.jifactor.com ADVANCED FIVE LEVEL - FIVE PHASE CASCADED MULTILEVEL INVERTER WITH SVPWM ALGORITHM Rajasekharachari k 1, K.Shalini 2, Kumar .k 3, S.R.Divya 4 1 M.Tech (PEED) student, S.V.C.E.T, Chittoor, India 2 M.Tech (PEED) student, S.V.C.E.T, Chittoor, India 3 M.Tech (PEED) student, S.V.C.E.T, Chittoor, India 4 M.Tech (PEED) student, S.V.C.E.T, Chittoor, India ABSTRACT An Advanced five level five phase multi level inverter with space vector pulse width modulation control has been discussed here. The detailed working principles, operation, control schemes, design and the performance were presented. The dc-link capacitor voltages of various types of multi level inverter and design and the performance is presented. The performance of the diode clamped multi level inverter and flying capacitor multi level inverter are presents and the five phase, five level inverter with full bridge cascaded multi level inverter has been discussed. Multi-phase machines and drives is a topic of growing relevance in recent years, and it presents many challenging issues that still need further research. This is the case of multi-phase space vector pulse width modulation (SVPWM), which shows not only more space vectors than the standard three-phase case, but also new subspaces where the space vectors are mapped. A recent multilevel multiphase space vector PWM with switching state redundancy is particularized for multilevel converters. Finally, the new algorithm is implemented in a low-cost field-programmable gate array and it is tested with a five-level cascaded full-bridge inverter. The proposed implemented circuit of five-level five phase cascaded full bridge inverter simulation and its results of output voltages are discussed. Keywords: cascaded full bridge inverter, dc-link capacitor, multi-phase, multi level voltages, and SVPWM algorithm. I. INTRODUCTION Inverter is power electronic circuit that converts a direct current into an alternative frequency. The inverters find their application in modern ac motor and uninterrupted power supplies and static, inverters have no moving parts and are used in a wide range of applications, from small switching 144 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME power supplies in computers, to large electric utility high-voltage direct current applications that transport bulk power. Inverters are commonly used to supply AC power from DC sources such as solar panels or batteries. The electrical inverter is a high-power electronic oscillator. It is so named because early mechanical AC to DC converters was made to work in reverse, and thus was "inverted", to convert DC to AC. 1.1 Conventional Two-Level and Three-Level Voltage Source Inverter Switch-mode dc-to-ac inverters used in ac power supplies and ac motor drives where the objective is to produce a sinusoidal ac output whose magnitude and frequency can both be controlled. Practically, we use an inverter in both single-phase and three phase ac systems. A half- bridge is the simplest topology, which is used to produce a two level square-wave output waveform. A center-tapped voltage source supply is needed in such a topology. It may be possible to use a simple supply with two well-matched capacitors in series to provide the center tap. The full-bridge topology is used to synthesize a three-level square-wave output waveform. The half-bridge and full- bridge configurations of the single-phase voltage source inverter are shown in Fig. 1.1 and 1.2, respectively. Fig: 1.1 Half Bridge Configuration Fig: 1.2 Full Bridge Inverter In a single-phase half-bridge inverter, only two switches are needed. To avoid shoot-through fault, both switches are never turned on at the same time. S1 is turned on and S2 is turned off to give a load voltage, AO V in Fig. 1.1, of 2 / s V+. To complete one cycle, S1 is turned off and S2 is turned on to give a load voltage, AO V, of 2 / s V-. In full bridge configuration, turning on S1 and S4 and turning off S2 and S3 give a voltage of VS between point A and B ( AB V ) in Fig. 1.2, while turning off S1 and S4 and turning on S2 and S3 give a voltage of Vs - . Figure 1.2.2 Full-bridge configuration. To generate zero level in a full-bridge inverter, the combination can be S1 and S2 on while S3 and S4 off or vice versa. The three possible levels referring to above discussion are shown in Table 1.1 Conducting switches Load voltages S1, S4 +Vs S2, S4 -Vs S1,S2 or S3&S4 0 Table 1.1 Load Voltages with Corresponding Conducting Switches 145 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME Conducting Switches Load Voltage AB V S1, S4 s V + S2, S3 s V - S1, S2 or S3, S4 0 Note that S1 and S3 should not be closed at the same time, nor should S2 and S4. Otherwise, a short circuit would exist across the dc source. The output waveform of half bridge and full-bridge of single-phase voltage source inverter are shown in Fig. 1.3 and 1.4, respectively. Fig: 1.3 Output waveform of half-bridge configuration Fig: 1.4 Output waveform of full-bridge configuration Multilevel inverters are ideal for connecting renewable energy sources such as photovoltaic to the grid. They have been developed in such to overcome shortcomings in solid-state switching device ratings by using a series connected semiconductors devices to block the higher voltage levels involved. The desired high ac voltage is synthesized from several of smaller dc voltages levels. For this reason, additional applications of multilevel inverters include such uses as medium voltage adjustable, speed motor drives, static VAR compensation. The main advantages of this approach are summarized as follows • The semiconductors are wired in a series-type connection, which allows operation at higher voltage. • The voltage capacity of the existing devices can be increased many times without the complications of static and dynamic voltage sharing that occur in series connected devices. • The smaller voltage steps lead to the production of higher power quality waveforms with low distortion harmonics without the use of transformers • Spectral performance of multilevel waveforms is superior to that of their two level counterparts. The selection of the best multilevel topology and the best control strategy for each given application is often not clear and is subject to various engineering tradeoffs. By narrowing this study 146 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME to the DC/AC multilevel power conversion technologies that do not require power regeneration, several attractive topological, modulation and power semiconductor device choices present themselves. The most actively developed of these multilevel topologies are listed in figure 1.5. Fig: 1.5 Multilevel Converter Topologies II. INTRODUCTION TO MULTI LEVEL INVERTERS Inverters are expected to play an essential role in the field of power production, especially in the rural areas where over two billion people today have no access to electricity. As a result of the variety of inverters applications, a number of inverter topologies have been developed ranging from single-phase half-bridge to three-phase multilevel inverters. The concept of multilevel converters has been introduced since 1975. The term multilevel began with the three-level converter. Subsequently, several multilevel converter topologies have been developed. However, the elementary concept of a multilevel converter to achieve higher power is to use a series of power semiconductor switches with several lower voltage dc sources to perform the power conversion by synthesizing a staircase voltage waveform. Capacitors, batteries, and renewable energy voltage sources can be used as the multiple dc voltage sources. The commutation of the power switches aggregate these multiple dc sources in order to achieve high voltage at the output; however, the rated voltage of the power semiconductor switches depends only upon the rating of the dc voltage sources to which they are connected. A multilevel converter has several advantages over a conventional two-level converter that uses high switching frequency pulse width modulation (PWM). The attractive features of a multilevel converter can be briefly summarized as follows. Staircase waveform quality: Multilevel converters not only can generate the output voltages with very low distortion, but also can reduce the dv/dt stresses; therefore electromagnetic compatibility (EMC) problems can be reduced. Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage; therefore, the stress in the bearings of a motor connected to a multilevel motor drive can be reduced. Furthermore, CM voltage can be eliminated by using advanced modulation strategies. Input current: Multilevel converters can draw input current with low distortion. Switching frequency: Multilevel converters can operate at both fundamental switching frequency and high switching frequency PWM. It should be noted that lower switching frequency usually means lower switching loss and higher efficiency. 147 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME One particular disadvantage is the greater number of power semiconductor switches needed. Although lower voltage rated switches can be utilized in a multilevel converter, each switch requires a related gate drive circuit. This may cause the overall system to be more expensive and complex. Plenty multilevel converter topologies have been proposed during the last two decades. Contemporary research has engaged novel converter topologies and unique modulation schemes. Moreover, three different major multilevel converter structures have been reported in the literature: cascaded H-bridges converter with separate dc sources, diode clamped (neutral-clamped), and flying capacitors (capacitor clamped). Moreover, abundant modulation techniques and control paradigms have been developed for multilevel converters such as sinusoidal pulse width modulation (SPWM), selective harmonic elimination (SHE-PWM), space vector modulation (SVM), and others. In addition, many multilevel converter applications focus on industrial medium-voltage motor drives, utility interface for renewable energy systems, flexible AC transmission system (FACTS), and traction drive systems. Three different major multilevel converter structures have been applied in industrial applications: cascaded H-bridges converter with separate dc sources, diode clamped, and flying capacitors. Before continuing discussion in this topic, it should be noted that the term multilevel converter is utilized to refer to a power electronic circuit that could operate in an inverter or rectifier mode. 2.1 Diode Clamped Inverters The most commonly used multilevel topology is the diode clamped inverter, in which the diode is used as the clamping device to clamp the dc bus voltage so as to achieve steps in the output voltage. Figure shows the circuit for a diode clamped inverter for a three-level and a four-level inverter. The key difference between the two-level inverter and the three-level inverter are the diodes D1a and D2a. These two devices clamp the switch voltage to half the level of the dc-bus voltage. In general the voltage across each capacitor for an N level diode clamped inverter at steady state is vdc/(n-1) Although each active switching device is only required to block V, the clamping devices have different ratings. The diode-clamped inverter provides multiple voltage levels through connection of the phases to a series of capacitors. Due to capacitor voltage balancing issues, the diode-clamped inverter implementation has been limited to the three levels. Because of industrial developments over the past several years, the three level inverter is now used extensively in industry applications. Although most applications are medium-voltage, a three-level inverter for 480V is on the market. Fig:2.1 Topology of the diode-clamped inverter (I) two-level inverter, (II) three-level inverter, (III) four-level inverter In general for a N level diode clamped inverter, for each leg 2 (N-1) switching devices, (N-1) * (N-2) clamping diodes and (N-1) dc link capacitors are required. When N is sufficiently high, the number of diodes and the number of switching devices will increase and make the system 148 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME impracticable to implement. If the inverter runs under pulse width modulation (PWM), the diode reverse recovery of these clamping diodes becomes the major design challenge. 2.2 Flying Capacitor Multilevel Inverter Meynard and Foch introduced a flying-capacitor-based inverter in 1992. The structure of this inverter is similar to that of the diode-clamped inverter except that instead of using clamping diodes, the inverter uses capacitors in their place. The circuit topology of the flying capacitor multilevel inverter is shown in Fig2.2. This topology has a ladder structure of dc side capacitors, where the voltage on each capacitor differs from that of the next capacitor. The voltage increment between two adjacent capacitor legs gives the size of the voltage steps in the output waveform. One advantage of the flying-capacitor-based inverter is that it has redundancies for inner voltage levels; in other words, two or more valid switch combinations can synthesize an output voltage. Figure: 2.2 Three-phase six-level structure of a flying capacitor inverter Moreover, the flying-capacitor inverter has phase redundancies, whereas the diode-clamped inverter has only line-line redundancies. These redundancies allow a choice of charging/discharging specific capacitors and can be incorporated in the control system for balancing the voltages across the various levels. In addition to the (m-1) dc link capacitors, the m-level flying-capacitor multilevel inverter will require (m-1) × (m-2)/2 auxiliary capacitors per phase if the voltage rating of the capacitors is identical to that of the main switches. One application proposed in the literature for the multilevel flying capacitor is static var generation. 2.3 Cascaded H-Bridges Inverter A single-phase structure of an m-level cascaded inverter is illustrated in Figure 2.3. Each separate dc source (SDCS) is connected to a single-phase full-bridge, or H-bridge, inverter. Each inverter level can generate three different voltage outputs, +Vdc, 0, and –Vdc by connecting the dc source to the ac output by different combinations of the four switches, S1, S2, S3, and S4. To obtain 149 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME +Vdc, switches S1 and S4 are turned on, whereas –Vdc can be obtained by turning on switches S2 and S3. By turning on S1 and S2 or S3 and S4, the output voltage is 0. The ac outputs of each of the different full-bridge inverter levels are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. The number of output phase voltage levels m in a cascade inverter is defined by m = 2s+1, where s is the number of separate dc sources. The phase voltage van = va1 + va2 + va3 + va4 + va5 …… (1) For a stepped waveform such as the one depicted in Figure 2.4.1 with s steps, the Fourier Transform for this waveform follows )+ ) +…+ )] , where n=1, 3, 5, 7,…….(2) Fig: 2.3 Single-phase structure of a Fig: 2.3.1 Output phase voltage waveform Multilevel cascaded H-bridges inverter of an 11-level cascade inverter III. MULTI LEVEL MULTIPHASE SVPWM In order to solve the multilevel modulation problem various pulse-width modulation (PWM) strategies have been developed and studied in detail such as multilevel sinusoidal PWM, multilevel selective harmonic elimination and space vector modulation. Among these strategies, the space vector PWM (SVPWM) stands out because it offers significant flexibility to optimize switching waveforms and it is well suited for digital implementation. Complexity and computational cost of traditional SVPWM techniques increase with the number of levels of the converter, and most of them use trigonometric functions or precomputed tables. A two-dimensional (2D) SVPWM algorithm that calculates the switching vectors and the switching times without using angles, trigonometric func- tions or precomputed tables was proposed. A tree-dimensional (3D) SVPWM algorithm that generalizes this 2D algorithm for systems with neutral wire was presented. Due to their low computational cost both techniques are suitable for real time hardware implementation in low cost- 150 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME devices. A generalized direct PWM method in which the switching states and the pulse-width of each phase are directly determined in terms of the normalized reference voltage vector is proposed. It is proved that the modulation outputs of the direct algorithm and the previous 3D SVPWM generalized algorithm are equivalent. Recently, a new multiphase SVPWM technique with low computational complexity, that makes it suitable for real-time implementation in low-cost devices, was presented. This new technique can be used with the standard multilevel topologies such us diode-clamped, flying capacitor, cascaded full-bridge or even hybrid converters. That new modulation algorithm is valid for any number of phases and consequently it can be applied to three-phase converters 3.1 MULTILEVEL MULTIPHASE SVPWM ALGORITHM In multiphase converters the space vector PWM is a multidimensional problem where the vector selection can be carried out directly in a multidimensional space. In the modulation problem of a P-phase converter is formulated in a P-dimension space and it is solved for multilevel topologies in which the output level of every phase is an integer multiple of a fixed voltage step Vdc , such as flying capacitor, diode-clamped, cascaded full- bridge or hybrid converters. The solution is an algorithm based on a displacement plus a two-level multiphase SVPWM modulator that is valid for any number of levels and phases. This multiphase modulation technique is able to handle all switching states of the inverter, without discard any one, and it provides a sorted switching vector sequence that minimizes the number of switching. In addition, the algorithm proves suitable for real- time implementation due to its low computational complexity. Since the switching states of any power converter topology stay at discrete states, the multilevel multiphase SVPWM technique is used to synthesize a reference voltage vector Vr by means of a sequence of space vectors during each modulation cycle. Each space vector vsj must be applied during an interval tj in accordance with the following modulation law. Vr = --------> (3.1) Where = 1 In which Vr =Vr/Vdc = [ , ........ ] -------- > (3.1.1) Is the normalized reference vector, which belongs to the P-dimension real space , vsj = [ , ........ ] are the switching vectors, which belongs to the integer space , and tj are the normalized switching times that correspond to each switching vector. If expressions in (3.1) are rewritten in matrix format the following system of linear equations. Which must be solved by the multilevel multiphase SVPWM algorithm is obtained. ---------- > (3.1.2) 151 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME The modulation problem solving requires searching a set of integer numbers for the coefficients matrix that permit to solve the linear system in order to calculate the switching times. As fig 3.1 shows, if the reference vector vr, is decomposed in the sum of an integer, vi, and a fractional part , vf, as vi = integ(vr) ε --------- > (3.1.3) vf = vr – vi ε ---------- > (3.1.4) then the modulation law in (3.1.2) can be solved by means of a two – level multiphase modulator where the reference vector is vf --------- > (3.1.5) The solution of this new system of equations is the sequence of displaced switching vectors, vdj = [ , ........ ] that approximate the reference vf. The elements of the multilevel switching sequence, vsj, can be obtained from this two level switching sequence by adding the integer part of the reference to the displaced vectors. vsj = vi + vdj ---------------- > (3.1.6) The switching times tj of the multilevel algorithm are the same as the switching times of the two –level algorithm. Fig: 3.1 Block diagram of the multi level Fig 3.1.2 Block diagram of the two Multi phase SVPWM level multiphase SVPWM Fig 3.1.2 shows the block diagram of the two level multiphase space vector PWM algorithm. This algorithm searches a coefficient matrix 152 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME D= ------------ > (3.1.7) That permits to solve the linear system in (3.1.5) in order to calculate the switching time. This matrix can be calculated by means of D= D --------------- > (3.1.8) Where D= ------------- > (3.1.9) And P is a permutation matrix that sorts the elements of the reference vector in descending order. P = ------------- > (3.1.10) Where vf = [ , ........ ] is the sorted vector in which 1> ≥...........≥ ≥ ≥........ ≥0 ----------> (3.1.11) Finally, the switching times can be calculated from vf as tj = ------- (3.1.12) Fig 3.1.3 Multi level multiphase SVPWM ALGORITHM flow chart 153 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME Steps Involved In the Algorithm Which are summarized in the flow chart fig 3.1.3 are 1) Calculate normalized reference vr. from the reference voltage vector using the expression in (3.1.1) 2) Decompose the normalized reference into the sum of its integer part vi and its fractional part vf by means of(3.1.3) and (3.1.4) respectively 3) Calculate the permutation matrix P that sorts the vector vf in descending order in accordance with (3.1.10) and (3.1.11) 4) Rearrange the row of the triangular matrix D in order to obtain the matrix D by means of (3.1.8) 5) Extract the displaced switching vector. vdj from the matrix D by taking into account the expression in (3.1.7) 6) Obtain the final switching vector, vsi by adding the integer part of the reference, vi to the displaced switching vector vdj according to (3.1.6) 7) Calculate the time corresponding to each switching vector from components of the vector vf by means of expression in (3.1.12). Finally, trigger signals have to be generated from the switching vectors and the switching times. The relationship between switching states and the particular trigger signals of transistors depends on the multilevel topology. 3.2 FIVE PHASE FIVE LEVEL CASCADED MULTI LEVEL INVERTER Multiphase multilevel inverters are controlled by this hybrid modulation (SVPWM) to provide multiphase variable voltage and variable frequency supply. The proposed modulation inherits the features of fundamental frequency modulation and carrier based space vector modulation strategies. The main characteristics of this hybrid modulation are the reduction in power losses, and effectively improve harmonic performance. This algorithm can be applied to cascaded multilevel inverter topologies. It has low computational complexity and it is suitable for hardware implementations. Theoretical considerations are detailed using a five phase multilevel inverter. The performance of this hybrid modulation (SVPWM) is analyzed based on power loss, weighted total harmonic distortion, the linearity and it is compared with standard modulation strategies. Fig: 3.2 Schematic diagram of the Fig: 3.2.1 Power circuit configuration Five phase multilevel inverter topology For One phase leg 154 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME The power circuit for a five-phase five-level cascaded inverter topology is shown in Fig 3.2.1. Modulation control of multiphase multilevel inverter is quite challenging, and much of the reported research is based on somewhat heuristic investigations. Most of the available work on PWM schemes for a multiphase voltage source inverter either covers carrier-based PWM or space vector PWM schemes. By and large, the emphasis has been placed on space vector PWM (SVPWM) methods. SVPWM offers great flexibility to optimize switching waveforms and is suited for digital implementation. However, due to constant sampling rate used in SVPWM, the equivalent carrier- based techniques have been developed. Carrier-based space vector modulation (CBSVM) is appropriate for inverters with more than five levels, where the computational overhead for conventional SVPWM is exceeding due to many output states a new hybrid modulation technique is presented to address the reduction of power losses in multiphase multilevel inverter, with improved harmonic performance. IV. SIMULATION OF FIVE LEVEL FIVE PHASE INVERTER Fig: 4.1 simulation diagram for five level five phase cascaded full bridge inverter by using SVPWM The above simulation represents the simulation diagram of five phase five level cascaded full bridge inverter. The operation of the blocks Multilevel multiphase SVPWM and Two-level multiphase SVPWM. It includes a five-level five-phase inverter feeding a passive load. 155 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME Fig: 4.2 simulation circuit for sequence block The above simulation represents the subsystem of the sequence block. The Sequence block provides the time sequence of switching vectors. The output of the sequence block is connected to the triggering signal. The Trigger signals generates the proper trigger signals from output levels specified in each switching vector. Fig: 4.3 simulation circuit for triggering signal The above diagram represents the subsystem of the triggering signal. The input of the triggering signal taken from the sequence block. 156 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME Fig: 4.4 simulation circuit for 5 level 5 phase cascaded full bridge inverter The above diagram represents the subsystem of the five phase five level cascaded full bridge inverter. The 5-level 5-phase cascaded full-bridge inverter block is the ideal model of the multilevel voltage-source converter. The loads are resistances with a series connected inductances. Load neutral is connected to the inverter neutral. Fig: 4.5 output waveform of five level five phase cascaded full bridge inverter 157 International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print), ISSN 0976 – 6553(Online) Volume 4, Issue 4, July-August (2013), © IAEME The above simulation output represents the output waveform of five level five phase cascaded full bridge inverter. The scope 1 represents the reference voltages Vref of five phases. The phase shift between each phase is 72˚. The scope 2 represents the filtered output voltage which is taken from the low pass filter. The filter is used for eliminating the harmonics. The scope 3 represents the inverter output. V. CONCLUSION In this five phase five level we are using the cascaded multilevel inverter topology. Multilevel technology permits the achievement of high power ratings with voltage limited devices. With the cascaded multi level inverter reaches the higher output voltage and power levels and higher reliability due to its modular topology. Here a new space vector pulse-width modulation algorithm for multilevel multiphase voltage source converters with low computational cost has been presented. This algorithm can be used with any number of phases; therefore it can be also used with classical three-phase topologies. The SVPWM algorithm provides a sorted switching vector sequence that minimizes the number of switching’s. The SVPWM algorithm proves suitable for real-time implementation due to its low computational complexity. VI. REFERENCES [1] Oscar Jacobo Alvarez, Jesus Doval-Gandoy and Franciso D.Freijedo “Multilevel Multiphase Space Vector PWM algorithm”,IEEE® Transactions on Industrial Electronics, vol. 55, no. 5, pp. 1933-1942, May 2008, doi:10.1109/TIE.2008.918466 [2] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R.Portillo, and M. A. M. Prats, "The age of multilevel converters arrives," IEEE Ind. [3] G. S. Perantzakis, F. H. Xepapas, and S. N. Manias, “A new four-level PWMinverter topology for high power applications-effect of switching strategies on losses distribution,” in Proc. PESC’04, Aachen, Germany, 2004, pp. 4398–4404. [4] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, “A new multilevel PWM method: a theoretical analysis,” IEEE Trans. Power Electron., vol. 7, no. 3, pp. 497–505, Jul. 1992. [5] J. S. Lai and F. Z. Peng, “Multilevel converters-a new breed of power converters,” IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509–517, May/Jun. 1996. [6] S.M.Padmaja and Dr. G. Tulasi Ramdas, “SVPWM Based 3-Level Statcom for Reactive Power Management Under Line-Line Fault in a Transmission Line”, International Journal of Electrical Engineering & Technology (IJEET), Volume 4, Issue 3, 2013, pp. 167 - 187, ISSN Print : 0976- 6545, ISSN Online: 0976-6553. [7] Pradeep B Jyoti, J.Amarnath and D.Subbarayudu, “The Scheme of Three-Level Inverters Based on SVPWM OverModulation Technique for Vector Controlled Induction Motor Drives”, International Journal of Electrical Engineering & Technology (IJEET), Volume 4, Issue 2, 2013, pp. 245 - 260, ISSN Print: 0976-6545, ISSN Online: 0976-6553. [8] B.KiranKumar, Y.V.Sivareddy and M.Vijayakumar, “Comparative Analysis of Sine Triangle and Space Vector PWM for Cascaded Multilevel Inverters”, International Journal of Electrical Engineering & Technology (IJEET), Volume 4, Issue 2, 2013, pp. 155 - 164, ISSN Print: 0976-6545, ISSN Online: 0976-6553. [9] Dr. Hina Chandwani, Himanshu N Chaudhari and Dhaval Patel, “Analysis and Simulation of Multilevel Inverter using Multi Carrier Based PWM Control Technique”, International Journal of Electrical Engineering & Technology (IJEET), Volume 4, Issue 3, 2013, pp. 200 - 208, ISSN Print: 0976-6545, ISSN Online: 0976-6553. 158