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A POWER-GATING SCHEME FOR IMPROVRED

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A POWER-GATING SCHEME FOR IMPROVRED Powered By Docstoc
					International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
         INTERNATIONAL JOURNAL OF ELECTRONICS AND
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME
 COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)

ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)                                                       IJECET
Volume 4, Issue 4, July-August, 2013, pp. 79-85
© IAEME: www.iaeme.com/ijecet.asp                                            ©IAEME
Journal Impact Factor (2013): 5.8896 (Calculated by GISI)
www.jifactor.com




                   POWER-GATING SCHEME FOR IMPROVRED
                              CAL CIRCUITS

             R.GUNA SEKHAR1                                    K.D.MOHANA SUNDARAM2
   Assistant Professor, Department of ECE,                  Assistant professor, Department of ECE
               SVPCET, puttur.                                          SVPCET, puttur.

              C.MANIKANTA3                                               K.SARITHA4
   Assistant professor, Department of ECE                   Assistant professor, Department of ECE
               SVPCET, puttur.                                          SVPCET, puttur.


ABSTRACT

        This paper presents a power gating technique for improved CAL (clocked adiabatic logic)
circuits to minimise the energy loss of adiabatic circuits during idle periods. Transmission gate is
used as power gating switch, which is inserted between single phase power clock and virtual power
clock. Power gating switch disconnects the power gated cal logic blocks from single phase power
clocks during idle periods. 8-bit carry-look ahead adder based on improved CAL circuits used to
verify power gating technique. It consists of a power gating CAL AND gate, power gating CAL OR
gate, power gating CAL XOR gate. The energy dissipation is greatly reduced by shutting down the
idle power gating CAL blocks. With the help of Mentor Graphics simulations, the energy dissipation
is analyzed.

INDEX TERM: Power Gating Switch, CAL (clocked adiabatic logic), and Energy Dissipation.

1. INTRODUCTION

        Reducing power dissipation is design objective for any VLSI device. Since excessive power
dissipation results in increased packaging and cooling costs as well as potential reliability problems
[2] adiabatic logic uses AC voltage supplies to recycle the energy of the circuits instead of being
dissipated as heat. There are many adiabatic logics which uses multi phase power clock those are
ECRL (Efficient Charge Recovery Logic), PAL-2N (Pass Transistor Adiabatic Logic with NMOS
pull down configuration), etc., The problems with these techniques are power clock tree, clock skew
and addition of multi phase power clock generator that increases the power dissipation, the multi-
phase power clock tree results in extra area over head and increases the complexity of layout place
and route. A few adiabatic logic families have been reported which uses single phase power clock[1].
These have simple clock generator than the multi phase schemes TSEL(True Single Phase Energy
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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME

Recovery Logic) and SCAL(Source Coupled Adiabatic Logic )use single phase power clock. The
CAL circuits also use a single phase power clock by introducing a auxiliary clock signal.
  CAL [3] has a simple structure so complicated circuits can be realized easily. In adiabatic circuits
energy dissipation happens even for constant input signal because output nodes are always change
and discharged by power clocks. This limits the energy saving of adiabatic circuits.

2. CAL (CLOCKED ADIABATIC LOGIC)

         The basic CAL [3] circuit is as shown in the figure it consists of 2 main parts: logic evolution
circuit (N5 and N6) and the energy recovery circuit (P1 and P2). In order to realize an adiabatic logic
functions with a single phase power clock, auxiliary timing clock Cx has been introduced. This
signal controls transistor (N3and N4) which are in series with logic tree represented by N5and
N6.The Cx enable device N3 and N4 allow operation with single phase power clock.N5 and N6
NMOS transistor can be replaced with NMOS logic trees to realize any logic function. Conventional
CAL logic buffer which uses square wave for auxiliary clocks are shown in figure.




                                       Fig .1 Basic CAL Buffer




                              Fig .2 Operation Waveform of CAL Buffer


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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
                                                                July August
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME

3. IMPROVED CAL CIRCUITS

        Auxiliary clock [1] Cx and Cxb use square wave in conventional CAL circuits as shown in
figure. Thus operation for gates of the transistors (N3 and N4) does not work in an adiabatic manner.
                                                                                            dissipation
For large functional block, transistors (N3 and N4) will cause an increase in the energy dissipa
                                                               lines.In
due to large switching capacitance on auxiliary clock lines.In improved CAL circuits non          non-
overlapping sinusoidal signals are used for the auxiliary clocks Cx and Cxb as shown in figure.
                                                              generator
Hence it is possible to recycle the charge of auxiliary clock generator are shown in figure. The clock
uses the same sinusoidal power clock. The charge of auxiliary clock nodes are well recycled in
improved CAL circuits by using non overlapping sinusoidal clocks. However auxiliary clock
                                   ergy
generators introduce additional energy dissipation which should minimize.




                                  Fig .3 Auxiliary Clock Generators




                                        .
                                    Fig .4 Simulation Waveform




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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME

4. POWER GATING TECHNIQUE FOR IMPROVED CAL CIRCUITS

        In order to reduce the energy loss during idle periods, the power gating technique is
introduced to adiabatic circuit by switching of their power clocks. A transmission gate is used as the
power gating switch [5] which is inserted between single phase and virtual power clock.
        It disconnects the power gated CAL [3] logic block and auxiliary clock generator from the
single phase power clock during the idle periods. NMOS transistor (NC) prevents the floating state
of virtual power clock in sleep mode. When power gating control signal (Active) is high, clk signal
follows the power clock(PC), this mode of operation is called active mode. In sleep mode, active is
low, clk signal goes to low level, so that the power gated CAL [6] logic blocks and auxiliary clock
generator disconnected from the PC to reduce the energy dissipation. Power gating switches
introduce additional energy loss that should be analyzed and minimized.

4.1. 8-BIT CARRY –LOOK ADDER BASED ON IMPROVED CAL CIRCUITS WITH POWER GATING
SCHEME
        8-bit Carry –Look Adder Based on improved CAL circuits with power gating scheme is
shown in figure. 8-bit consists of six pipeline stages. Six Power Gating switches [4] are inserted
between power clock and virtual power clocks.
        The logic gates are realized in CAL logic by replacing (N5 and N6) transistor with NMOS
pass transistor logic block in CAL buffer. To achieve proper power gating timing, 6 auxiliary clock
generators are used to generate auxiliary clocks for the 6 pipeline stages as shown in figure
4(a)shows energy dissipation per cycle of the improved CAL 8-bit carry –look ahead adder without
and with power gating technique.




                           Fig .5 Realization of AND gate based on CAL




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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME




 Fig .6 Realization of OR gate based on CAL        Fig .7 Realization of XOR gate based on CAL




Fig .8 8-bit Carry Look Ahead Adder based on Improved CAL circuits with Power Gating Scheme



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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
                                                                July August
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME

5. RESULTS




       Fig .9 Energy dissipation of Improved 8
                       ssipation             8-bit CAL Adder with and without power gating


6. CONCLUSION

                        y
        In this paper by introducing power gating scheme for CAL adiabatic logic, energy dissipation
is reduced in large extent. In this paper power gating technique is introduced for the improved CAL
circuits. Since it is easy to switch of single phase power clock than multi phase power clock, power
gating schemes attains greater energy saving.

REFERENCES

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[5]    W. C. Athas, J. G. Koller, and L. J. Svensson, “An energy efficient CMOS line driver using
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[7]    R. T. Hinman and M. F. Schlecht, “Power dissipation Measurements on recovered energy
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[9]          Power
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[12]                                                                  Mahore The
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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 4, July-August (2013), © IAEME

[13]     A.Andamuthu,R. Shankar and J. Vinoth Kumar “Design Of Power Efficient 4x4 Array
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[14]     Praveer Saxena, Swati Dhamani, Dinesh Chandra, Sampath Kumar V, “Modified Two Phase
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AUTHOR’S PROFILE

       1. GUNA SEKHAR R

                             GUNA SEKHAR obtained a B.Tech. degree in Electronics and
                      Instrumentation Engineering from Sree Vidyanikethan Engineering College,
                      Tirupathi, India, in 2009, and the M.Tech. degree in VLSI Design engineering
                      from the VIT University at Vellore, India in 2012. Currently, he is working as
                      Assistant professor in SVPCET College at Puttur.


       2. K.D. MOHANA SUNDARAM

                             Mohana Sundaram received his B.Tech degree in Electronics and
                      Communication Engineering from Sri Venkateswara College of Engineering
                      and Technology, Chittoor, India in 2008, and M.Tech Degree in VLSI Design
                      Engineering from SIETK, PUTTUR, 2012. Currently he is working as
                      Asst.Professor in SVPCET, Puttur, India.



       3. CHINTALA MANIKANTA

                                CHINTALA MANIKANTA received M.Tech degree with
                        specialization of embedded systems from SIETK, PUTTUR under JNTUA.
                        Presently he is working in SVPCET, puttur he is joined this institution in
                        2013 as Assistant Professor in the department of ECE.




       4. K SARITHA
                               K SARITHA obtained B Tech in the college of sree vidyanikethan
                        engineering college and M Tech in VLSI Design from SIETK, PUTTUR,
                        2011.presently she is working in svpcet ,Puttur with working experience of 3
                        years.




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