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					   Formal Methods for System Level Performance
            Analysis and Optimization




Simon Schliecker                      Wimi Treffen
                                          16.6.08
Outline

• SYMTA VISION:

  ”Hot Topics in Automotive Network Evolution”


• IDA:

  “Formal performance modeling and analysis principles
  for Multicore”




                                         Simon Schliecker – 06.06.2008   2
SYMTA VISION

 p   Founded May 2005
 p   Spin-Off from Braunschweig University, Germany (Prof. Ernst)
 p   Focusing on real-time systems for over 10 years
 p   12+ staff and growing

 Expertise
 p Real-time system design and integration
 p Timing verification and performance optimization for
    ¨ ECUs
    ¨ Buses
    ¨ Networked systems
 p Technology: scheduling analysis, symbolic simulation, optimization
 p Tool: SymTA/S (Symbolic Timing Analysis for Systems)


                                                 Symtavision Overview, May 2008
                                                 © Symtavision GmbH, Germany
Customers – Partners – Networks




                                  Symtavision Overview, May 2008
                                  © Symtavision GmbH, Germany
Why SYMTA VISION


 Electronic Complexity
 p Hundreds of functions,
    many safety-critical
 p 50+ ECUs
 p Networked
 p Heterogeneous
 p Many suppliers

 Integration challenges                             55 ECUs, 7 Buses

 p Reliability, quality, safety
 p Extensibility
 p Time to Market
 p Development and production cost
                                                               Skip architecture
                                     Symtavision Overview, May 2008
                                     © Symtavision GmbH, Germany
Automotive Electronics Evolution

 p Adding new components to existing architecture
    ¨ Software functions
    ¨ ECUs
    ¨ Subsystems




                                               Symtavision Overview, May 2008
                                               © Symtavision GmbH, Germany
 Challenge Timing Analysis including End-to-end

e.g.: Source à ECU1   à   CAN à Gateway à FlexRay à ECU2 à Sink




                                             Symtavision Overview, May 2008
                                             © Symtavision GmbH, Germany
Automotive Electronics Revolution?
 p Novel topology
 p Restructuring, higher integration of functions
   (e.g. small number of powerful domain control units - DCUs)
 p Becomes feasible with AUTOSAR and FlexRay
 p Selecting optimized architectures becomes key

                                          FlexRay Backbone



                   DCU1             DCU2                   DCU3                      DCU4

             Act                 Sens                Sens                          Act
                          Act                 Sens                  Act                            Sens

             Sens                Sens                Act                          Sens
                          Sens                Sens                  Sens                           Sens

             Sens                Sens                Sens                          Act



                    LIN                 LS-CAN              ???                          FlexRay



                                                                  Symtavision Overview, May 2008
                                                                  © Symtavision GmbH, Germany
Revolution Co-Enabled by High-Performance Multi-Core ECUs

 Typically Dual-Processor / Dual-Core ECUs
 p Exploring alternative Hardware/Software architectures
 p Migration from Prototype to series ECU
 p new challenge: Integration of functions and communication from multiple
    sources

                           funct 001         funct 101          funct 201                 OEM developed
                           funct 002         funct 102          funct 202                 Co-developed
                           funct 003         funct 103          funct 203                 Supplier developed
                           funct 004                            funct 204
                                                                funct 205


            Sensor
                                            CPU1                  CPU2
            Cluster                                       SPI


                                Video
                              processor   Bus CTRL
           Actuators
                                            Bus CTRL
           Indicators                          Bus CTRL



                        CAN HS
                          CAN LS
                               …
                                                                     Symtavision Overview, May 2008
                                                                     © Symtavision GmbH, Germany
Symtavision Contribution to

p   Development of a Timing Model
p   AUTOSAR OS scheduling analysis
p   SW-component integration and scheduling
p   System-level timing budgeting, analysis, optimization
p   for key steps of AUTOSAR methodology:
                                    scheduling
                                     decisions




                   mapping
                   decisions



                                     figure taken from AUTOSAR Website
                                                          Symtavision Overview, May 2008
                                                          © Symtavision GmbH, Germany
AUTOSAR System Timing Aspects

   ECU1               Sensor
                       SWC
                                                   ECU2                          SWC-1
                                                                                                        Actuator
                                                                                                         SWC



          RTE                                                              RTE
          BSW                                                              BSW




           Sensor                    Signal Path / Data Flow                                                       Actuator



                                                   INTER-ECU                              INTRA-ECU
                                  Sensor                                                               Actuator
Sensor                             SWC
                                                                                 SWC1
                                                                                                        SWC                            Actuator
                                              communication
                                                                                         communication

          I/O                                            CAN                                                                   I/O




                                                                                                                         BSW
                                                               BSW




                                                                                                                   RTE
                                                                                              RTE
                                                                     RTE
                                             RTE
                    BSW




                                                   BSW
                          RTE




   Sens                         Sensor SWC                                       SWC1               Actuator SWC                      Act

HOPs




                                      timing chain segments

                                                                                            end-to-end timing chain

                                                                                                     Symtavision Overview, May 2008
                                                                                                     © Symtavision GmbH, Germany
Commercial Application of Performance Analysis

Application: Active Front Steering
p Safety critical function
p Formal Performance Analysis performed to
   ¨ sensitivity analysis of previous product
   ¨ deadline verification of all functions
p Analysis with commercial SymTA/S tool
   ¨ Data import from ECU traces
                                                                                 Source: BMW
p Result:
   ¨ reliable performance
   ¨ cost savings (use of smaller CPU)




                                                Symtavision Overview, May 2008
                                                © Symtavision GmbH, Germany
Outline

• SYMTA VISION:

  ”Hot Topics in Automotive Network Evolution”


• IDA:
  “Formal performance modeling and analysis
  principles for Multicore”




                                         Simon Schliecker – 06.06.2008   13
Application Domains for Formal Performance Analysis
                                  Distributed Systems
         Mem       Mem

 HW     CPU1      CPU2       HW
         T1        T2




• Automotive systems consists of a large set of distributed
  functions
      – 55 ECUs
      – 7 Buses of 4 types
      – several Gateways
• Formal methods are used in different phases of the
  design
• What’s so different in for Multicore?

                                            Simon Schliecker – 06.06.2008   14
Application Domains for Formal Performance Analysis
                                 Distributed Systems
      Mem    Mem

 HW   CPU1   CPU2     HW
      T1     T2




                       New integration issues:
                              Mem         Mem

                          Shared resources contention
                       • HW   CPU1        CPU2      HW
                            – Shared memory, coprocessors,
                                T1         T2

                            – Shared caches
                       •   Diverse interaction
                            – Message passing, shared memory,
                              resources, …
                                 Shared Memory
             MpSoCs    •   Multirate

                                             Simon Schliecker – 06.06.2008   15
Timing Model Hierarchy
              IP                M

                                            • system timing model
                                                  performance of
                                               •–“Compositionalcomponents
                                                  integrated in a network
        P          M        M           P        Performance Analysis”

                       T1           T2      • component timing model
        P
                            RTE                 – activation function
                            BSW                • symbolic simulation of
                                                – component
                                                 locally “critical instance”
                                                   scheduling/arbitration
 activation            *            *

                                            • task timing model
                       T1           T2             execution load estimate
                                               •–early phases: and timing
                                               •–later: e.g. simulateand timing
                                                   communication load


                                                               Simon Schliecker – 06.06.2008   16
System analysis using compositional approach
  • independently scheduled subsystems are coupled
    by data flow

      comp 1                          comp 2
               P1                                  P3

        P2                              P4
         scheduling                      scheduling
         comp 1       event streams      comp 2


 Þ subsystems coupled by streams of data
    Þinterpreted as activating events
 Þ coupling corresponds to event propagation


                                             Simon Schliecker – 06.06.2008   17
Compositional Analysis Loop – SymTA/S

              environment model

            input traffic description


                 local analysis


            output traffic description

              until convergence or
               non-schedulability


                                        Simon Schliecker – 06.06.2008   18
Competition for shared resources in MpSoCs

• In MpSoCs, tasks may share “secondary“ resources
  throughout the system
   –   Shared memory
   –   Coprocessors
   –   Blocking for logically / physically shared resources
   –   Synchronization through shared memory

                                         Mem         Mem

                                         CPU1        CPU2            HW
                                  HW
                                          T1         T2




                                          Shared Memory


                                                      Simon Schliecker – 06.06.2008   19
  MpSoC process execution
                                   memory
classical        read data         accesses
process
model                                             output data


process model
w/ memory
access     network
               memory                                                          Memory
                                                                               transaction
considering
system
interference
       network
       arbitration                                                                     …
       memory
       arbitration           transaction      transaction     transaction
                                time 1           time 2          time 3
                                                            Simon Schliecker – 06.06.2008    20
Improved combination in transaction modeling
  • complex and highly dynamic interactions if memory
    transactions of multiple processors interfere
     – simple combination not sufficient
Solution:                                              core execution time

• derive upper total                           core communication time +
                                               total netw. interference
  interference
                                               core memory access time +
  bound using                                  total mem. interference
  formal analysis
• superimpose on each core                 +   +      +        +
   ® total execution time
     (conservative)                  ≥ total worst case execution time
• couple single core analysis
  with iterative nested scheme
   ® enhanced SymTA/S analysis

                                                   Simon Schliecker – 06.06.2008   21
Extended Analysis Loop

                     environment model

                   input traffic description

 Shared resource        local analysis
 access analysis       (WCET + WCRT)

                   output traffic description

                     until convergence or
                      non-schedulability


                                   Simon Schliecker – 06.06.2008   22
Conclusion

• System level performance analysis for heterogeneous
  embedded multiprocessor systems has grown beyond
  the stage of toy examples
• In automotive, current challenges are in “power
  components” that trigger topological evolution
• The technology is applicable both to large scale
  distributed systems and for MpSoC




                                         Simon Schliecker – 06.06.2008   23

				
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