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VLSI PRD 1- Complex Number Multiplier

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					 Final Project Report

Multipliers and Adders



            John Ogembo
            Zach Smith
Outline
l   The multipliers and adders

l   Goals and Specifications

l   Design Process

l   Simulation and Timing Diagrams

l   Achieved Design Specification

l   Conclusion
Multipliers and Adders

l Spatial      Filter
l   Correlator
l   Matched Filter
Spatial Filter

l   No pipelining
l   Includes two multipliers
    with overflow detect
Multipliers and Adders

l   Spatial Filter

l Correlator
l   Matched Filter
Correlator

l   Includes two 8 by 1
    multipliers, 2s
    complement form
l   Two 8-bit adders
l   Three pipelining
    registers
8 bit adders
Multipliers and Adders

l   Spatial Filter
l   Correlator

l Matched            Filter
Matched Filter

l   Four 8 x 8 multipliers
l   Two adders with
    overflow detect
l   Three pipelining
    registers
Adders – 16 bit overflow
Goals and Design Specifications

l   Working chip
l   Target speed: 100 MHz
l   Fixed point integer
l   2’s complement format wherever signed
    numbers are used
l   16 bit vector Complex Numbers for Matched
    Filter
Design Process

•   4 Multipliers
•   2 Adders
•   5 pipelining registers

          Small       Large

Input     2 x 8-bit   2 x 16-bit

Output    8-bit       16-bit
Initial Multiplier Design

Advantages:
l Size, power


Disadvantages:
l Slow
l Multiple clock cycles to
  perform operation
l Complicated to debug
New Multiplier Design
l   8 bit input Multiplier

l   Single cycle

l   Uses Cells


l   To take care of
    overflow, an overflow
    detector was added as
    shown below
Multiplier Signal propagation

l   Signal propagates
    all the seven cells

l   Signal take .61ns
    in each cell
Cell Timing

l   Timing diagram of
    a single cell
Multiplier Timing Diagram

l This is the worst-
  case scenario
  timing of the
  multiplier,
   01111111
 x 01111111
This takes 9 ns
8 bit Adder

l   Implemented using
    carry look ahead

l   This eliminates the
    carry delay speeding
    up addition
Addition Problem

Problem: It is impossible to tell the sign of any
  output from the adder. This is needed to
  determine the sign of the default overflow
  output

Solution: Use logic based on the inputs and
 outputs to determine the sign of the output
Addition Problem (example)

Notice:

 0000      0       0111 7
+1110     +(-2)   +0111 +7
=1110     = -2    =1110 =14
Adder With Overflow

l   This adder performs:
l   if S > 0111,(max)
    S = 0111 (7)

l   If S < 1000 (min)
    S = 1000 (-8)
Substractor Timing Diagram

l Worst scenario:
Operation of (-1)-(-1) = 0

This takes 7.8 ns
Small

l   2 x 8 bit input
l   8 bit output
l   12 test pins
Flat

l   Same as previous,
    flattened
l   Used for layout
Layout

l   Reduced
    design
    layout
Padframe

l   Padframe for
    our design

l   Utilizes 39
    pins with one
    pin with no
    connection.
Achieved Design Specification

l   Clock speed of 100 MHz
l   Correctly multiplies signed, fixed-point,
    complex integers.
Conclusion

l   Correct functionality of the overall design and its clear
    verification is crucial to progress on the project.

l   The theoretical results remain tentative until simulations
    can verify that the design meets specifications.

l   DRC and LVS verification was performed on the layout
    and both passed this initial test thereby verifying the
    correct-to-spec functionality of the design.
Questions



l   Pad frame DRC check
l   How to implement
    hierarchical automated
    layout

				
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posted:7/26/2013
language:English
pages:29