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Programmable Elements and Their Impact on FPGA Architecture

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					 Programmable Elements and
    Their Impact on FPGA
Architecture, Performance, and
     Radiation Hardness
         John McCollum



                1         B0
               Gate Array
• A Gate array consists of wires and Logic
  Gates - typically a 2 input NAND gate.
• The Key point here is UNCOMMITTED
  WIRING.
• This takes four masks to manufacture the
  typical Gate Array.



                        2              B0
Wires




   3    B0
 FPGAs must add some kind of
switch to the equation to be user
         programmable.

• The size and performance of the switch
  essentially determines the architecture
• ULM (Universal Logic Module) must be as
  small as possible to maximize versatility
  and utilization


                       4             B0
                 The Switch
• There are four kinds of switches
  –   EPROM brought to us by Altera
  –   The SRAM brought to us by Xilinx
  –   Antifuse brought to us by Actel
  –   Flash brought to us by Actel




                          5              B0
                   EPROM
• Strengths              • Weaknesses
  – Mainstream                – requires high voltage - 1
    Technology                  generation behind
  – Reprogrammable              SRAM
  – 100% testable             – requires programmer
  – non-volatile              – requires socket
  – software is simple        – high impedance 80uA/
                                minimum gate (12K
                                ohm)
                              – impact ionization limits
                                voltage across the device

                          6                      B0
                  Impact Ionization
                    Inversion Layer

     Gate Oxide                        Gate
                     Source                              Drain

                                                       n-Substrate

                                                     Depletion Layer


                                                                 p-Substrate

                                      Back Contact




Electrons accelerated to 3.2eV in the high field region of
the drain will enter the gate oxide conduction band




                                          7                                    B0
Hence PLDs




     8       B0
PLD + Wire = CPLD




         9          B0
Programmable Interface Array




              10         B0
           CPLD Summary
• Constant delay
• Shallow logic
• great for combinatorial logic , but not
  sequential logic
• less than 5000 gates
• Marginal radiation tolerance due to erasure
  ~20K Rads
• Can suffer SEGR during programming
                        11              B0
                           • Weaknesses
                             – Largest Area element using
  SRAM                         5 to 6 transistors plus switch
                               = 30u2 per node @ 0.25u
• Strengths                  – switch is medium
  – Base logic process -       impedance - 3k/ohms per
    so it uses leading         square (500uA/micron)
    edge processing          – high capacitance -1.6 fA per
  – Re-programmable            micron/ per node @ 0.25u
  – 100% testable            – volatile
  – no programmer            – requires external memory to
  – No socket                  load
                             – designs easily copied
                             – dead until loaded
                             – soft ware is difficult
                             12                    B0
     Wires are Very Expensive

• Since the switch is large and slow the
  module must be large so as to minimize
  interconnect ~ 20 gates.
• The logic module must be symmetrical so
  all inputs are the same to minimize wires.
  Hence the 4X4 RAM array affectionately
  known as the 4 input LUT (look up table).


                        13              B0
LUT




  14   B0
Altera 10K Chip




        15        B0
  The SRAM with Lots of Metal

• The SRAM FPGA has benefited the most
  from 5 and 6 layer metal due to the wiring
  complexity of flip flops. This has also
  altered the optimum module to 2X3 LUT
  and to hierarchical designs.



                        16              B0
Actel SRAM Architecture




            17        B0
18   B0
      New Module

• Efficient hierarchical routing
  has allowed the LUT - 4 to
  be broken in to a 2:1 to mix
  of LUT 3 and LUT2.




      19                B0
     SEU problem for SRAMS
• Basically a six megabit configuration
  SRAM will have driver contention if a bit
  flips - hence the bit error rate must be in the
  10-14 rate. A very difficult task.
• Typical resistor approaches to harden
  SRAMs are in the range of 10 -10
• Still Actel is developing devices that have
  some level of radiation tolerance.

                         20               B0
       Antifuse Advantages
– Highest density - a           – Nearly impossible to
  mere cross point - 10X          reverse engineer
  the density of SRAM           – Radiation hard
– Lowest switch                 – Live with in 1
  resistance - 25 Ohms            millisecond of the
– Very low capacitance 1          power supply reaching
  fF per node.-                   spec voltage
  approaching the metal         – Software is easy to
  line capacitance                place and route
– non- volatile


                           21                   B0
           Antifuse Disadvantages
– Requires programmer
– Requires a socket - a            – ONO antifuses require less
   • problem for devices with >
                                     only 5mA needed so can
     200 pins                        be programmed from the
   • solved with BGA                 edge
– Those who design by test         – Some antifuse defects not
  will throw out a lot of parts.     testable until programming
– Requires one to two                - hence only 98% to 99 %
  transistors per wire for           programming yield - but
  programming ~ 10mA for             100% functional
  Metal antifuses.
                                   22                  B0
          Antifuse Architecture
• Since wires are relatively cheap
  –   Modules can be smaller - 3.5 real gates
  –   Non-symmetrical hence MUX based logic
  –   About 30 antifuses per input
  –   Add a flip flop
  –   Routing is very similar to Gate Array



                           23              B0
ONO Antifuse FPGA Layout




            24        B0
ACT 1 MODULE
Note Isolation Transistor




             25             B0
Metal to Metal Antifuse




            26            B0
Metal to metal antifuse moved the antifuse out of
silicon making the part denser and faster


                          27                   B0
                   SX Routing Efficiency
• Faster Signal Propagation than SRAM FPGA
    –      Signals travel through more interconnect in SRAM
    –      Interconnect dominates delays in deep sub-micron
    –      Antifuse architecture uses minimum silicon area
    –      SRAM needs silicon overhead for interconnect
                    M3                             M3
Antifuse

               M2        M2               M2      M2   M2    M2


               M1        M1             M1   M1   M1   M1   M1        M1


           Logic          Logic   Logic      SRAM SRAM                 Logic

                                   28                            B0
         A54SX Logic Element
 Combinatorial Cell                     Register Cell

D0                                                      PSETB
                                               DIN S1
D1                                        S0
                           Y                                     Y
D2                                                      D    Q
D3                              DC IN
           Sa         Sb
                                HCLK


DB                             CLKA,
                               CLKB
        A0 B0    A1 B1                    CKS     CKP   CLRB




                               29                       B0
SX-A = Lower Power




         30          B0
          Antifuse Radiation
• The interconnect is out of the silicon
• Actel has hardened the Antifuse against
  SEDR
• The antifuse configured MUX based logic
  module is not susceptible to change
• The customer can make radiation tolerant
  flip flops out of combinatorial logic cells
• Actel is hardening the Flip flop
                        31               B0
           Flash Architecture
• Fundamentally similar device to EPROM
  but device scaling has brought a new
  wrinkle
• since Vcc is now at 2.5 volts it is possible to
  use a floating gate as a switch (impact
  ionization)



                         32               B0
• Advantages                   • Disadvantages
  – Re-programmable in              – Requires high voltages
    the board                       – About the same speed
  – No socket                         as SRAM
  – Non-volatile                    – Radiation Hardness is
  – One transistor instead            expected to behave
    of 6 for routing control          similar to EPROM -
    - i.e. denser parts               has not been tested yet
  – Passes full Vcc without
    pump
  – Live at power up.
  – Difficult to reverse
    engineer


                               33                    B0
          SRAM Versus Flash
         Switch & Memory Size
SRAM based PLD              FLASH based PLD
           Switch
          & Routing
                                      Memory
                                       Cell




           Memory                      Switch
            Cell                      & Routing

                 7:1
                       34                 B0
              ProASIC Flash Switch
 FLASH        SWITCH                    SRAM              FLASH

               WORD LINE                       Switch
                                              & Routing
                                                               Memory
                                                                Cell
SEL 1 SEL 2



                                               Memory           Switch
                                                Cell           & Routing

                                           7 : 1 Advantage


                           •   Smaller Die
                           •   Less Power
                           •   Non-Volatile
                                  35                      B0
         ProASIC Basic Logic Cell

                                                      L7
                                     0                      1
         I8               L10
         (X3)                                         L11               YL
         Pin 4                       1                      0           (long)
                          L9
         Data        L8                                                 F2
                                                                        (local)


         I5               L4
         (X2)
         Pin 3
                          L5
         CLK         L6
                                L2   L0   L13    L3   L1 L15 L12 L14


         I2
         (X1)
         Pin 2
1 to 8   Set/Reset
gates



                                                36                     B0
                      D Flip Flop                   D
                                                    CLK
                                                    Set
                                                          Q




                                       L7

                      0                      1
           L10
                                       L11                    YL
D                     1                      0                (long)
           L9
      L8                                                      F2
                                                              (local)


           L4


CLK
           L5
      L6
                 L2   L0   L13   L3    L1 L15 L12 L14




SET




                                  37                      B0
                      ProASIC is
               1/3 Size of SRAM FPGAs


  Actel          Altera               Altera            Xilinx
 ProASIC      EPF10K100E           EPF10K100A         XC4062XL
  0.25µ          0.25µ                0.35µ             0.35µ
   3LM            5LM                  4LM               3LM
100K Total     100K Total           100KTotal         5,472 LEs
  Gates          Gates                gates
+ Memory       + Memory             + Memory           SRAM
  Flash          SRAM                 SRAM

   0.2              0.6                1.0               1.9
                                  Relative Die Size

         Source: Xilinx Website
                                        38                        B0
           Flash radiation
– Flash cells are usually in the 20K RAD Total
  Dose Range for typical 0.5u devices.
– MUX based Logic can not flip
– Part could be periodically refreshed to increase
  total dose.
– Could be reconfigured in space
– Programming in space can lead to SEGR - a
  calculated risk.


                         39                B0
     Relative Logic Density




40
                              Relative Size




B0
Relative Speed




       41        B0
Conclusion




     42      B0

				
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